CN106487342A - A kind of matrix power amplifier based on transistor stack structure - Google Patents
A kind of matrix power amplifier based on transistor stack structure Download PDFInfo
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- CN106487342A CN106487342A CN201610935636.4A CN201610935636A CN106487342A CN 106487342 A CN106487342 A CN 106487342A CN 201610935636 A CN201610935636 A CN 201610935636A CN 106487342 A CN106487342 A CN 106487342A
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- 238000010276 construction Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 6
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- 238000013461 design Methods 0.000 description 4
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Abstract
The invention discloses a kind of matrix power amplifier based on transistor stack structure, including the input matching network, power distributing network, stacking matrix amplification network, power synthesis network and the output matching network that are sequentially connected, and amplify, with the stacking matrix, the first biasing circuit and the second biasing circuit that network is symmetrically connected respectively.The power amplifier chip circuit realized by the present invention, the wide, power output of band is high, power gain is high, area is little.
Description
Technical field
The present invention relates to field-effect transistor radio-frequency power amplifier and integrated circuit fields, receive especially for ultra broadband
Send out a kind of matrix power amplifier based on transistor stack structure of the transmitter module application of machine end.
Background technology
With the fast development of the wireless communications market such as ultra-wideband communications, software radio, WLAN (WLAN), penetrate
Frequency front-end transceiver is also required that therewith and is developed to highly integrated, low-power consumption, compact conformation, cheap direction.
Radio frequency and microwave power amplifier, as the important module of emitter, are most electricity that consume energy in whole emitter
Road, its demanded power output are higher, electric with microwave power amplifier chip when radio frequency is realized using integrated circuit technology design
Lu Shi, its performance and cost receive certain restriction, are mainly reflected in following several respects:
(1) high-power high-efficiency amplifying power is limited:Development and the contracting of transistor size equal proportion with semiconductor technology
Little trend, the grid length of transistor are shorter and shorter, result in the reduction of breakdown voltage and the rising of knee-point voltage, so as to limit
Transistor drain output voltage swing, and then limit the power capacity of one-transistor.At present, typical solution be by
Multiple transistor (8 to 32) are arranged in parallel to carry out power combing, to improve power margin, but, this solution but because
This increased gate-source capacitance, reduce input impedance, increase the design difficulty of the impedance matching of input circuit, meanwhile, adopt
The optimal output load impedance of the crystal amplifier of this structure is very little, needs to enter by extra output impedance matching networks
The designing impedance matching of line output circuit, therefore, also increases the designing impedance matching difficulty of output circuit, meanwhile, using many
Individual transistor composite structure arranged in parallel will take very big chip area, so as to considerably increase chip production cost.
(2) ultra-wideband high power amplifying power is limited:In the design process of radio-frequency power amplifier, by transistor gain
The impact of bandwidth product, designer are always intended to be compromised between power amplifier bandwidth and the two indexs of power gain.Meanwhile, integrated electricity
Multiple transistors (8 to 32) for adopting in road structure for carrying out power combing arranged in parallel, realize in very wide frequency band 8 to
The power combing of the filter with low insertion loss of 32 amplification branch roads, and the Broadband Matching of the optimum load impedance of each branch, its design are difficult
Degree is very big.
At present, the circuit structure of common ultra-wideband high power amplifier has a lot, such as multichannel combining amplifier, and balance is put
Big device and distributed amplifier etc., want while the requirement for meeting parameters is very difficult, generally, its impedance matching
Realization is reducing the linearity, or increases what power consumption or chip area etc. were obtained for cost.
It can thus be seen that based on the ultra-wide band radio-frequency Designing power amplifier difficult point of integrated circuit technology being:(1) ultra-wide
Under band high-power output difficulty is larger;(2) the high power gain difficulty under the conditions of ultra broadband is larger;(3) tradition under ultra broadband
The chip area of method is larger.
Content of the invention
The technical problem to be solved is to provide a kind of matrix power amplifier based on transistor stack technology,
Low excellent with high-power output ability, high power gain, good input and output matching properties, the little and cost of chip area
Point.
The technical scheme that the present invention solves above-mentioned technical problem is as follows:A kind of Matrix Power based on transistor stack structure
Amplifier, including be sequentially connected input matching network, power distributing network, stacking matrix amplify network, power synthesis network
And output matching network, and amplify the first biasing circuit and the second biasing that network is symmetrically connected respectively with the stacking matrix
Circuit.
The invention has the beneficial effects as follows:Network is amplified using transistor stack matrix, the area of chip is saved, while real
Show good broadband power fan-out capability and power gain ability, it is to avoid the low breakdown voltage characteristic of integrated circuit technology,
Improve the Stability and dependability of circuit.
On the basis of technique scheme, the present invention can also do following improvement.
Further, the stacking matrix amplifies network includes at least parallel stacked structure of two-way, and the stacked structure is extremely
It is made up of according to the connected stacking of source drain two transistors less;
The grid of the transistor of the bottom per road stacked structure is each individually connected to institute after connecting two parallel resistances
State the grid bypass electric capacity of the first biasing circuit and the grid bypass electric capacity of second biasing circuit, the bottom transistor
Source ground, and the grid of the bottom transistor is connected to the input pair net by the power distributing network
Network;
It is inclined that the grid of the transistor of the remainder layer per road stacked structure is each individually connected to described first by resistance
The grid divider resistance of circuits and the grid divider resistance of the second biasing circuit, and the grid of the transistor of the remainder layer divides
Not Lian Jie two route grids compensation resistance be connected with grid compensating electric capacity be grounded constitute compensation circuit;
The drain electrode of the transistor of the superiors per road stacked structure is connected respectively to by the power synthesis network
The output matching network feeds inductance with the drain electrode of first biasing circuit and second biasing circuit.
It is to ensure that power amplifier obtains the power output of maximum, Ke Yi great using the beneficial effect of above-mentioned further scheme
The big area for saving chip.
Further, the compensation circuit per road stacked structure on adjacent gate node passes through gate isolation resistance string
Connect.
Using the beneficial effect of above-mentioned further scheme it is:Make matrix power amplifier stabilizing effect more preferable.
Further, the bias voltage of the transistor that the stacking matrix is stacked in amplifying per layer of network not decile, most bottom
The bias voltage of layer transistor is minimum, the bias voltage highest of the superiors' transistor, and the bias voltage of remaining transistor is between two
Between person.
Further, first biasing circuit and second biasing circuit are by grid bypass electric capacity, grid partial pressure electricity
Resistance, drain electrode feed inductance and drain electrode shunt capacitance are constituted.
Using the beneficial effect of above-mentioned further scheme it is:For realize the power amplifier grid and drain electrode feed and
The bypass functionality of spurious signal.
Further, the stacking matrix amplifies network includes the parallel stacked structure in four tunnels, and the stacked structure is by three
Transistor is connected to stack according to source drain and constitutes.
Further, low pressure bias supply is connected respectively to the grid of first biasing circuit and second biasing circuit
In shunt capacitance;HVB high voltage bias power supply is connected respectively to the drain electrode feed of first biasing circuit and second biasing circuit
On inductance and drain electrode shunt capacitance.
Further, the input matching network by capacitance, matching capacitance and mates inductance with output matching network
Constitute.
Using the beneficial effect of above-mentioned further scheme it is:For realizing the input impedance of the matrix power amplifier
Mate and every straight function and output impedance coupling and every straight function.
Further, the power distributing network is constituted by six sections of microstrip line constructions with power synthesis network.
Using the beneficial effect of above-mentioned further scheme it is:For realizing the distribution function of input signal respectively with output letter
Number complex functionality.
Further, it is active amplification network that the stacking matrix amplifies network, the input matching network, power distributing network
Network, power synthesis network and output matching network are passive network.
Description of the drawings
Fig. 1 is matrix power amplifier theory diagram of the present invention;
Fig. 2 is matrix power amplifier circuit diagram of the present invention.
Specific embodiment
The principle of the present invention and feature are described below in conjunction with accompanying drawing, example is served only for explaining the present invention, and
Non- for limiting the scope of the present invention.
As shown in Figure 1 and Figure 2, a kind of matrix power amplifier based on transistor stack structure that the present invention is provided, is one
The ultra-wide band radio-frequency power amplifier for amplifying network structure using transistor stack matrix is planted, is set using integrated circuit technology
Meter, amplifies network, power synthesis network and defeated including the input matching network that is sequentially connected, power distributing network, stacking matrix
Go out matching network, and amplify, with stacking matrix, the first biasing circuit and the second biasing circuit that network is symmetrically connected respectively, its
In, it is active amplification network that stacking matrix amplifies network, input matching network, power distributing network, power synthesis network, output
Matching network, the first biasing circuit and the second biasing circuit are passive network.
Wherein, stacking matrix amplifies network includes at least parallel stacked structure of two-way, and stacked structure is at least by two crystalline substances
Body pipe is connected to stack according to source drain and constitutes;The grid of the transistor per the bottom of road stacked structure connects two parallel resistances
The grid bypass electric capacity of first biasing circuit and the grid bypass electric capacity of second biasing circuit are each individually connected to afterwards, and the bottom is brilliant
The source ground of body pipe, and the grid of bottom transistor is connected to input matching network by power distributing network;
The first biasing circuit is each individually connected to by resistance per the grid of the transistor of the remainder layer of road stacked structure
The grid divider resistance of grid divider resistance and the second biasing circuit, and the grid of the transistor of remainder layer connects two routes respectively
Grid compensation resistance is connected the compensation circuit of ground connection composition with grid compensating electric capacity, and compensation circuit passes through gate isolation resistance string
Connect;
The drain electrode of the transistor per the superiors of road stacked structure is connected respectively to described by the power synthesis network
Output matching network feeds inductance with the drain electrode of first biasing circuit and second biasing circuit.
Input matching network by capacitance, matching capacitance and mates inductance composition with output matching network, for reality
The input impedance of the existing matrix power amplifier is mated with output impedance and every straight function.
Power distributing network is constituted by six sections of microstrip line constructions with power synthesis network, for realizing input signal respectively
Distribution function and complex functionality with output signal.
First biasing circuit and the second biasing circuit are by grid bypass electric capacity, three grid divider resistances, drain electrode feeds
Inductance and drain electrode shunt capacitance are constituted, for realizing the bypass work(of the power amplifier grid and drain electrode feed and spurious signal
Energy.
Low pressure bias supply is connected respectively on the grid bypass electric capacity of the first biasing circuit and the second biasing circuit;High
Pressure bias supply is connected respectively to drain electrode feed inductance and the drain electrode bypass electricity of the first biasing circuit and second biasing circuit
Rong Shang, stacks the bias voltage of the transistor stacked during matrix amplifies per layer of network not decile, most goes up the inclined of bottom transistor
Put that voltage is minimum, the bias voltage highest of upper strata transistor is most descended, the bias voltage of remaining transistor falls between.
For ensureing that power amplifier obtains the power output of maximum, the bigger voltage output amplitude of oscillation is needed, so the matrix
Power amplifier core amplifies network for stacking matrix, by the way of 4 tunnels of 3 transistor stack are amplified parallel, forms 3 × 4
Transistor stack matrix amplify network, DC feedback is carried out by multilevel resistance partial pressure type structure.With dividing using transformer
Cloth ultra broadband power amplifier structure is compared, and 3 × 4 transistor stack matrix amplifies the area that network can greatly save chip.
Wherein, amplify in network in stacking matrix, the method for solving of its key circuit parameters is as follows:
(1) grid compensating electric capacity C of stacked structure9~C16=Cgg:
(2) grid compensating electric capacity C of stacked structure17~C24=Cggg:
In above-mentioned formula, ZoptFor transistor optimum load true impedance, unit is Ω;CgsFor transistor gate-source capacitance,
CgdIt is Miller capacitance for transistor gate-drain parasitic capacitances, unit is pF;gmFor transistor transconductance, unit is mS.
(3) the grid compensation resistance R of stacked structure13、R14、R16、R17、R19、R20、R22、R23Value is 3~5 Ω;
(4) the grid compensation resistance R of stacked structure28、R29、R31、R32、R34、R35、R37、R38Value is 5~10 Ω;
The gate isolation resistance R of the parallel structure for amplifying in (5) 4 tunnels15、R18、R21、R30、R33、R36Value is 50~100 Ω;
Based on above-mentioned formula, and pass through structure adjusting transistor M1~M12Size, biasing and feedback resistance R1~
R42Resistance value size, compensation and matching capacitance C1~C24Size, biasing and coupling inductance L1~L4Size, power combing
With distribution network TL1~TL12Size, the whole amplifier circuit of the present invention can be made to realize input in ultra broadband and export
Good impedance matching, high power gain, good power gain flatness, and whole power amplifier area very little, low cost.
The course of work of the present invention is:Radio-frequency input signals enters circuit by input IN, by input every straight coupling
Electric capacity C1, enter matching capacitance C2With coupling inductance L1The input matching network of the L minor matters of composition, subsequently into microstrip line TL1~
TL6The power distributing network of composition, subsequently into the bottom transistor M of 3 parallel transistor stack power amplifiers of 4 tunnels1~
M4Grid, then from M1~M4Drain electrode parallel output, then and be advanced into the second level transistor of 3 transistor stack amplifiers
M5~M8Source electrode, then from M5~M8Drain electrode parallel output, then and be advanced into 3 transistor stack amplifiers the third level brilliant
Body pipe M9~M12Source electrode, then from M9~M12Drain electrode parallel output, enter microstrip line TL7~TL12The power combing of composition
Network, subsequently into coupling inductance L2With matching capacitance C3The output matching network of the L minor matters of composition, enters output every straight coupling
Electric capacity C4, output end is reached finally by output end OUT, complete power amplification.
In the whole matrix power amplifier circuit based on transistor stack technology, the size of transistor and other direct currents
Feed resistance, the size of compensating electric capacity are to consider after the indices such as gain, bandwidth and the power output of whole circuit certainly
Fixed, by layout design and the rational deployment in later stage, required indices can be better achieved, realize in ultra broadband
Under the conditions of high-power output ability, high power gain, good input and output matching properties, the little and low cost of chip area.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and
Within principle, any modification, equivalent substitution and improvement that is made etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of matrix power amplifier based on transistor stack structure, it is characterised in that including the input being sequentially connected
Distribution network, power distributing network, stacking matrix amplify network, power synthesis network and output matching network, and respectively with institute
State stacking matrix and amplify network symmetrically the first biasing circuit of connection and the second biasing circuit.
2. the matrix power amplifier based on transistor stack structure according to claim 1, it is characterised in that the heap
Folded matrix amplifies network includes at least parallel stacked structure of two-way, and the stacked structure is at least by two transistors according to source electrode
Drain electrode is connected to stack and constitutes;
The grid of the transistor of the bottom per road stacked structure is each individually connected to described the after connecting two parallel resistances
The grid bypass electric capacity of one biasing circuit and the grid bypass electric capacity of second biasing circuit, the source of the bottom transistor
Pole is grounded, and the grid of the bottom transistor is connected to the input matching network by the power distributing network;
The grid of the transistor of the remainder layer per road stacked structure is each individually connected to first biased electrical by resistance
The grid divider resistance on road and the grid divider resistance of the second biasing circuit, and the grid of the transistor of the remainder layer connects respectively
Connect the compensation circuit that two route grids compensation resistance is connected ground connection composition with grid compensating electric capacity;
The drain electrode of the transistor of the superiors per road stacked structure is connected respectively to described by the power synthesis network
Output matching network feeds inductance with the drain electrode of first biasing circuit and second biasing circuit.
3. the matrix power amplifier based on transistor stack structure according to claim 2, it is characterised in that described per
Compensation circuit of the road stacked structure on adjacent gate node is concatenated by gate isolation resistance.
4. the matrix power amplifier based on transistor stack structure according to claim 2, it is characterised in that the heap
The bias voltage of the transistor that folded matrix is stacked in amplifying per layer of network not decile, the bias voltage of bottom transistor is most
Low, the bias voltage highest of the superiors' transistor, the bias voltage of remaining transistor fall between.
5. the matrix power amplifier based on transistor stack structure according to claim 2, it is characterised in that described
One biasing circuit and second biasing circuit are by grid bypass electric capacity, grid divider resistance, drain electrode feed inductance and drain electrode
Shunt capacitance is constituted.
6. the matrix power amplifier based on transistor stack structure according to claim 2, it is characterised in that the heap
Folded matrix amplifies network includes the parallel stacked structure in four tunnels, and the stacked structure is connected according to source drain by three transistors
Stacking is constituted.
7. the matrix power amplifier based on transistor stack structure according to claim 5, it is characterised in that low pressure is inclined
Put power supply to be connected respectively on the grid bypass electric capacity of first biasing circuit and second biasing circuit;HVB high voltage bias electricity
Source is connected respectively on the drain electrode feed inductance and drain electrode shunt capacitance of first biasing circuit and second biasing circuit.
8. the matrix power amplifier based on transistor stack structure according to claim 1, it is characterised in that described defeated
Enter matching network and by capacitance, matching capacitance and mate inductance composition with output matching network.
9. the matrix power amplifier based on transistor stack structure according to claim 1, it is characterised in that the work(
Rate distribution network is constituted by six sections of microstrip line constructions with power synthesis network.
10. the matrix power amplifier based on transistor stack structure according to any one of claim 1 to 9, its feature
It is, it is active amplification network that the stacking matrix amplifies network, and the input matching network, power distributing network, power are closed
Network and output matching network is become to be passive network.
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CN107743021A (en) * | 2017-10-10 | 2018-02-27 | 成都嘉纳海威科技有限责任公司 | A kind of strong anti-mismatch high efficiency power amplifier based on transistor stack technology |
CN107846196A (en) * | 2017-11-03 | 2018-03-27 | 成都嘉纳海威科技有限责任公司 | A kind of high-power high-efficiency power amplifier insensitive to source and load impedance |
CN107994875A (en) * | 2017-12-11 | 2018-05-04 | 成都嘉纳海威科技有限责任公司 | Ultra wide band based on compound reactance LC filter networks stacks power amplifier |
CN108599730A (en) * | 2018-06-15 | 2018-09-28 | 成都嘉纳海威科技有限责任公司 | A kind of high efficiency F classes stacking power amplifier based on compact resonator |
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