CN103746665B - Drive power amplifier with adjustable gain of 0.1-3GHz CMOS - Google Patents
Drive power amplifier with adjustable gain of 0.1-3GHz CMOS Download PDFInfo
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- CN103746665B CN103746665B CN201310488079.2A CN201310488079A CN103746665B CN 103746665 B CN103746665 B CN 103746665B CN 201310488079 A CN201310488079 A CN 201310488079A CN 103746665 B CN103746665 B CN 103746665B
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Abstract
The invention discloses a drive power amplifier with the adjustable gain of a 0.1-3GHz CMOS. The drive power amplifier comprises an input match circuit, an ultra-wideband drive stage amplifying circuit, a gain-adjustable amplifying circuit, an ultra-wideband power amplifying circuit and an output blocking circuit. A first ultra-wideband drive stage is used for achieving preceding-stage gain and ensuring ultra-wideband input match of the whole circuit. A gain control circuit is used for controlling power gain of wideband radio frequency signals and the good inter-ultra-wideband matching property. A third ultra-wideband drive power stage is used for ensuring large power output of the whole circuit and the good wideband output matching property. A three-stage stacking structure is combined with a compensation capacitance circuit, and the area of a chip is small. In the whole circuit, parameters of an adopted component can be determined according to indexes of items such as the whole circuit gain, the wideband and the output power, and therefore the adjustable gain, the high-linearity and the high drive power within the 0.1-3GHz can be achieved.
Description
Technical field
The present invention relates to CMOS complementary metal-oxide-semiconductor (cmos) radio-frequency power amplifier and integrated electrical domain, especially
It is a kind of ultra broadband cmos adjustable gain driving power amplifier covering towards the application of trade Special Network frequency range.
Background technology
The quick of the wireless communications market such as mobile phone, wireless phone, radio-frequency (RF) tag (rfid), WLAN (wlan) sends out
Exhibition, constantly promotes radio frequency front-end transceiver to develop to highly integrated, low-power consumption, compact conformation, cheap direction.More and more
Monolithic radio frequency transmitting-receiving communication system adopt cheap and relative maturity reliable cmos technological design to realize, this requires to get over
Come more communication system submodules ensure high performance must be designed using cmos technique simultaneously, thus realizing highly
Integrated, with low cost, dependable performance monolithic radio frequency communication system.
Power amplifier (abbreviation power amplifier, english abbreviation pa) is requisite submodule in wireless transmitter, is also whole
Consume energy in individual transmitter most parts, and output is typically than larger.Driving power amplifier is then final power amplifier
The important module of front end, when last stage of transmitter mixer output signal power is less, final power amplifier needs to drive simultaneously
When power signal is again larger, driving power amplifier played an important role.Meanwhile, for prevent drive power amplifier gain too high and
Make final power amplifier supersaturation, general driving power amplifier has adjustable gain function.
In order to improve the availability of frequency spectrum, the technology of commonly used amplitude modulation and phase modulation simultaneously is it is desirable to power amplifier has modern communication technology
The linearity well；The mobility of communication requires the power efficiency of power amplifier high as much as possible.Due to spread spectrum and communication system
The needs of system high speed transmitting-receiving speed, ultra-wide band radio-frequency power amplifier and ultra broadband adjustable gain radio-frequency driven power amplifier
Demand more and more higher.
The design difficulty of cmos adjustable gain radio-frequency driven power amplifier realizes high increasing under the conditions of being ultra broadband at present
Beneficial dynamic range, good flatness, less chip area and lower cost.The transistor longitudinal arrangement of stacked structures
(series configuration), in order to improve output voltage swing, optimal output load impedance is also improved, and makes defeated
Go out circuit impedance coupling to be more prone to realize, meanwhile, input circuit impedance remains constant, thus avoiding input, output matching
The power attenuation that network brings, improves the efficiency of circuit.But, traditional single-stage stacked structure based on cmos technique exists
Following problem: 1) the high-frequency gain decline of power gain relatively low 2) ultra broadband input difficulty of matching larger 3) is serious.Meanwhile, stack
The power amplifier of formula structure cannot realize gain control function.
At present, broadband wireless access equipment in the range of 0.1～1.2ghz for the frequency is mainly used in trade Special Network, but row
The frequency of industry private network and bandwidth species are various, standard disunity.Cover 1.2ghz～5ghz simultaneously and be used for commercial and civil area
Communication system species more.In order to reduce design cost, improve circuit versatility, the demand of distributed power amplifier is more next
More urgent, thus the demand for ultra broadband adjustable gain driving power amplifier also heats up therewith.However, covering industry at present
Radio frequency front end chip majority used by private network frequency range is monopolized by offshore company, and distributed power amplifier circuit (includes gain
Adjustable driving power amplifier) also also such.Also there are problems in trade Special Network core devices application foreign chip.
With respect to other wireless transceiving component, high-power, High Linear, high efficiency are that the Basic Design of power amplifier will
Ask.Much commercial power amplifier uses gaas device at present, but, gaas device is higher than cmos si device cost, and hybrid technique does
The system bulk ratio becoming is larger, and popular SOC(system on a chip) requires power amplifier energy and other radio-frequency front-end assemblies, baseband circuit, dsp
Circuit etc. uses the cmos technique of main flow integrated on the same chip, to reduce volume, reduce cost, increase system reliability.By
In it low cost, small area, high integration and the advantages of low-power consumption, cmos technology is got in distributed power amplifier field
More paid close attention to by people.In cmos radio-frequency front-end, low-noise amplifier, frequency mixer, wave filter, the research of amplifier and
Design comparison is ripe, and broadband, high efficiency, the deep-submicron cmos radio-frequency power amplifier of High Linear remain and on cmos piece be
System is most difficult to one of assembly of realization.
The circuit basic structure of common adjustable gain driving power amplifier has a lot, and such as adjustable gain common source amplifies
Device etc., the requirement wanting simultaneously to meet parameters is very difficult.
The adjustable gain driving power Amplifier Design difficult point being currently based on cmos technique is as follows:
1. the chip area of the traditional method under ultra broadband is larger；
2. the input under ultra broadband, the difficult point of output matching circuit increase；
3. the adjustable gain flatness difficulty under the conditions of ultra broadband is larger.
Content of the invention
For above-mentioned prior art, the present invention provides a kind of 0.1～3ghz cmos adjustable gain driving power amplifier,
It is a kind of ultra broadband adjustable gain driving power amplifier circuit knot covering towards trade Special Network application band 0.1～1.2ghz
Structure, its design frequency range is up to 0.1～3ghz so as to have adjustable gain function, good input and output matching properties, chip face
Amass little and low cost.
In order to solve above-mentioned technical problem, one kind of the present invention 0.1～3ghz cmos adjustable gain driving power amplifier,
It is achieved using three-level stacked structure and capacitor compensating circuit, its technical scheme is: include input matching circuit, ultra broadband drives
Dynamic level amplifying circuit, gain adjustable amplifying circuit, ultra broadband power amplification circuit and output block isolating circuit, described ultra broadband drives
Level amplifying circuit, gain adjustable amplifying circuit and ultra broadband power amplification circuit are active Two-port netwerk and amplify network；Described defeated
Enter match circuit by inputting the outer capacitance of dististyle, build-out resistor, feedback resistance and constitute every straight coupled capacitor；Described output every
Straight circuit is constituted by every straight coupled capacitor；Described ultra broadband driving stage amplifying circuit includes four nmos pipes, a current offset
Circuit and the outer capacitance of input chip；Four nmos transistors sequentially concatenate according to the mode that source electrode connects drain electrode, four nmos
The gate bias of transistor adopts the multilevel resistance partial pressure type structure that five resistance are constituted, and the grid of each nmos transistor connects
To on corresponding electric resistance partial pressure node, the grid of the nmos transistor of bottom inputs as AC signal, the nmos of the top
The drain electrode of transistor exports as AC signal；The input circuit of input nmos transistor takes series matching resistor and electric capacity
Mode is mated, and adopts a feedback resistance will input the node between the series matching resistor of nmos transistor and electric capacity simultaneously
It is connected with the drain electrode of output transistor；Big inductance, inductance another termination power vdd outside the drain electrode contact pin of output transistor；Should
In ultra broadband driving stage amplifying circuit, in addition to the input nmos transistor of bottom, the grid of its excess-three nmos transistor is inclined
Put node and respectively connect a grid compensating electric capacity, the compensating electric capacity other end is grounded, totally three；Except the input nmos of bottom is brilliant
Outside body pipe, between its excess-three nmos transistor drain and source electrode, respectively connect a drain-source compensating electric capacity, totally three；Described gain
Adjustable amplifying circuit, using two noms transistors, according to common source, grid mode carries out power amplification altogether, and common gate amplifies simultaneously
Device gate bias voltage is gain control signal, the change of gain-controlled voltage size, controls whole three-level to drive the increasing of power amplifier
Benefit；Described ultra broadband power amplification circuit, using essentially identical with ultra broadband drive amplification circuit, is managed including four nmos, one
Current biasing circuit and the outer capacitance of input chip；Four nmos transistors sequentially concatenate according to the mode that source electrode connects drain electrode,
The gate bias of four nmos transistors adopts the multilevel resistance partial pressure type structure that five resistance are constituted, each nmos transistor
Grid is connected on corresponding electric resistance partial pressure node, and the grid of the nmos transistor of bottom inputs as AC signal, goes up most
The drain electrode of the nmos transistor of side exports as AC signal；Series matching resistor taken by the input circuit of input nmos transistor
Mated with the mode of electric capacity, adopt a feedback resistance will input series matching resistor and the electric capacity of nmos transistor simultaneously
Between node be connected with the drain electrode of output transistor；Big inductance outside the drain electrode contact pin of output transistor, inductance another termination electricity
Source vdd；In this ultra broadband power amplification circuit, in addition to the input nmos transistor of bottom, its excess-three nmos transistor
Gate bias node respectively connects a grid compensating electric capacity, and the compensating electric capacity other end is grounded, totally three；Input except bottom
Outside nmos transistor, between its excess-three nmos transistor drain and source electrode, respectively connect a drain-source compensating electric capacity, totally three；Its
Difference is, the ultra broadband input circuit mating structure of the circuit of the third level first connects and is followed by build-out resistor every straight coupled capacitor；Institute
State ultra broadband driving stage amplifying circuit and the drain voltage of described ultra broadband power amplification circuit passes through two piece external inductances respectively
Connect Dc bias vdd.
Compared with prior art, the invention has the beneficial effects as follows: using electric resistance partial pressure type stacked structure and capacitance compensation electricity
Road, can greatly save the area of chip, realize good broadband character and gain flatness simultaneously, it is to avoid cmos technique
Low breakdown voltage characteristic, improve circuit Stability and dependability.
One kind of the present invention 0.1～3ghz cmos adjustable gain driving power amplifier adopts twin-stage ultra broadband cmos radio frequency
Power amplifier structure different from the structure of the conventional adjustable gain radio-frequency driven power amplifier based on cmos technique it
Place is:
(1) in overall architecture, the first order and the 3rd pole adopt stacked structure, improve power gain, and the second level is gain
Control circuit, improves dynamic gain control scope；
(2) first order and third level input circuit, all using resistive degeneration structure, improve the input of first order power amplifier
Circuit Matching and the interstage circuit ultra broadband matching properties of the 3rd pole and the second level；
(3) first, third level stacked structure carries out high-frequency gain using universal high voltage fet form
Compensate, improve high frequency power gain, and then expand the bandwidth of operation of distributed power amplifier.
Brief description
Fig. 1 is one kind of the present invention 0.1～3ghz cmos adjustable gain driving power amplifier principle block diagram；
Fig. 2 is the circuit theory diagrams that a kind of present invention 0.1～3ghz cmos adjustable gain driving power amplifier is implemented.
Specific embodiment
A kind of present invention 0.1～3ghz cmos adjustable gain driving power amplifier is a kind of adjustable gain four of three-level
Rank stacked structure capacitance compensation type amplifier, is designed using cmos technique.
Including input matching circuit, ultra broadband driving stage amplifying circuit, gain adjustable amplifying circuit, ultra broadband power amplification
Circuit and output block isolating circuit, described ultra broadband driving stage amplifying circuit, gain adjustable amplifying circuit and ultra broadband power amplification
Circuit is active Two-port netwerk and amplifies network；Described input matching circuit is by inputting dististyle outer capacitance, build-out resistor, feedback
Resistance and every straight coupled capacitor constitute；Described output block isolating circuit is constituted by every straight coupled capacitor.
Wherein, the first order of circuit is ultra broadband driving stage, for realizing the ultra broadband driving power gain of its amplifier,
And ensure the ultra broadband s11 parameter coupling of whole circuit；The second level is adjustable gain amplifier stage, is used for realizing high-gain transferring
State scope；The third level is ultra broadband driving stage, for ensureing the ultra broadband power output of whole circuit and good ultra broadband s22
Parameter is mated.And, three-level is active Two-port netwerk and amplifies network.
As the ultra broadband driving stage amplifying circuit of the first order, manage including four nmos, a current biasing circuit and defeated
Enter the outer capacitance of piece；Four nmos transistors sequentially concatenate according to the mode that source electrode connects drain electrode, four nmos transistors
Gate bias adopts the multilevel resistance partial pressure type structure that five resistance are constituted, and the grid of each nmos transistor is connected to accordingly
On electric resistance partial pressure node, the grid of the nmos transistor of bottom inputs as AC signal, the nmos transistor of the top
Drain electrode is as AC signal output；The input circuit of input nmos transistor takes series matching resistor and the mode of electric capacity to carry out
Coupling, adopts a feedback resistance by the node inputting between the series matching resistor of nmos transistor and electric capacity and to export brilliant simultaneously
The drain electrode of body pipe is connected；Big inductance, inductance another termination power vdd outside the drain electrode contact pin of output transistor；This ultra broadband drives
In dynamic level amplifying circuit, in addition to the input nmos transistor of bottom, the gate bias node of its excess-three nmos transistor is equal
Connect a grid compensating electric capacity respectively, the compensating electric capacity other end is grounded, totally three；In addition to the input nmos transistor of bottom,
A drain-source compensating electric capacity is respectively connected between its excess-three nmos transistor drain and source electrode, totally three.
As the gain adjustable amplifying circuit of the second level, using two noms transistors, according to common source, grid mode is carried out altogether
Power amplification, common grid amplifier gate bias voltage is gain control signal simultaneously, the change of gain-controlled voltage size, control
Make the gain that whole three-level drives power amplifier.
Described ultra broadband power amplification circuit as the third level adopts the ultra broadband drive amplification circuit phase with the first pole
Same bias structure and basic structure for amplifying, described ultra broadband power amplification circuit includes four nmos pipes, a current offset
Circuit and the outer capacitance of input chip；Four nmos transistors sequentially concatenate according to the mode that source electrode connects drain electrode, four nmos
The gate bias of transistor adopts the multilevel resistance partial pressure type structure that five resistance are constituted, and the grid of each nmos transistor connects
To on corresponding electric resistance partial pressure node, the grid of the nmos transistor of bottom inputs as AC signal, the nmos of the top
The drain electrode of transistor exports as AC signal；The input circuit of input nmos transistor takes series matching resistor and electric capacity
Mode is mated, and adopts a feedback resistance will input the node between the series matching resistor of nmos transistor and electric capacity simultaneously
It is connected with the drain electrode of output transistor；Big inductance, inductance another termination power vdd outside the drain electrode contact pin of output transistor；Should
In ultra broadband power amplification circuit, in addition to the input nmos transistor of bottom, the gate bias of its excess-three nmos transistor
Node respectively connects a grid compensating electric capacity, and the compensating electric capacity other end is grounded, totally three；Input nmos crystal except bottom
Pipe is outer, respectively connects a drain-source compensating electric capacity between its excess-three nmos transistor drain and source electrode, totally three；The institute of the third level
State ultra broadband power amplification circuit from unlike the ultra broadband drive amplification circuit of the first pole, the described ultra broadband work(of the third level
The ultra broadband input circuit mating structure of rate amplifying circuit first connects and is followed by build-out resistor every straight coupled capacitor.
The drain voltage of described ultra broadband driving stage amplifying circuit and described ultra broadband power amplification circuit passes through two respectively
Individual piece external inductance connects Dc bias vdd, and inductance is at least 100nh.
The gain of the whole three-level in a kind of present invention 0.1～3ghz cmos adjustable gain driving power amplifier can
Adjust in quadravalence stacked structure capacitance compensation type amplifier, the size of nmos pipe and other DC feedback resistance, compensating electric capacity, feedbacks
The size of resistance is decision after the indices such as adjustable gain scope, bandwidth and the output of the whole circuit considering
's.By layout design and the rational deployment in later stage, required indices can be better achieved, realize 0.1～
Adjustable gain power amplification under the broadband condition of 3ghz, good input and output matching properties, chip area be little and low cost.
Compared with the distributed ultra wide-band power amplifier structure using transformator, multilevel resistance partial pressure type structure can greatly save the face of chip
Long-pending.
Below in conjunction with the accompanying drawings circuit of the present invention is described in further detail.
As shown in figure 1, the ultra broadband cmos adjustable gain of the present invention drives radio-frequency power amplifier to use three-level
Structure for amplifying.The first order is ultra broadband driving stage, for realizing the ultra broadband gain of circuit；The second level is amplified for adjustable gain
Level, is used for realizing the adjustable dynamic range of high-gain；The third level is ultra broadband power output stage it is ensured that whole circuit is larger
Ultra broadband power output, realizes the final amplification of radiofrequency signal.Whole circuit vdd can be used uniformly across the DC source of 3.3v or 5v
Power supply, vcc control voltage scope -3.3～3.3v.
Fig. 2 is based on being embodied as circuit diagram under the cmos technique shown in Fig. 1.
Radio-frequency input signals enters circuit by input vin, by build-out resistor r1, every straight coupled capacitor cm1, from crystalline substance
Body pipe m4 grid enters first order driving power level, after power amplification, from the drain electrode output of transistor m1, through every straight coupling
Close electric capacity cm2 and series matching resistor r14, enter second level power-amplifier stage from the grid of transistor m8, through power amplification
Export from the drain electrode of transistor m5 afterwards, by reaching outfan every straight coupled capacitor cout, complete power amplification.
The specific embodiment of the first order amplifier architecture of three-level adjustable gain power amplifier is:
(1) it is connected in series by tetra- transistors of m1, m2, m3, m4, that is, the source electrode of transistor m1 connects the drain electrode of m2, m2's
Source electrode connects the drain electrode of m3, and the source electrode of m3 connects the drain electrode of m4, the source ground of m4, the exchange input letter of this structure that is connected in series
Number flow into from the grid of m4, the drain electrode to m1 is flowed out.
(2) r3, r4, r5, r6, r7 series connection partial-pressure structure provides electric resistance partial pressure type bias for the grid of each transistor, with
When, r3 is resistance-type negative feedback, forms feedback network, thus improving the indexs such as the bandwidth of circuit between the drain and gate being m1.
(3) by grid capacitance cgs and extra grid compensating electric capacity c1, c2, the c3 of m1, m2, m3, m4 transistor, carry out
Capacitive voltage distributes.The value of c1, c2, c3 is through accurate analytical calculation, so that each transistor of m1, m2, m3, m4
Drain-source voltage vds, gate source voltage vgs, drain-gate voltage vdg realize Phase synchronization, it is achieved thereby that m1, m2, m3, m4 transistor
The synchronization superposition of AC signal, therefore, the ac small signal of each m1, m2, m3, m4 transistor is superposed to m1 to m4 cascaded structure
The overall big signal of exchange.In short, the ac small signal of each transistor of m1, m2, m3, m4 is connected in series together, due to phase place
Synchronous, small-signal is superposed to big signal.Because the cascaded structure voltage swing of m1 to m4 increases (4 times of single transistor), string
Connection electric current constant (m1 to m4 cascaded structure it is assumed that when the electric current that flows through is constant), so this structure may operate in big voltage swing
Under width and high-power signal (4 times of single transistor).Because this structure may operate in big voltage swing characteristic, therefore may be used
To break through the restriction of the breakdown voltage of conventional cmos technique.
(4) c4, c5, c6 constitute drain-source compensating electric capacity, and c4 is connected to the drain-source two ends of m1, and c5 is connected to the drain-source two of m2
End, c6 is connected to the drain-source two ends of m3, in order to balance the high frequency gate leakage (gate leakage) of m1 to m4 cascaded structure, from
And (< 6ghz) can also normal work in high frequency to ensure this circuit structure.Because, when frequency is relatively low (< 3ghz), m1, m2,
The phase equalization of m3, m4 transistor is preferable；(> 3ghz during high frequency), the phase equalization between m1, m2, m3, m4 transistor is sensitive
Degree uprises, grid compensating electric capacity c1, and c2, c3 just produce slight gate leakage so that the phase of m1, m2, m3, m4 transistor
Bit integrity is destroyed, and during ac small signal superposition, power attenuation increases, and reduces power gain.By drain-source compensating electric capacity
C4, c5, c6 produce drain-source AC regeneration, can balance gate leakage, and specially c4 balances the high frequency gate leakage that c1 causes, c5
The high frequency gate leakage that balance c2 causes, c6 balances the high frequency gate leakage that c3 causes, it is achieved thereby that the phase place of transistor is put down
Weighing apparatus is it is ensured that the high-frequency gain of m1 to m4 cascaded structure.
(5) because the watt level of m1 to m4 cascaded structure is constant, voltage bias are 4 times of single transistor, and electric current is not
Become, therefore, the output optimum load impedance of this cascaded structure exports 4 times of optimum load impedance for single transistor.Typically come
Say, the output optimum load impedance of single tube power amplifier is Low ESR (such as 12 ohm), need extra impedance matching knot
Structure enters 50 ohm of matched design of line output circuit.Optimal output loading resistance using the power amplifier of m1 to m4 cascaded structure
Resist 4 times (12 ohm * 4 ≈ 50 ohm) for single tube, be closer to 50 ohm, therefore do not need extra match circuit, just
The output circuit impedance coupling of preferable ultra broadband can be realized.
(6) input circuit part adopts feedback resistance r2, build-out resistor r1 and every straight coupled capacitor cm1, realizes input electricity
The Broadband Matching of line structure.Need to adopt inductance in conventional rlc coupling, but on-chip inductor area is larger, in order to realize face
Long-pending miniaturization, it is to avoid matched design is carried out using inductance.
Three-level adjustable gain power amplifier second level amplifier, is gain adjustable amplifier, specific embodiment is:
It is connected in series using common source, cathode-input amplifier form by two transistors of m9, m10, that is, the source electrode of transistor m10 connects
Connect the drain electrode of m9, the source ground of m9, first order output signal after the grid of m9, in the amplification of common source, cathode-input amplifier
Under effect, enter into m10 drain electrode, as the output of second level gain adjustable amplifier.A DC feedback is passed through in the drain electrode of m10
Resistance r15 is connected with the DC feedback network of the first order, provides drain electrode feed for the whole second level.The grid of m10 connects outside
Gain control signal vcc, of different sizes by vcc voltage, control m10 cathode-input amplifier power gain, and then realize
The whole adjustable gain function of driving power amplifier module.
Three-level adjustable gain power amplifier third level amplifier, using the structure similar with the first order, specific embodiment party
Formula is:
(1) it is connected in series by tetra- transistors of m5, m6, m7, m8, that is, the source electrode of transistor m5 connects the drain electrode of m6, m6's
Source electrode connects the drain electrode of m7, and the source electrode of m7 connects the drain electrode of m8, the source ground of m8, the exchange input letter of this structure that is connected in series
Number flow into from the grid of m8, the drain electrode to m5 is flowed out.
(2) r8, r9, r10, r11, r12 series connection partial-pressure structure provides electric resistance partial pressure type bias for the grid of each transistor,
Meanwhile, r8 is resistance-type negative feedback, forms feedback network between the drain and gate being m5.
(3) by grid capacitance cgs and extra grid compensating electric capacity c7, c8, the c9 of m5, m6, m7, m8 transistor, carry out
Capacitive voltage distributes.
(4) c10, c11, c12 constitute drain-source compensating electric capacity, and c10 is connected to the drain-source two ends of m5, and c11 is connected to the leakage of m6
Source two ends, c12 is connected to the drain-source two ends of m7, in order to balance the high frequency gate leakage of m5 to m8 cascaded structure.
(5) it is similar to prime, rear class output circuit does not need extra match circuit it is possible to realize preferable ultra broadband
Output circuit impedance coupling.The input circuit part of rear class adopts feedback resistance r13, build-out resistor r14 and couples electricity every straight
Hold cm2, realize Broadband Matching between the level of rear class input circuit structure.
The drain voltage of dual-stage amplifier passes through big inductance l1 and l2 outside piece and connects Dc bias vdd, overall twin-stage power amplifier
Piece outside input every straight coupled capacitor be cin, export outside piece every straight coupled capacitor be cout.
By adjusting the size of m1 to m8 transistor, the resistance value size of biasing and feedback resistance r1 to r14, compensate
The size of electric capacity c1 to c12, and the size of the transistor of m9 and m10 of gain control circuit, DC feedback resistance r15's is big
Little.Whole circuit can be made to have adjustable gain function, good input and output matching in 0.1～3ghz ultra wideband frequency
Characteristic, chip area be little and low cost.
Although above in conjunction with figure, invention has been described, the invention is not limited in above-mentioned specific embodiment party
Formula, above-mentioned specific embodiment is only schematically, rather than restricted, and those of ordinary skill in the art is at this
Under bright enlightenment, without deviating from the spirit of the invention, many variations can also be made, these belong to the guarantor of the present invention
Within shield.
Claims (1)
1. one kind 0.1～3ghz cmos adjustable gain driving power amplifier is it is characterised in that including input matching circuit, surpassing
Broadband driving stage amplifying circuit, gain adjustable amplifying circuit, ultra broadband power amplification circuit and output block isolating circuit, described ultra-wide
Band driving stage amplifying circuit, gain adjustable amplifying circuit and ultra broadband power amplification circuit are active Two-port netwerk and amplify network；
Described input matching circuit is by inputting the outer capacitance of dististyle, build-out resistor, feedback resistance and constitute every straight coupled capacitor；
Described output block isolating circuit is constituted by every straight coupled capacitor；
Described ultra broadband driving stage amplifying circuit includes four nmos pipes, every directly electricity outside a current biasing circuit and input chip
Hold；Four nmos transistors sequentially concatenate according to the mode that source electrode connects drain electrode, and the gate bias of four nmos transistors adopts
The multilevel resistance partial pressure type structure that five resistance is constituted, the grid of each nmos transistor is connected to corresponding electric resistance partial pressure node
On, the grid of the nmos transistor of bottom inputs as AC signal, and the drain electrode of the nmos transistor of the top is as exchange
Signal output；The input circuit of input nmos transistor takes series matching resistor and the mode of electric capacity to be mated, and adopts simultaneously
The drain electrode of the node between the series matching resistor of nmos transistor and electric capacity and output transistor will be inputted with a feedback resistance
It is connected；Big inductance, inductance another termination power vdd outside the drain electrode contact pin of output transistor；This ultra broadband driving stage amplifies electricity
Lu Zhong, in addition to the input nmos transistor of bottom, the gate bias node of its excess-three nmos transistor respectively connects one
Grid compensating electric capacity, the compensating electric capacity other end is grounded；In addition to the input nmos transistor of bottom, its excess-three nmos transistor
Drain electrode and source electrode between respectively connect a drain-source compensating electric capacity；
Described gain adjustable amplifying circuit, using two noms transistors, according to common source, grid mode carries out power amplification altogether, with
When common grid amplifier gate bias voltage be gain control signal, the change of gain-controlled voltage size, control whole three-level
Drive the gain of power amplifier；
Described ultra broadband power amplification circuit includes four nmos pipes, a current biasing circuit and the outer capacitance of input chip；
Four nmos transistors sequentially concatenate according to the mode that source electrode connects drain electrode, and the gate bias of four nmos transistors adopts five
The multilevel resistance partial pressure type structure that resistance is constituted, the grid of each nmos transistor is connected on corresponding electric resistance partial pressure node,
The grid of the nmos transistor of bottom inputs as AC signal, and the drain electrode of the nmos transistor of the top is as AC signal
Output；The input circuit of input nmos transistor takes series matching resistor and the mode of electric capacity to be mated, and adopts one simultaneously
Individual feedback resistance is connected inputting the node between the series matching resistor of nmos transistor and electric capacity with the drain electrode of output transistor
Connect；Big inductance, inductance another termination power vdd outside the drain electrode contact pin of output transistor；In this ultra broadband power amplification circuit, remove
Outside the input nmos transistor of bottom, the gate bias node of its excess-three nmos transistor respectively connects a grid and compensates
Electric capacity, the compensating electric capacity other end is grounded；In addition to the input nmos transistor of bottom, the drain electrode of its excess-three nmos transistor and
A drain-source compensating electric capacity is respectively connected between source electrode；The ultra broadband input circuit mating structure of the circuit of the third level first connects every straight coupling
Close electric capacity and be followed by build-out resistor；
The drain voltage of described ultra broadband driving stage amplifying circuit and described ultra broadband power amplification circuit passes through two pieces respectively
External inductance connects Dc bias vdd, and inductance is at least 100nh.
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| CN201310488079.2A CN103746665B (en) | 2013-10-17 | 2013-10-17 | Drive power amplifier with adjustable gain of 0.1-3GHz CMOS |
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| CN201310488079.2A CN103746665B (en) | 2013-10-17 | 2013-10-17 | Drive power amplifier with adjustable gain of 0.1-3GHz CMOS |
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| CN107093988A (en) * | 2017-04-17 | 2017-08-25 | 武汉大学 | The controllable K-band power amplifier of a kind of 7 modal gain and power output |
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| CN113162564B (en) * | 2021-03-25 | 2023-05-26 | 成都知融科技有限公司 | CMOS power amplifier with temperature compensation function on chip |
| CN114244293A (en) * | 2022-01-11 | 2022-03-25 | 中国航天科工集团八五一一研究所 | Radio frequency stack power amplifier adopting parallel capacitors |
| CN114944819B (en) * | 2022-05-16 | 2023-02-10 | 广东工业大学 | Bias circuit for radio frequency power amplifier |
| CN114793094B (en) * | 2022-06-20 | 2022-10-25 | 华南理工大学 | Adjustable gain low noise amplifier and receiver |
| CN115347871B (en) * | 2022-10-17 | 2023-04-07 | 成都嘉纳海威科技有限责任公司 | Continuous gain adjustable millimeter wave broadband drive amplifier |
| CN116505896A (en) * | 2023-05-26 | 2023-07-28 | 西安博瑞集信电子科技有限公司 | Ultra-wideband power amplifier based on stacked structure |
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| US6636119B2 (en) * | 2000-12-21 | 2003-10-21 | Koninklijke Philips Electronics N.V. | Compact cascode radio frequency CMOS power amplifier |
| US7560994B1 (en) * | 2008-01-03 | 2009-07-14 | Samsung Electro-Mechanics Company | Systems and methods for cascode switching power amplifiers |
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