CN103746665A - Drive power amplifier with adjustable gain of 0.1-3GHz CMOS - Google Patents
Drive power amplifier with adjustable gain of 0.1-3GHz CMOS Download PDFInfo
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Abstract
The invention discloses a drive power amplifier with the adjustable gain of a 0.1-3GHz CMOS. The drive power amplifier comprises an input match circuit, an ultra-wideband drive stage amplifying circuit, a gain-adjustable amplifying circuit, an ultra-wideband power amplifying circuit and an output blocking circuit. A first ultra-wideband drive stage is used for achieving preceding-stage gain and ensuring ultra-wideband input match of the whole circuit. A gain control circuit is used for controlling power gain of wideband radio frequency signals and the good inter-ultra-wideband matching property. A third ultra-wideband drive power stage is used for ensuring large power output of the whole circuit and the good wideband output matching property. A three-stage stacking structure is combined with a compensation capacitance circuit, and the area of a chip is small. In the whole circuit, parameters of an adopted component can be determined according to indexes of items such as the whole circuit gain, the wideband and the output power, and therefore the adjustable gain, the high-linearity and the high drive power within the 0.1-3GHz can be achieved.
Description
Technical field
The present invention relates to CMOS (Complementary Metal Oxide Semiconductor) (CMOS) radio-frequency power amplifier and integrated electric field, particularly coverage rate to a kind of Ultrawideband CMOS of trade Special Network frequency range application adjustable Driver amplifier that gains.
Background technology
The fast development of the wireless communications market such as mobile phone, cordless telephone, radio-frequency (RF) tag (RFID), WLAN (wireless local area network) (WLAN), constantly promotes that radio-frequency front-end transceiver is integrated to height, low-power consumption, compact conformation, cheap future development.Increasing monolithic radio frequency transmitting-receiving communication system adopts the CMOS technological design of cheap and relative mature and reliable to realize, this just requires increasing communication system submodule guaranteeing that the high performance CMOS technique that simultaneously must adopt designs, thereby realizes monolithic radio frequency communication system highly integrated, with low cost, dependable performance.
Power amplifier (being called for short power amplifier, english abbreviation PA) is requisite submodule in wireless launcher, is also maximum parts that consume energy in whole transmitter, and power output is generally larger.Driver amplifier is the important module of final power amplifier front end, and when last stage of transmitter mixer output signal power is less, when simultaneously final power amplifier demand motive power signal is larger again, Driver amplifier has been brought into play important effect.Meanwhile, in order to prevent from driving, power amplifier gain is too high makes final power amplifier supersaturation, and general Driver amplifier has gain adjustable function.
Modern communication technology, in order to improve the availability of frequency spectrum, generally adopts the technology of amplitude modulation and phase modulation simultaneously, requires power amplifier to have the good linearity; The mobility of communication requires the power efficiency of power amplifier high as much as possible.Because spread spectrum and communication system are received and dispatched at a high speed the needs of speed, the demand of ultra-wide band radio-frequency power amplifier and ultra broadband gain tunable radio frequency Driver amplifier is more and more higher.
The design difficulty of the tunable radio frequency of CMOS gain at present Driver amplifier is to realize high-gain dynamic range under ultra broadband condition, good flatness, less chip area and lower cost.The transistor longitudinal arrangement of stacked structures (series configuration), in order to improve output voltage swing, best output load impedance is also improved, make output circuit impedance coupling be more prone to realize, simultaneously, input circuit impedance remains constant, thereby the power loss of having avoided input, output matching network to bring has improved the efficiency of circuit.But there is following problem in traditional single-stage stacked structure based on CMOS technique: 1) power gain is lower by 2) ultra broadband Input matching difficulty larger 3) high-frequency gain decline is seriously.Meanwhile, the power amplifier of stacked structures cannot be realized gain control function.
At present, the broadband wireless access equipment of frequency within the scope of 0.1～1.2GHz is mainly used in trade Special Network, but the frequency of trade Special Network and bandwidth are of a great variety, standard disunity.Cover 1.2GHz～5GHz more for the communication system kind of commercialization and civil area simultaneously.In order to reduce design cost, improve circuit versatility, the demand of distributed power amplifier is more and more urgent, thereby also heats up for the gain demand of adjustable Driver amplifier of ultra broadband thereupon.Yet, covering at present trade Special Network frequency range radio frequency front end chip majority used and monopolized by offshore company, distributed power amplifier circuit (comprising the adjustable Driver amplifier of gain) is also also like this.Trade Special Network core devices is applied external chip and is also had problems.
With respect to other wireless transceiving component, high-power, high linearity, high efficiency are the prime design requirements of power amplifier.At present a lot of commercial power amplifiers are used GaAs device, but, GaAs device is higher than CMOS Si device cost, and the system bulk that hybrid technique is made is larger, and the CMOS technique of the use main flows such as popular SOC (system on a chip) requirement power amplifier energy and other radio-frequency front-end assembly, baseband circuit, DSP circuit is integrated on same chip, to reduce volume, reduce cost, to increase system reliability.Due to its advantages such as low cost, small size, high integration and low-power consumption, CMOS technology more and more receives people's concern in distributed power amplifier field.In CMOS radio-frequency front-end, the research of low noise amplifier, frequency mixer, filter, amplifier and design comparison are ripe, and broadband, high efficiency, high linear deep-submicron CMOS radio-frequency power amplifier remain one of the assembly of difficult realization of CMOS SOC (system on a chip).
The circuit basic structure of the common adjustable Driver amplifier of gain has a lot, as the adjustable commonsource amplifier etc. that gains, and the requirement that wants simultaneously to meet parameters is very difficult.
The adjustable Driver amplifier design difficulty of gain based on CMOS technique is as follows at present:
1. the chip area of the conventional method under ultra broadband is larger;
2. the difficult point of the input under ultra broadband, output matching circuit strengthens;
3. the adjustable gain flatness difficulty under ultra broadband condition is larger.
Summary of the invention
For above-mentioned prior art, the invention provides a kind of 0.1～3GHz CMOS adjustable Driver amplifier that gains, a kind of coverage rate to the ultra broadband of the trade Special Network application band 0.1～1.2GHz adjustable Driver amplifier circuit structure that gains, its design frequency range can reach 0.1～3GHz, makes it have gain adjustable function, good input-output adapt ation characteristic, chip area is little and cost is low.
In order to solve the problems of the technologies described above, a kind of 0.1～3GHz CMOS of the present invention adjustable Driver amplifier that gains, adopt three grades of stacked structures and capacitor compensating circuit to be achieved, its technical scheme is: comprise input matching circuit, ultra broadband driving stage amplifying circuit, gain adjustable amplifying circuit, ultra broadband power amplification circuit and output block isolating circuit, described ultra broadband driving stage amplifying circuit, gain adjustable amplifying circuit and ultra broadband power amplification circuit are active two ports and amplify network; Described input matching circuit is by inputting dististyle outer capacitance, build-out resistor, feedback resistance and forming every straight coupling capacitance; Described output block isolating circuit is by forming every straight coupling capacitance; Described ultra broadband drive amplification circuit comprises four NMOS pipe, the outer capacitance of current biasing circuit and input chip; The mode that four NMOS transistors connects drain electrode according to source electrode is connected in series in turn, the multilevel resistance partial pressure type structure that the gate bias of four NMOS transistors adopts five resistance to form, the grid of each nmos pass transistor is connected on corresponding electric resistance partial pressure node, the grid of the nmos pass transistor of below is inputted as AC signal, and the drain electrode of the nmos pass transistor of the top is exported as AC signal; The input circuit of input NMOS transistor takes the mode of series matching resistor and electric capacity to mate, and adopts a feedback resistance that the series matching resistor of input NMOS transistor is connected with the drain electrode of output transistor with the node between electric capacity simultaneously; The outer large inductance of drain electrode contact pin of output transistor, another termination power vd of inductance D; Ultra broadband driving amplifier, except the input NMOS transistor of below, the gate bias node of its excess-three nmos pass transistor connects a grid building-out capacitor respectively, building-out capacitor other end ground connection, totally three; Except the input NMOS transistor of below, between its excess-three nmos transistor drain and source electrode, be connected respectively a drain-source building-out capacitor, totally three; Described gain adjustable amplifying circuit, adopt two NOMS transistors, according to common source, common grid mode, carry out power amplification, common grid amplifier gate bias voltage is gain control signal simultaneously, the variation of gain-controlled voltage size, controls whole three grades of gains that drive power amplifier; Described ultra broadband power amplification circuit adopts with ultra broadband drive amplification circuit basic identical, comprises four NMOS pipe, current biasing circuit and the outer capacitance of input chip; The mode that four NMOS transistors connects drain electrode according to source electrode is connected in series in turn, the multilevel resistance partial pressure type structure that the gate bias of four NMOS transistors adopts five resistance to form, the grid of each nmos pass transistor is connected on corresponding electric resistance partial pressure node, the grid of the nmos pass transistor of below is inputted as AC signal, and the drain electrode of the nmos pass transistor of the top is exported as AC signal; The input circuit of input NMOS transistor takes the mode of series matching resistor and electric capacity to mate, and adopts a feedback resistance that the series matching resistor of input NMOS transistor is connected with the drain electrode of output transistor with the node between electric capacity simultaneously; The outer large inductance of drain electrode contact pin of output transistor, another termination power vd of inductance D; Ultra broadband driving amplifier, except the input NMOS transistor of below, the gate bias node of its excess-three nmos pass transistor connects a grid building-out capacitor respectively, building-out capacitor other end ground connection, totally three; Except the input NMOS transistor of below, between its excess-three nmos transistor drain and source electrode, be connected respectively a drain-source building-out capacitor, totally three; Its difference is, the ultra broadband input circuit matching structure of the circuit of the third level first connects after straight coupling capacitance and connects build-out resistor; The drain voltage of described ultra broadband driving stage amplifying circuit and described ultra broadband power amplification circuit is connected direct current (DC) bias VDD by two sheet external inductances respectively.
Compared with prior art, the invention has the beneficial effects as follows: adopt electric resistance partial pressure type stacked structure and capacitor compensating circuit, can save greatly the area of chip, realize good broadband character and gain flatness simultaneously, avoid the low breakdown voltage characteristic of CMOS technique, improved the Stability and dependability of circuit.
Gain adjustable Driver amplifier of a kind of 0.1～3GHz CMOS of the present invention adopts twin-stage Ultrawideband CMOS radio-frequency power amplifier structure and the difference of the structure of the gain tunable radio frequency Driver amplifier based on CMOS technique to be in the past:
(1) in overall architecture, the first order and the 3rd utmost point adopt stacked structure, have improved power gain, and the second level is gain control circuit, has improved dynamic gain control scope;
(2) first order and third level input circuit all adopt resistive degeneration structure, have improved the input circuit coupling of first order power amplifier and the interstage circuit ultra broadband matching properties of the 3rd utmost point and the second level;
(3) first, third level stacked structure adopts Universal high voltage FET form to carry out high-frequency gain compensation, has improved high frequency power gain, and then has expanded the bandwidth of operation of distributed power amplifier.
Accompanying drawing explanation
Fig. 1 is a kind of 0.1～3GHz CMOS of the present invention adjustable Driver amplifier functional-block diagram that gains;
Fig. 2 is a kind of 0.1～3GHz CMOS of the present invention circuit theory diagrams that adjustable Driver amplifier implements that gain.
Embodiment
A kind of 0.1～3GHz CMOS of the present invention adjustable Driver amplifier that gains is the adjustable quadravalence stacked structure of the gain capacitance compensation type amplifier of a kind of three grades, adopts CMOS technique to design.
Comprise input matching circuit, ultra broadband driving stage amplifying circuit, gain adjustable amplifying circuit, ultra broadband power amplification circuit and output block isolating circuit, described ultra broadband driving stage amplifying circuit, gain adjustable amplifying circuit and ultra broadband power amplification circuit are active two ports and amplify network; Described input matching circuit is by inputting dististyle outer capacitance, build-out resistor, feedback resistance and forming every straight coupling capacitance; Described output block isolating circuit is by forming every straight coupling capacitance.
Wherein, the first order of circuit is ultra broadband driving stage, for realizing the ultra broadband driving power gain of its amplifier, and guarantees the ultra broadband S11 parameter matching of whole circuit; The second level is for the adjustable amplifying stage of gain, for realizing the adjustable dynamic range of high-gain; The third level is ultra broadband driving stage, for guaranteeing the ultra broadband power stage of whole circuit and good ultra broadband S22 parameter matching.And three grades are active two ports and amplify network.
Ultra broadband drive amplification circuit as the first order, comprises four NMOS pipe, the outer capacitance of current biasing circuit and input chip; The mode that four NMOS transistors connects drain electrode according to source electrode is connected in series in turn, the multilevel resistance partial pressure type structure that the gate bias of four NMOS transistors adopts five resistance to form, the grid of each nmos pass transistor is connected on corresponding electric resistance partial pressure node, the grid of the nmos pass transistor of below is inputted as AC signal, and the drain electrode of the nmos pass transistor of the top is exported as AC signal; The input circuit of input NMOS transistor takes the mode of series matching resistor and electric capacity to mate, and adopts a feedback resistance that the series matching resistor of input NMOS transistor is connected with the drain electrode of output transistor with the node between electric capacity simultaneously; The outer large inductance of drain electrode contact pin of output transistor, another termination power vd of inductance D; In this ultra broadband drive amplification circuit, except the input NMOS transistor of below, the gate bias node of its excess-three nmos pass transistor connects a grid building-out capacitor respectively, building-out capacitor other end ground connection, totally three; Except the input NMOS transistor of below, between its excess-three nmos transistor drain and source electrode, be connected respectively a drain-source building-out capacitor, totally three.
Gain adjustable amplifying circuit as the second level, adopt two NOMS transistors, according to common source, common grid mode, carry out power amplification, common grid amplifier gate bias voltage is gain control signal simultaneously, the variation of gain-controlled voltage size, controls whole three grades of gains that drive power amplifier.
Described ultra broadband power amplification circuit as the third level adopts the bias structure identical with the ultra broadband drive amplification circuit of first utmost point and basic structure for amplifying, described ultra broadband power amplification circuit comprises four NMOS pipe, the outer capacitance of current biasing circuit and input chip; The mode that four NMOS transistors connects drain electrode according to source electrode is connected in series in turn, the multilevel resistance partial pressure type structure that the gate bias of four NMOS transistors adopts five resistance to form, the grid of each nmos pass transistor is connected on corresponding electric resistance partial pressure node, the grid of the nmos pass transistor of below is inputted as AC signal, and the drain electrode of the nmos pass transistor of the top is exported as AC signal; The input circuit of input NMOS transistor takes the mode of series matching resistor and electric capacity to mate, and adopts a feedback resistance that the series matching resistor of input NMOS transistor is connected with the drain electrode of output transistor with the node between electric capacity simultaneously; The outer large inductance of drain electrode contact pin of output transistor, another termination power vd of inductance D; Ultra broadband driving amplifier, except the input NMOS transistor of below, the gate bias node of its excess-three nmos pass transistor connects a grid building-out capacitor respectively, building-out capacitor other end ground connection, totally three; Except the input NMOS transistor of below, between its excess-three nmos transistor drain and source electrode, be connected respectively a drain-source building-out capacitor, totally three; The described ultra broadband power amplification circuit of the third level is different from the ultra broadband drive amplification circuit of first utmost point, and the ultra broadband input circuit matching structure of the described ultra broadband power amplification circuit of the third level first connects after straight coupling capacitance and connects build-out resistor.
The drain voltage of described ultra broadband driving stage amplifying circuit and described ultra broadband power amplification circuit is connected direct current (DC) bias VDD by two sheet external inductances respectively, and inductance is at least 100nH.
In the adjustable quadravalence stacked structure of the gain capacitance compensation type amplifier of whole three grades gaining in adjustable Driver amplifier at a kind of 0.1～3GHz CMOS of the present invention, the size of the size of NMOS pipe and other DC feedback resistance, building-out capacitor, feedback resistance is to determine after the indices such as adjustable gain scope, bandwidth and power output of the whole circuit that considers.By layout design and the rational deployment in later stage, can realize better desired indices, realize that gain power-adjustable under the broadband condition of 0.1～3GHz amplifies, good input-output adapt ation characteristic, chip area is little and cost is low.Compare with adopting the distributed ultra wide-band power amplifier structure of transformer, multilevel resistance partial pressure type structure can be saved the area of chip greatly.
Below in conjunction with accompanying drawing, circuit of the present invention is described in further detail.
As shown in Figure 1, Ultrawideband CMOS of the present invention gains that adjustable driving radio-frequency power amplifier adopts is the structure for amplifying of three grades.The first order is ultra broadband driving stage, for realizing the ultra broadband gain of circuit; The second level is for the adjustable amplifying stage of gain, for realizing the adjustable dynamic range of high-gain; The third level is ultra broadband power output stage, can guarantee the ultra broadband power stage that whole circuit is larger, realizes the final amplification of radiofrequency signal.Whole circuit VDD can unify to adopt the DC power supply of 3.3V or 5V, and Vcc controls voltage range-3.3～3.3V.
Fig. 2 is the concrete implementing circuit figure under the CMOS technique based on shown in Fig. 1.
Radio-frequency input signals enters circuit by input Vin, by build-out resistor R1, every straight coupling capacitance Cm1, from transistor M4 grid, enter first order driving power level, after power amplification, drain electrode output from transistor M1, through every straight coupling capacitance Cm2 and series matching resistor R14, from the grid of transistor M8, enter second level power-amplifier stage, the drain electrode from transistor M5 after power amplification is exported, by arriving output every straight coupling capacitance Cout, complete power amplification.
The embodiment of the first order amplifier architecture of three stage gain adjustable power amplifiers is:
(1) by M1, M2, M3, tetra-transistor series of M4, joined, it is the drain electrode of the source electrode connection M2 of transistor M1, the source electrode of M2 connects the drain electrode of M3, the source electrode of M3 connects the drain electrode of M4, the source ground of M4, the ac input signal of this structure that is connected in series flows into from the grid of M4, to the drain electrode of M1, flows out.
(2) R3, R4, R5, R6, R7 series connection partial-pressure structure provides electric resistance partial pressure type bias voltage for each transistorized grid, and meanwhile, R3 is resistance-type negative feedback, between the drain and gate for M1, forms feedback network, thereby improves the indexs such as bandwidth of circuit.
(3) by M1, M2, the transistorized grid capacitance Cgs of M3, M4 and extra grid building-out capacitor C1, C2, C3, carries out capacitive voltage distribution.C1, C2, the value of C3 is through accurate analytical calculation, can be so that M1, M2, M3, M4 each transistorized drain-source voltage Vds, gate source voltage Vgs, drain-gate voltage Vdg realize Phase synchronization, thereby realized the synchronous stack of M1, M2, M3, the transistorized AC signal of M4, therefore, each M1, M2, the transistorized ac small signal of M3, M4 are superposed to M1 to the interchange large-signal of M4 cascaded structure integral body.In brief, M1, M2, each transistorized ac small signal of M3, M4 are connected in series together, and due to Phase synchronization, small-signal is superposed to large-signal.Because M1 strengthens (single transistor 4 times) to the cascaded structure voltage swing of M4, series current is constant, and (M1 is to M4 cascaded structure, while supposing that the electric current flowing through is constant), so this structure can work under large voltage swing and high-power signal (single transistor 4 times).Because this structure can work in large voltage swing characteristic, therefore can break through the restriction of the puncture voltage of stand CMOS.
(4) C4, C5, C6 form drain-source building-out capacitor, C4 is connected in the drain-source two ends of M1, C5 is connected in the drain-source two ends of M2, C6 is connected in the drain-source two ends of M3, high frequency gate leakage (gateleakage) in order to balance M1 to M4 cascaded structure, thus guarantee that this circuit structure (<6GHz) when high frequency also can normally work.Because when frequency is lower (<3GHz), M1, M2, the transistorized phase equalization of M3, M4 are better; During high frequency (>3GHz), phase equalization susceptibility between M1, M2, M3, M4 transistor uprises, grid building-out capacitor C1, C2, C3 produces slight gate leakage just can be so that M1, M2, the transistorized phase equalization of M3, M4 be damaged, during ac small signal stack, power loss strengthens, and reduces power gain.By drain-source building-out capacitor C4, C5, C6, produce drain-source and exchange feedback, can balance gate leakage, be specially the high frequency gate leakage that C4 balance C1 causes, the high frequency gate leakage that C5 balance C2 causes, the high frequency gate leakage that C6 balance C3 causes, thereby realized transistorized phase equilibrium, guaranteed the high-frequency gain of M1 to M4 cascaded structure.
(5) because M1 is constant to the watt level of M4 cascaded structure, voltage bias is single transistor 4 times, electric current is constant, therefore, the output optimum load impedance of this cascaded structure is 4 times of single transistor output optimum load impedance.In general, the output optimum load impedance of single tube power amplifier is Low ESR (for example 12 ohm), needs extra impedance matching structure to carry out 50 ohm of coupling designs of output circuit.Adopt that M1 is single tube to the best output load impedance of the power amplifier of M4 cascaded structure 4 times (12 ohm * 4 ≈ 50 ohm), more close to 50 ohm, therefore do not need extra match circuit, just can realize the output circuit impedance coupling of good ultra broadband.
(6) input circuit part adopts feedback resistance R2, build-out resistor R1 and every straight coupling capacitance Cm1, realizes the Broadband Matching of input circuit structure.In conventional RLC coupling, need to adopt inductance, but on-chip inductor area is larger, in order to realize the miniaturization of area, avoids adopting inductance to mate design.
Three stage gain adjustable power amplifier second level amplifiers, are gain adjustable amplifier, and embodiment is:
By M9, two transistors of M10, adopt common source, cathode-input amplifier form to be connected in series, it is the drain electrode of the source electrode connection M9 of transistor M10, the source ground of M9, first order output signal is by after the grid of M9, under the amplification of common source, cathode-input amplifier, enter into M10 drain electrode, as the output of second level gain adjustable amplifier.The drain electrode of M10 is connected with the DC feedback network of the first order by a DC feedback resistance R 15, for the whole second level provides drain electrode feed.The grid of M10 connects outside gain control signal Vcc, by varying in size of Vcc voltage, controls the power gain of M10 cathode-input amplifier, and then realizes the gain adjustable function of whole driving power amplifier module.
Three stage gain adjustable power amplifier third level amplifiers, adopt and the similar structure of the first order, and embodiment is:
(1) by M5, M6, M7, tetra-transistor series of M8, joined, it is the drain electrode of the source electrode connection M6 of transistor M5, the source electrode of M6 connects the drain electrode of M7, the source electrode of M7 connects the drain electrode of M8, the source ground of M8, the ac input signal of this structure that is connected in series flows into from the grid of M8, to the drain electrode of M5, flows out.
(2) R8, R9, R10, R11, R12 series connection partial-pressure structure provides electric resistance partial pressure type bias voltage for each transistorized grid, and meanwhile, R8 is resistance-type negative feedback, between the drain and gate for M5, forms feedback network.
(3) by M5, M6, the transistorized grid capacitance Cgs of M7, M8 and extra grid building-out capacitor C7, C8, C9, carries out capacitive voltage distribution.
(4) C10, C11, C12 form drain-source building-out capacitor, and C10 is connected in the drain-source two ends of M5, and C11 is connected in the drain-source two ends of M6, and C12 is connected in the drain-source two ends of M7, the high frequency gate leakage in order to balance M5 to M8 cascaded structure.
(5) similar with prime, rear class output circuit does not need extra match circuit, just can realize the output circuit impedance coupling of good ultra broadband.The input circuit part of rear class adopts feedback resistance R13, build-out resistor R14 and every straight coupling capacitance Cm2, realizes the inter-stage Broadband Matching of rear class input circuit structure.
The drain voltage of dual-stage amplifier is connected direct current (DC) bias VDD by the outer large inductance L 1 of sheet with L2, it is Cin every straight coupling capacitance that the sheet of whole twin-stage power amplifier is inputted outward, and it is Cout every straight coupling capacitance that sheet is exported outward.
By adjusting M1 to the transistorized size of M8, biasing and feedback resistance R1 are to the resistance value size of R14, and building-out capacitor C1 is to the size of C12, and the transistorized size of the M9 of gain control circuit and M10, the size of DC feedback resistance R 15.Can make that whole circuit has gain adjustable function, good input and output matching characteristic in 0.1～3GHz ultra broadband frequency range, chip area is little and cost is low.
Although in conjunction with figure, invention has been described above; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; rather than restrictive; those of ordinary skill in the art is under enlightenment of the present invention; in the situation that not departing from aim of the present invention, can also make a lot of distortion, within these all belong to protection of the present invention.
Claims (1)
1. 0.1～3GHz CMOS adjustable Driver amplifier that gains, it is characterized in that, comprise input matching circuit, ultra broadband driving stage amplifying circuit, gain adjustable amplifying circuit, ultra broadband power amplification circuit and output block isolating circuit, described ultra broadband driving stage amplifying circuit, gain adjustable amplifying circuit and ultra broadband power amplification circuit are active two ports and amplify network;
Described input matching circuit is by inputting dististyle outer capacitance, build-out resistor, feedback resistance and forming every straight coupling capacitance;
Described output block isolating circuit is by forming every straight coupling capacitance;
Described ultra broadband drive amplification circuit comprises four NMOS pipe, the outer capacitance of current biasing circuit and input chip; The mode that four NMOS transistors connects drain electrode according to source electrode is connected in series in turn, the multilevel resistance partial pressure type structure that the gate bias of four NMOS transistors adopts five resistance to form, the grid of each nmos pass transistor is connected on corresponding electric resistance partial pressure node, the grid of the nmos pass transistor of below is inputted as AC signal, and the drain electrode of the nmos pass transistor of the top is exported as AC signal; The input circuit of input NMOS transistor takes the mode of series matching resistor and electric capacity to mate, and adopts a feedback resistance that the series matching resistor of input NMOS transistor is connected with the drain electrode of output transistor with the node between electric capacity simultaneously; The outer large inductance of drain electrode contact pin of output transistor, another termination power vd of inductance D; Ultra broadband driving amplifier, except the input NMOS transistor of below, the gate bias node of its excess-three nmos pass transistor connects a grid building-out capacitor respectively, building-out capacitor other end ground connection; Except the input NMOS transistor of below, between the drain electrode of its excess-three nmos pass transistor and source electrode, be connected respectively a drain-source building-out capacitor;
Described gain adjustable amplifying circuit, adopt two NOMS transistors, according to common source, common grid mode, carry out power amplification, common grid amplifier gate bias voltage is gain control signal simultaneously, the variation of gain-controlled voltage size, controls whole three grades of gains that drive power amplifier;
Described ultra broadband power amplification circuit comprises four NMOS pipe, the outer capacitance of current biasing circuit and input chip; The mode that four NMOS transistors connects drain electrode according to source electrode is connected in series in turn, the multilevel resistance partial pressure type structure that the gate bias of four NMOS transistors adopts five resistance to form, the grid of each nmos pass transistor is connected on corresponding electric resistance partial pressure node, the grid of the nmos pass transistor of below is inputted as AC signal, and the drain electrode of the nmos pass transistor of the top is exported as AC signal; The input circuit of input NMOS transistor takes the mode of series matching resistor and electric capacity to mate, and adopts a feedback resistance that the series matching resistor of input NMOS transistor is connected with the drain electrode of output transistor with the node between electric capacity simultaneously; The outer large inductance of drain electrode contact pin of output transistor, another termination power vd of inductance D; Ultra broadband driving amplifier, except the input NMOS transistor of below, the gate bias node of its excess-three nmos pass transistor connects a grid building-out capacitor respectively, building-out capacitor other end ground connection; Except the input NMOS transistor of below, between the drain electrode of its excess-three nmos pass transistor and source electrode, be connected respectively a drain-source building-out capacitor; The ultra broadband input circuit matching structure of the circuit of the third level first connects after straight coupling capacitance and connects build-out resistor;
The drain voltage of described ultra broadband driving stage amplifying circuit and described ultra broadband power amplification circuit is connected direct current (DC) bias VDD by two sheet external inductances respectively, and inductance is at least 100nH.
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| CN113162564A (en) * | 2021-03-25 | 2021-07-23 | 成都知融科技股份有限公司 | CMOS power amplifier with on-chip temperature compensation function |
| CN114244293A (en) * | 2022-01-11 | 2022-03-25 | 中国航天科工集团八五一一研究所 | Radio frequency stack power amplifier adopting parallel capacitors |
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| US11777454B1 (en) * | 2022-05-16 | 2023-10-03 | Guangdong University Of Technology | Bias circuit for radio frequency power amplifier |
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| CN114793094A (en) * | 2022-06-20 | 2022-07-26 | 华南理工大学 | Adjustable gain low noise amplifier and receiver |
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