CN103595357A - 0.1-1.2GHz CMOS (complementary metal oxide semiconductor) ultra-wideband radiofrequency power amplifier - Google Patents
0.1-1.2GHz CMOS (complementary metal oxide semiconductor) ultra-wideband radiofrequency power amplifier Download PDFInfo
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- CN103595357A CN103595357A CN201310486290.0A CN201310486290A CN103595357A CN 103595357 A CN103595357 A CN 103595357A CN 201310486290 A CN201310486290 A CN 201310486290A CN 103595357 A CN103595357 A CN 103595357A
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Abstract
The invention discloses a 0.1-1.2GHz CMOS (complementary metal oxide semiconductor) ultra-wideband radiofrequency power amplifier which comprises multiple stages of amplifying circuits. The amplifying circuits include a driving-stage amplifying circuit, an intermediate-stage amplifying circuit, a power-output-stage amplifying circuit, a driving-stage active biasing and matching circuit, an intermediate-stage active biasing and matching circuit and an output-stage active biasing and matching circuit; the driving-stage amplifying circuit is used for acquiring gain of the integral amplifier and guaranteeing that requirements on input matching (of S11 parameters) of the integral circuits can be met; the intermediate-stage amplifying circuit is used for guaranteeing the gain, the efficiency and inter-stage matching of the integral circuits; the power-output-stage amplifying circuit is used for guaranteeing excellent output matching (of S22 parameters) and power output of the integral circuits. The 0.1-1.2GHz CMOS ultra-wideband radiofrequency power amplifier has the advantages that a COMS Si process is adopted, so that input and output singly balanced circuits for the integral circuits can be omitted by a single-end structure, the area of a chip can be saved, and the performance of the integral circuits can be improved.
Description
Technical field
The present invention relates to CMOS (Complementary Metal Oxide Semiconductor) (CMOS) radio-frequency power amplifier and integrated electric field, particularly a kind of CMOS ultra-wide band radio-frequency power amplifier of Industry-oriented private network application.
Background technology
Along with the fast development of Modern wireless communication technology, constantly promote that radio-frequency front-end transceiver is integrated to height, low-power consumption, compact conformation, cheap future development.Power amplifier (abbreviation power amplifier) is requisite part in wireless launcher, is also maximum parts that consume energy in whole transmitter, and power output is generally larger.At present, people are also more and more higher to the requirement of Designing power amplifier, particularly the consideration of the aspect such as the power of power amplifier, efficiency, bandwidth and linearity.So in present radio system, wideband power amplifer has very important status, the quality of its performance will directly affect the working condition of whole radio system.
With respect to other wireless transceiving component, high-power, high linearity, high efficiency are the prime design requirements of power amplifier.The progress of CMOS technique, except improving the operational frequency bandwidth of power amplifier, strengthens the difficulty of improving of the indexs such as power output, the linearity, PAE, implements more difficult.From frequency domain, ultra broadband is different from traditional arrowband and broadband, and its frequency band is wider.At present, the broadband wireless access equipment of frequency within the scope of 100MHz-1.2GHz is mainly used in trade Special Network, but the frequency of trade Special Network and bandwidth are of a great variety, standard disunity.China starts late for the development of wideband power amplifer, especially CMOS wideband power amplifer.And trade Special Network radio frequency front end chip majority used is monopolized by offshore company at present.Trade Special Network core devices is applied external chip and is also had problems.Therefore, we need research and development to have the radio frequency front end chip of independent intellectual property right very urgently.
Summary of the invention
For above-mentioned prior art, the invention provides the CMOS ultra-wide band radio-frequency power amplifier of a kind of 0.1～1.2GHz, the design of the ultra-wide band radio-frequency power amplifier circuit chip of the 0.1～1.2GHz applying for Industry-oriented private network, it has enough gains, bandwidth and power output, and has the good linearity.
In order to solve the problems of the technologies described above, the CMOS ultra-wide band radio-frequency power amplifier of a kind of 0.1～1.2GHz of the present invention, comprise multistage amplifier circuit, multistage amplifier circuit is for realizing the gain of whole amplifier, and the Input matching (S11 parameter) that guarantees whole circuit reaches requirement, described multistage amplifier circuit comprises input capacitance C1, driving stage biasing and input matching circuit, driving stage amplifying circuit, inter-stage capacitance C2, intergrade biasing and intervalve matching circuit, intergrade amplifying circuit, inter-stage capacitance C3, power stage biasing and intervalve matching circuit, power stage amplifying circuit, output capacitance C4 and chip power, described chip power adopts voltage node VDD, described intergrade amplifying circuit is for guaranteeing gain, efficiency and the interstage matched of whole circuit, power output stage amplifying circuit is for guaranteeing good output matching (S22 parameter) and the power stage of whole circuit.Described driving stage amplifying circuit comprises NMOS pipe M1 and the NMOS pipe M2 of two Cascodes, a sheet external inductance L0, and its inductance value is at least 100nH; Described intergrade amplifying circuit comprises NMOS pipe M4 and the NMOS pipe M5 of two Cascodes, a sheet external inductance L1, and its inductance value is at least 100nH; Described power stage amplifying circuit comprises NMOS pipe M7 and a sheet external inductance L2 of a common source configuration, its inductance value is at least 100nH, between the leakage level of described NMOS pipe M7 and grid level, be provided with feedback resistance Rf, described feedback resistance Rf is used for improving output matching, bandwidth gain flatness and stability.Described driving stage biasing and input matching circuit, intergrade biasing and intervalve matching circuit are identical with power stage biasing and intervalve matching circuit structure, include respectively NMOS pipe, the first resistance and second resistance, in described driving stage amplifying circuit, the source ground of described NMOS pipe M2, the grid of described NMOS pipe M2 is by driving the input Vin that is connected to amplifier after described driving stage biasing and input matching circuit and input capacitance C1, the drain electrode of described NMOS pipe M2 is connected with the source electrode of described NMOS pipe M1, the gate bias of described NMOS pipe M1 is connected to voltage node VDD, the drain electrode of described NMOS pipe M1 is connected with described external inductance L0, another termination voltage node VDD of described external inductance L0, in described intergrade amplifying circuit, adopt bias structure and the structure for amplifying identical with driving stage amplifying circuit, be in described intergrade amplifying circuit, the source ground of described NMOS pipe M5, the grid of described NMOS pipe M5 by intergrade, setover and intervalve matching circuit and inter-stage capacitance C2 after be connected to the drain electrode of described NMOS pipe M1, the drain electrode of described NMOS pipe M5 is connected with the source electrode of described NMOS pipe M4, the gate bias of described NMOS pipe M4 is chip power, be node VDD, the drain electrode of described NMOS pipe M4 is connected with described external inductance L1, another termination voltage node VDD of described external inductance L1, described power stage amplifying circuit adopts the bias structure identical with front two-stage, in described power stage amplifying circuit, the source ground of described NMOS pipe M7, the grid of described NMOS pipe M7 by power stage, setover and intervalve matching circuit and inter-stage capacitance C3 after be connected to the drain electrode of described NMOS pipe M4, the drain electrode of described NMOS pipe M7 is connected with described external inductance L2, drain electrode and the described output capacitance C4 of described NMOS pipe M7 and connect after be connected to the output port Vout of amplifier, another termination voltage node VDD of described external inductance L2.
Compared with prior art, the invention has the beneficial effects as follows:
The present invention, for for realizing broadband power output and the higher gain under CMOS technique, adopts the single-ended category-A circuit structure of three grades, can produce the good linearity thus.The first order in amplifier of the present invention is driving stage, is used for realizing the gain of whole amplifier and the Input matching of circuit; The second level is the middle transition level of circuit, for realizing the adjustment of whole circuit gain and interstage matched; The third level is power output stage, for guaranteeing final good output matching and the maximum power output of circuit.The present invention adopts CMOS Si technique, uses single-ended structure can make whole circuit save input and output Ba Lun, thus can saving chip area and promote the performance of whole circuit.
Accompanying drawing explanation
Fig. 1 is the functional-block diagram of CMOS ultra-wide band radio-frequency power amplifier of the present invention;
Fig. 2 is the circuit theory diagrams of CMOS ultra-wide band radio-frequency power amplifier embodiment of the present invention.
Fig. 3 is the stability Kf value curve chart of amplifier of the present invention;
Fig. 4 is the S parametric plot of amplifier of the present invention;
Fig. 5 is the output power curve figure of amplifier of the present invention;
Fig. 6 is the power added efficiency curve chart of amplifier of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, circuit of the present invention is described in further detail.
As shown in Figure 1, the CMOS ultra-wide band radio-frequency power amplifier of a kind of 0.1～1.2GHz of the present invention, what adopt is three grades of single-ended structure for amplifying, the unified 3.3V of employing powers, comprise that the first order is the high-gain that driving stage amplifying circuit is used for realizing circuit, the second level is that intergrade amplifying circuit is for guaranteeing gain, efficiency and the interstage matched of whole circuit; The third level is output matching and the final larger power stage of power stage amplification grade circuit for guaranteeing that whole circuit is good.Described circuit also comprises the active biased and match circuit of driving stage, intergrade is active biased and match circuit and output stage is active biased and match circuit.
As shown in Figure 2, described driving stage amplifying circuit comprises NMOS pipe M1 and the NMOS pipe M2 of two cascodes, a sheet external inductance L0, and inductance value is greater than 100nH; Described intergrade amplifying circuit comprises NMOS pipe M4 and the NMOS pipe M5 of two cascodes, a sheet external inductance L1, and inductance value is greater than 100nH; Described power output stage amplifying circuit comprises NMOS pipe M7 and a sheet external inductance L2 of a common source configuration, and inductance value is greater than 100nH, between the leakage level of described NMOS pipe M7 and grid level, is provided with feedback resistance Rf; Described driving stage active biased with match circuit, that intergrade is active biased is active biased identical with match circuit structure with match circuit and output stage, includes respectively a NMOS pipe, the first resistance, the second resistance.
In described driving stage amplifying circuit, the source ground of described NMOS pipe M2, the grid of described NMOS pipe M2 is connected to the input Vin of amplifier after active biased and input matching circuit and the outer capacitance C1 of sheet by driving stage, the drain electrode of described NMOS pipe M2 is connected with the source electrode of described NMOS pipe M1, the gate bias of described NMOS pipe M1 meets voltage node VDD, the drain electrode of described NMOS pipe M1 is connected with described external inductance L0, another termination voltage node VDD of described external inductance L0; In the active biased and match circuit of described driving stage, the drain electrode of NMOS pipe M0 first resistance R 0 of connecting is connected to voltage node VDD, and the grid of described NMOS pipe M0 is connected with drain electrode, and connects after the second resistance R 1 grid of managing M1 to described NMOS and be biased.
In described intergrade amplifying circuit, the source ground of described NMOS pipe M5, the grid of described NMOS pipe M5 is connected to the drain electrode of described NMOS pipe M1 after capacitance C2 in active biased and intervalve matching circuit and sheet by intergrade, the drain electrode of described NMOS pipe M5 is connected with the source electrode of described NMOS pipe M4, the gate bias of described NMOS pipe M4 meets voltage node VDD, the drain electrode of described NMOS pipe M4 is connected with described external inductance L1, another termination voltage node VDD of described external inductance L1; In the active biased and match circuit of described intergrade, the drain electrode of NMOS pipe M3 first resistance R 2 of connecting is connected to voltage node VDD, and the grid of described NMOS pipe M3 is connected with drain electrode, and connects after the second resistance R 3 grid of managing M5 to described NMOS and be biased.
In described power output stage amplifying circuit, the source ground of described NMOS pipe M7, the grid of described NMOS pipe M7 is connected to the drain electrode of described NMOS pipe M4 after capacitance C3 in the sheet in active biased and intervalve matching circuit by power output stage, the drain electrode of described NMOS pipe M7 is connected with described external inductance L2, the drain electrode of described NMOS pipe M7 also meets the output port Vout that is connected to amplifier outside a sheet after capacitance C4, described outer capacitance C4 is for preventing extra DC power, another termination voltage node VDD of described external inductance L2.In the active biased and match circuit of described power stage, the drain electrode of NMOS pipe M6 first resistance R 4 of connecting is connected to voltage node VDD, and the grid of described NMOS pipe M6 is connected with drain electrode, and connects after the second resistance R 5 grid of managing M7 to described NMOS and be biased.It is for obtaining the larger Voltage-output amplitude of oscillation that power output stage amplifying circuit in the present invention adopts common source structure for amplifying, thereby guarantees that whole circuit obtains maximum power output.And common source configuration can be saved than cascodes the area of a part of chip, can reach equally desired power stage index.
The course of work of CMOS ultra-wide band radio-frequency power amplifier of the present invention is as follows:
As shown in Figure 2, first, radiofrequency signal is driving stage amplifying circuit from the input Vin of the amplifier first order that electric capacity C1 sheet enters amplifying circuit of flowing through, NMOS pipe M0 produces voltage bias and through the second resistance R 1, is added in the grid of this amplifying circuit under the effect of power vd D, under the effect of bias voltage, the NMOS of two cascodes pipe M1 and NMOS pipe M2 start working.Signal flows into bank tube altogether through common source pipe and also finally from its drain terminal, exports.Due to the effect of drain terminal sheet external inductance L0, the drain terminal that signal can not managed M2 from NMOS flows out to vdd terminal.Finally, after the drive amplification circuit amplification of signal through the first order, through capacitor C in the sheet of inter-stage 2, flow in the intergrade amplifying circuit of the second level.
Under the identical biasing circuit effect of the driving stage amplifying circuit with the first order, the intergrade amplifying circuit cascode amplifier of the second level also starts signal to amplify, and exports through drain terminal.Sheet external inductance L1 is identical with the first order with 3 effects of capacitor C in inter-stage sheet.
Signal, from second level circuit flows out, flows into the power output stage amplifying circuit of the third level through inter-stage capacitor C in sheet 3.Equally, under biasing circuit effect, third level common source amplifying circuit is started working, and signal is further amplified.NMOS pipe M7 adopts common source configuration to produce larger output voltage swing, simultaneously can saving chip area.Feedback resistance Rf and NMOS pipe M7 between NMOS pipe M7 drain-gate form feedback loop, can improve the Broadband emission coupling of circuit.Thus, the outer electric capacity C4 of power output stage sheet external inductance L2 and sheet and feedback resistance Rf acting in conjunction, make whole amplifier circuit obtain best output matching, thereby realize maximum power output.
In whole wideband amplification circuit design process, the size of each transistor and resistance capacitance is to determine after the indices such as bandwidth, gain, power output and efficiency of the whole circuit that considers.And layout design and rational deployment by the later stage are optimized, can farthest realize every output-index of requirement, the high-gain of realization under the ultra broadband of 0.1～1.2GHz, high linearity, larger power output and efficiency, and take less chip area.
With a design example, illustrate below.In actual design, get all NMOS pipes of front two-stage M0～M5 grid width/grid long than being 200um/0.35um,, third level NMOS pipe M6 and M7 size are 400um/0.35um; Resistance R 0 is 167ohm, and R1 is 30ohm, and R2 is 317ohm, and R3 is 220ohm, and R4 is 500ohm, and R5 is 230ohm, and feedback resistance Rf is 840ohm; Sheet outer capacitance C1, C4 are 1uF, and C2, C3 are 20pF; Inductance L 0, L1, L2 all get 200nH.
Be illustrated in figure 3 the stability Kf value simulation result of power amplifier of the present invention, when Kf value is greater than 1, amplifier is stable.As can be seen from the figure, in whole 0.1～1.2GHz frequency range, Kf value is all greater than 4.8e5, so this circuit is stable.
Be illustrated in figure 4 the S parameter curve simulation result of this power amplifier.As can be seen from the figure,, in whole band limits, gain curve S21 is all more than 28dB; Input and output return loss S11 and S22 all-below 10dB, mostly in-20dB left and right; Be less than-150dB of isolation S12.
Be illustrated in figure 5 the output power curve figure of power amplifier of the present invention.As can be seen from the figure, the saturation output power of power amplifier is 21.6dBm.
Be illustrated in figure 6 the power added efficiency curve chart of power amplifier of the present invention.As can be seen from the figure,, under the saturated condition of power output, the efficiency of this amplifier is 35% left and right.
The simulation result of complex chart 3, Fig. 4, Fig. 5 and Fig. 6 is known, and power amplifier of the present invention has good performance index in 0.1～1.2GHz frequency range, can meet the requirement of design.
Although in conjunction with figure, invention has been described above; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; rather than restrictive; those of ordinary skill in the art is under enlightenment of the present invention; in the situation that not departing from aim of the present invention, can also make a lot of distortion, within these all belong to protection of the present invention.
Claims (2)
1. the CMOS ultra-wide band radio-frequency power amplifier of a 0.1～1.2GHz, comprise multistage amplifier circuit, it is characterized in that, multistage amplifier circuit comprises input capacitance C1, driving stage biasing and input matching circuit, driving stage amplifying circuit, inter-stage capacitance C2, intergrade biasing and intervalve matching circuit, intergrade amplifying circuit, inter-stage capacitance C3, power stage biasing and intervalve matching circuit, power stage amplifying circuit, output capacitance C4 and chip power, and described chip power adopts voltage node VDD;
Described driving stage amplifying circuit comprises NMOS pipe M1 and the NMOS pipe M2 of two Cascodes, a sheet external inductance L0, and its inductance value is at least 100nH;
Described intergrade amplifying circuit comprises NMOS pipe M4 and the NMOS pipe M5 of two Cascodes, a sheet external inductance L1, and its inductance value is at least 100nH;
Described power stage amplifying circuit comprises NMOS pipe M7 and a sheet external inductance L2 of a common source configuration, and its inductance value is at least 100nH, between the leakage level of described NMOS pipe M7 and grid level, is provided with a feedback resistance Rf;
Described driving stage biasing and input matching circuit, intergrade biasing and intervalve matching circuit are identical with power stage biasing and intervalve matching circuit structure, include respectively NMOS pipe, the first resistance and second resistance;
In described driving stage amplifying circuit, the source ground of described NMOS pipe M2, the grid of described NMOS pipe M2 is by driving the input Vin that is connected to amplifier after described driving stage biasing and input matching circuit and input capacitance C1, the drain electrode of described NMOS pipe M2 is connected with the source electrode of described NMOS pipe M1, the gate bias of described NMOS pipe M1 is connected to voltage node VDD, the drain electrode of described NMOS pipe M1 is connected with described external inductance L0, another termination voltage node VDD of described external inductance L0;
In described intergrade amplifying circuit, the source ground of described NMOS pipe M5, the grid of described NMOS pipe M5 by intergrade, setover and intervalve matching circuit and inter-stage capacitance C2 after be connected to the drain electrode of described NMOS pipe M1, the drain electrode of described NMOS pipe M5 is connected with the source electrode of described NMOS pipe M4, the gate bias of described NMOS pipe M4 is connected to described voltage node VDD, the drain electrode of described NMOS pipe M4 is connected with described external inductance L1, another termination voltage node VDD of described external inductance L1;
In described power stage amplifying circuit, the source ground of described NMOS pipe M7, the grid of described NMOS pipe M7 by power stage, setover and intervalve matching circuit and inter-stage capacitance C3 after be connected to the drain electrode of described NMOS pipe M4, the drain electrode of described NMOS pipe M7 is connected with described external inductance L2, drain electrode and the described output capacitance C4 of described NMOS pipe M7 and connect after be connected to the output port Vout of amplifier, another termination voltage node VDD of described external inductance L2.
2. the CMOS ultra-wide band radio-frequency power amplifier of 0.1～1.2GHz according to claim 1, wherein, the drain electrode of NMOS pipe M0 in the biasing of described driving stage and input matching circuit first resistance R 0 of connecting is connected to voltage node VDD, the grid of described NMOS pipe M0 be connected with drain electrode and connect with the second resistance R 1 after to described NMOS, manage M1 grid be biased.
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Cited By (7)
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| CN105577126A (en) * | 2015-12-15 | 2016-05-11 | 清华大学 | Distributed amplifier circuit topological structure for inter-stage matching of graphene transmission line |
| CN106301255A (en) * | 2016-11-04 | 2017-01-04 | 杭州迦美信芯通讯技术有限公司 | Wideband power amplifer and active matching circuit thereof |
| CN108336976A (en) * | 2018-02-07 | 2018-07-27 | 广州慧智微电子有限公司 | A kind of multiband low-noise amplifier and amplification method |
| CN112003574A (en) * | 2020-07-14 | 2020-11-27 | 天津工业大学 | K-waveband CMOS high-efficiency radio frequency power amplifier circuit |
| CN112702029A (en) * | 2021-03-25 | 2021-04-23 | 成都知融科技股份有限公司 | CMOS power amplifier chip with on-chip integrated detection function |
| CN112910420A (en) * | 2021-01-18 | 2021-06-04 | 温州大学 | High-linearity radio frequency power amplifier |
| CN113612450A (en) * | 2021-10-09 | 2021-11-05 | 成都嘉纳海威科技有限责任公司 | Ultra-wideband driving amplification circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105577126A (en) * | 2015-12-15 | 2016-05-11 | 清华大学 | Distributed amplifier circuit topological structure for inter-stage matching of graphene transmission line |
| CN106301255A (en) * | 2016-11-04 | 2017-01-04 | 杭州迦美信芯通讯技术有限公司 | Wideband power amplifer and active matching circuit thereof |
| CN106301255B (en) * | 2016-11-04 | 2023-05-12 | 杭州迦美信芯通讯技术有限公司 | Broadband power amplifier and active matching circuit thereof |
| CN108336976A (en) * | 2018-02-07 | 2018-07-27 | 广州慧智微电子有限公司 | A kind of multiband low-noise amplifier and amplification method |
| CN112003574A (en) * | 2020-07-14 | 2020-11-27 | 天津工业大学 | K-waveband CMOS high-efficiency radio frequency power amplifier circuit |
| CN112003574B (en) * | 2020-07-14 | 2024-02-09 | 天津工业大学 | K-band CMOS efficient radio frequency power amplifier circuit |
| CN112910420A (en) * | 2021-01-18 | 2021-06-04 | 温州大学 | High-linearity radio frequency power amplifier |
| CN112702029A (en) * | 2021-03-25 | 2021-04-23 | 成都知融科技股份有限公司 | CMOS power amplifier chip with on-chip integrated detection function |
| CN113612450A (en) * | 2021-10-09 | 2021-11-05 | 成都嘉纳海威科技有限责任公司 | Ultra-wideband driving amplification circuit |
| CN113612450B (en) * | 2021-10-09 | 2022-01-04 | 成都嘉纳海威科技有限责任公司 | Ultra-wideband driving amplification circuit |
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