CN107743021B - High-mismatch-resistance high-efficiency power amplifier based on transistor stacking technology - Google Patents
High-mismatch-resistance high-efficiency power amplifier based on transistor stacking technology Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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Abstract
The invention discloses a high-efficiency power amplifier with strong mismatch resistance based on a transistor stacking technology, which comprises a-45 DEG phase-shifting input matching network, a +45 DEG phase-shifting input matching network, a two-way balance type three-stack power amplifying network, a +45 DEG phase-shifting output matching network, a-45 DEG phase-shifting output matching network, a first power supply bias network and a second power supply bias network. The invention adopts the three-stacked transistor amplifying network to realize the amplifying function of the balanced type amplifier, improves the power gain and the power capacity of the balanced type power amplifier, simultaneously utilizes the three-stage T-shaped filtering phase-shifting circuit to realize the +/-45 DEG phase-shifting control and the input and output impedance matching of two paths of balanced signals, and greatly improves the mismatch resistance characteristic of the amplifier on the premise of ensuring low insertion loss and high efficiency, thereby improving the stability and the reliability of the circuit. The high-mismatch-resistance high-efficiency power amplifier chip circuit is high in output power, high in power gain and small in area.
Description
Technical Field
The invention belongs to the technical field of field effect transistor microwave millimeter wave power amplifiers and integrated circuits, and particularly relates to a design of a high-mismatch-resistance high-efficiency power amplifier based on a transistor stacking technology.
Background
Along with the rapid development of civil communication markets such as 3G, 4G-LTE and the like and the early-stage layout of 5G communication, the microwave millimeter wave front-end transmitter also develops towards the directions of high performance, high integration and high efficiency of microwave millimeter wave frequency bands; in addition, due to the wide application of the MIMO technology, the system provides a serious test for the mismatch resistance of the terminal power amplifier, so that the market urgent needs a strong mismatch resistance and high efficiency power amplifier chip aiming at the microwave and millimeter wave frequency band.
However, in the design of microwave millimeter wave power amplifier chips, there are always some design challenges, which are embodied as follows:
(1) The strong mismatch resistance characteristic and the high efficiency index in the traditional balance type amplifier are mutually restricted: because the output end of the power amplifier in the microwave millimeter wave front end transmitter needs to be connected with an antenna with poor standing wave characteristic, the antenna provides serious challenges for the mismatch resistance characteristic of the microwave millimeter wave power amplifier; the existing balance type power amplifier for realizing 90-degree phase shift based on Langerhans structure is capable of enhancing mismatch resistance and simultaneously introducing larger in-band interpolation loss into an input matching network and an output matching network, so that the efficiency of the power amplifier is reduced. Therefore, the strong mismatch resistance and the high efficiency index in the conventional balanced amplifier are mutually restricted.
(2) The design difficulty of the high-power and high-gain indexes of the traditional balanced amplifier in the microwave millimeter wave frequency band is high: due to the driving of the 5G market in the future, a microwave millimeter wave front-end transmitter is urgently required to be provided with a high-gain, high-power, high-efficiency and strong-mismatch-resistance power amplifier, but an application circuit of the traditional millimeter wave frequency band is required to adopt a semiconductor process transistor with smaller gate length, and the voltage swing of the power amplifier is greatly limited due to the influence of the low breakdown voltage of the semiconductor process transistor, so that the power capacity of the power transistor is limited.
The most typical amplifier with strong mismatch resistance is a balanced power amplifier adopting a 90 DEG phase shift lange structure, however, in the microwave millimeter wave band, the conventional lange balanced amplifier still has some design defects, mainly expressed in that:
(1) The design difficulty of the strong mismatch resistance characteristic and the high efficiency index is high.
In order to improve the anti-mismatch characteristic of the circuit, a designer often needs to utilize a lange structure to realize 90-degree phase shift of two paths of balanced structure signals, and also needs to reduce the introduced in-band loss as much as possible, and meanwhile, the two paths of balanced signals are guaranteed to have approximately the same in-band loss. In order to compromise each design index, a designer often needs to implement 90 ° phase shift and impedance matching by introducing a certain in-band loss, which greatly reduces the efficiency index of the power amplifier.
(2) The impedance matching difficulty of the millimeter wave band high-power transistor is high.
Because the amplifier operates in the millimeter wave band, the power capacity of a single transistor is limited, and a designer often needs a 2 n-times power synthesis structure in order to obtain a higher power capacity, the structure often leads to a very low optimal load impedance of an output network, and the low load impedance leads to an increased impedance matching difficulty of the microwave millimeter wave band balanced amplifier.
Disclosure of Invention
The invention aims to provide a high-mismatch-resistance high-efficiency power amplifier based on a transistor stacking technology, which utilizes a three-transistor stacking technology and a +/-45 DEG phase-shifting input and output matching network corresponding to the three-transistor stacking technology to realize indexes such as high gain, high efficiency, high mismatch resistance and the like of microwave and millimeter wave frequency bands.
The technical scheme of the invention is as follows: a high-efficiency power amplifier with strong mismatch resistance based on transistor stacking technology comprises a-45 DEG phase-shifting input matching network, a +45 DEG phase-shifting input matching network, a double-path balanced three-stack power amplifying network, a +45 DEG phase-shifting output matching network, a-45 DEG phase-shifting output matching network, a first power supply bias network and a second power supply bias network.
The input end of the-45 DEG phase-shifting input matching network is connected with the input end of the +45 DEG phase-shifting input matching network to serve as the input end of the whole power amplifier; the output end of the +45 DEG phase-shifting output matching network is connected with the output end of the-45 DEG phase-shifting output matching network to serve as the output end of the whole power amplifier. The input end of the power amplifier is also connected with a blocking capacitor C 1 The output end of the power amplifier is also connected with a blocking capacitor C 9 。
The first input end of the two-way balance type three-stack power amplification network is connected with the output end of the-45 DEG phase-shifting input matching network, the second input end of the two-way balance type three-stack power amplification network is connected with the output end of the +45 DEG phase-shifting input matching network, the first output end of the two-way balance type three-stack power amplification network is connected with the input end of the +45 DEG phase-shifting output matching network, and the second output end of the two-way balance type three-stack power amplification network is connected with the input end of the-45 DEG phase-shifting output matching network.
The first power supply bias network is respectively connected with a-45 DEG phase-shifting input matching network, a double-path balanced type three-stack power amplification network and a +45 DEG phase-shifting output matching network; the second power supply bias network is respectively connected with the +45 DEG phase-shifting input matching network, the two-way balance type three-stack power amplification network and the-45 DEG phase-shifting output matching network.
The beneficial effects of the invention are as follows: the invention adopts the three-stacked transistor amplifying network to realize the amplifying function of the balanced type amplifier, improves the power gain and the power capacity of the balanced type power amplifier, simultaneously utilizes the three-stage T-shaped filtering phase-shifting circuit to realize the +/-45 DEG phase-shifting control and the input and output impedance matching of two paths of balanced signals, and greatly improves the mismatch resistance characteristic of the amplifier on the premise of ensuring low insertion loss and high efficiency, thereby improving the stability and the reliability of the circuit.
Further, -45 ° phase-shifted input matching network comprising a first T-type LC network circuit; one end of the first T-shaped LC network circuit is used as an input end of the-45 DEG phase-shifting input matching network, and the other end of the first T-shaped LC network circuit is connected in series with the first RC stabilizing circuit and then used as an output end of the-45 DEG phase-shifting input matching network. The +45° phase shift input matching network includes a second T-LC network circuit; one end of the second T-shaped LC network circuit is used as an input end of the +45 DEG phase-shifting input matching network, and the other end of the second T-shaped LC network circuit is connected in series with the second RC stabilizing circuit and then used as an output end of the +45 DEG phase-shifting input matching network.
Wherein the first T-type LC network circuit comprises a series inductance L 1 And L is equal to 2 And is connected in parallel with L 1 And L is equal to 2 Ground capacitance C on connection node 2 The method comprises the steps of carrying out a first treatment on the surface of the The second T-type LC network circuit comprises a capacitor C connected in series 3 And C 4 And is connected in parallel with C 3 And C 4 Grounding inductance L on connection node 3 . The first RC stabilizing circuit and the second RC stabilizing circuit have the same structure; the first RC stabilizing circuit comprises a resistor R connected in parallel gsbu And capacitor C gsbu The method comprises the steps of carrying out a first treatment on the surface of the The second RC stabilizing circuit comprises a resistor R connected in parallel gsbw And capacitor C gsbw 。
The +45° phase-shift output matching network comprises a third T-type LC network circuit; one end of the third T-shaped LC network circuit is used as the output end of the +45 DEG phase-shifting output matching network, and the other end is connected with an inductor L in series 4 Then the phase shift output is used as an input end of a +45° phase shift output matching network; third T-type LC network circuit and L 4 A grounding capacitor C is also connected to the connection node of (2) 5 . The-45 DEG phase-shifting output matching network comprises a fourth T-type LC network circuit; one end of the fourth T-shaped LC network circuit is used as an output end of the-45 DEG phase-shifting output matching network, and the other end is connected with an inductor L in series 8 Then the phase shift output is used as the input end of a-45 DEG phase shift output matching network; fourth T-type LC network circuit and L 8 A grounding capacitor C is also connected to the connection node of (2) 10 。
Wherein the third T-type LC network circuit comprises a capacitor C connected in series 6 And C 7 And is connected in parallel with C 6 And C 7 Grounding inductance L on connection node 5 The method comprises the steps of carrying out a first treatment on the surface of the The fourth T-type LC network circuit comprises an inductor L connected in series 6 And L is equal to 7 And is connected in parallel with L 6 And L is equal to 7 Ground capacitance C on connection node 8 。
The beneficial effects of the above-mentioned further scheme are: the invention adopts two three-stage T-shaped filtering phase shifting circuits to respectively realize + -45 DEG phase shifting control and input and output impedance matching of two paths of balanced signals, and the two paths of signals can be independently controlled, thereby greatly reducing design complexity, avoiding introducing unnecessary in-band loss and improving efficiency index of the power amplifier.
Further, the two-way balance type three-stack power amplification network comprises a first three-stack power amplification network and a second three-stack power amplification network, the first three-stack power amplification network and the second three-stack power amplification network have the same structure and comprise one or more parallel stack structures, and each stack structure comprises a group of top layer transistors, middle layer transistors and bottom layer transistors which are formed by stacking sequentially according to source electrode-drain electrode connection; the top layer transistor, the middle layer transistor and the bottom layer transistor are the same in size.
In the first path of three-stack power amplification network, the drain electrode of each top layer transistor is connected to serve as a first output end of the two-path balanced three-stack power amplification network; the grid electrode of each top layer transistor is respectively connected with a first power supply bias network and one path of compensation circuit; the grid electrode of each intermediate layer transistor is respectively connected with a first power supply bias network and one path of compensation circuit; the source electrode of each bottom layer transistor is grounded; the gate of each bottom layer transistor is connected as a first input terminal of the two-way balance type three-stack power amplification network.
In the second path three-stack power amplification network, the drain electrode of each top layer transistor is connected to serve as a second output end of the two-path balanced three-stack power amplification network; the grid electrode of each top layer transistor is respectively connected with a second power supply bias network and one path of compensation circuit; the grid electrode of each intermediate layer transistor is respectively connected with a second power supply bias network and one path of compensation circuit; the source electrode of each bottom layer transistor is grounded; the gate of each bottom layer transistor is connected as a second input terminal of the two-way balance type three-stack power amplification network.
The compensation circuit comprises a grid stabilizing resistor and a grid compensation capacitor which are connected in series, and the other end of the grid compensation capacitor is grounded.
The beneficial effects of the above-mentioned further scheme are: the core of the inventionThe heart amplifier architecture adopts a three-stack amplifying network, and can improve the power gain by 3-5 dB only by adopting a one-stage three-stack amplifying structure, thereby greatly simplifying the circuit complexity. Meanwhile, because the output impedance of the three-stack amplifying network is higher than that of the traditional common source amplifier, the two-way balance type three-stack power amplifying network can also adopt 2 n The multiple parallel multi-path stacked amplifier structure can still ensure relatively high output load impedance. In addition, the gate compensation capacitor of the three-stacked amplifying network is a capacitor with a smaller capacitance value, and is used for realizing synchronous swing of gate voltage, and in order to realize stability in millimeter wave frequency band, a series stable resistor is needed, while the stacked gate compensation capacitor of the traditional Cascode transistor is a capacitor with a larger capacitance value, and is used for realizing AC grounding of the gate, and no series stable resistor is needed.
Further, the first power supply bias network and the second power supply bias network have the same structure and both comprise an input power supply bias circuit and an amplifying and output power supply bias circuit.
In the first power supply bias network, the input power supply bias circuit comprises a resistor R connected in series gb1u And inductance L ggu Resistance R gb1u And inductance L ggu A grounding capacitor C is also connected to the connection node of (2) ggu The method comprises the steps of carrying out a first treatment on the surface of the Resistor R gb1u The other end of the first voltage bias power supply VGGu is connected with the other end of the first voltage bias power supply VGGu; inductance L ggu The other end of the first RC stabilizing circuit is connected with a connecting node of a first T-shaped LC network circuit and a first RC stabilizing circuit in a-45 DEG phase-shifting input matching network. In the first power supply bias network, the amplifying and output power supply bias circuit comprises resistors R which are sequentially connected in series gb4u 、R gb5u 、R gb6u Inductance L ddu The method comprises the steps of carrying out a first treatment on the surface of the Resistor R gb4u The other end of the first electrode is grounded; resistor R gb4u And R is R gb5u Through resistor R gb2u The first path of the third stacked power amplification network is connected with the grid electrode of each middle layer transistor in the first path of the third stacked power amplification network respectively; resistor R gb5u And R is R gb6u Through resistor R gb3u The first channel of the third stacked power amplification network is connected with the grid electrode of each top layer transistor in the first channel of the third stacked power amplification network respectively; resistor R gb6u And inductance L ddu Is connected with the joint of (a)The points are also respectively connected with a grounding capacitor C ddu And a first high voltage bias power supply VDDu; inductance L ddu The other end of the (C) and +45° phase-shifting output matching network is provided with a third T-shaped LC network circuit and an inductor L 4 Is connected to the connection node of (c).
In the second power supply bias network, the input power supply bias circuit comprises a resistor R connected in series gb1w And inductance L ggw Resistance R gb1w And inductance L ggw A grounding capacitor C is also connected to the connection node of (2) ggw The method comprises the steps of carrying out a first treatment on the surface of the Resistor R gb1w The other end of the first low-voltage bias power supply VGGw is connected with a second low-voltage bias power supply VGGw; inductance L ggw The other end of the first RC stabilizing circuit is connected with a connecting node of a second T-shaped LC network circuit and a second RC stabilizing circuit in the +45 DEG phase-shifting input matching network. In the second power supply bias network, the amplifying and output power supply bias circuit comprises resistors R which are sequentially connected in series gb4w 、R gb5w 、R gb6w Inductance L ddw The method comprises the steps of carrying out a first treatment on the surface of the Resistor R gb4w The other end of the first electrode is grounded; resistor R gb4w And R is R gb5w Through resistor R gb2w The second channel three-stack power amplification network is connected with the grid electrode of each middle layer transistor in the second channel three-stack power amplification network respectively; resistor R gb5w And R is R gb6w Through resistor R gb3w The second channel three-stack power amplification network is connected with the grid electrode of each top layer transistor in the second channel three-stack power amplification network respectively; resistor R gb6w And inductance L ddw The connection nodes of (a) are also respectively connected with a grounding capacitor C ddw And a second high voltage bias power supply VDDw; inductance L ddw The other end of the phase shift output matching network is phase-shifted by-45 degrees, and a fourth T-shaped LC network circuit and an inductor L are arranged in the phase shift output matching network 8 Is connected to the connection node of (c).
The beneficial effects of the above-mentioned further scheme are: the two symmetrically arranged power supply bias networks are used for realizing the bypass function of feeding and stray signals to the grid electrode and the drain electrode of the transistor in the double-path balanced three-stack power amplification network.
Drawings
Fig. 1 is a schematic block diagram of a high-efficiency power amplifier with strong mismatch resistance based on transistor stacking technology according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a high-efficiency power amplifier with strong mismatch resistance based on transistor stacking technology according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely illustrative of the principles and spirit of the invention and are not intended to limit the scope of the invention.
The embodiment of the invention provides a high-efficiency power amplifier with strong mismatch resistance based on a transistor stacking technology, which is shown in figure 1 and comprises a-45 DEG phase-shifting input matching network, a +45 DEG phase-shifting input matching network, a double-path balanced three-stacked power amplifying network, a +45 DEG phase-shifting output matching network, a-45 DEG phase-shifting output matching network, a first power supply bias network and a second power supply bias network. The input end of the-45 DEG phase-shifting input matching network is connected with the input end of the +45 DEG phase-shifting input matching network to serve as the input end of the whole power amplifier; the output end of the +45 DEG phase-shifting output matching network is connected with the output end of the-45 DEG phase-shifting output matching network to serve as the output end of the whole power amplifier. The input end of the power amplifier is also connected with a blocking capacitor C 1 The output end of the power amplifier is also connected with a blocking capacitor C 9 . The first input end of the two-way balance type three-stack power amplification network is connected with the output end of the-45 DEG phase-shifting input matching network, the second input end of the two-way balance type three-stack power amplification network is connected with the output end of the +45 DEG phase-shifting input matching network, the first output end of the two-way balance type three-stack power amplification network is connected with the input end of the +45 DEG phase-shifting output matching network, and the second output end of the two-way balance type three-stack power amplification network is connected with the input end of the-45 DEG phase-shifting output matching network. The first power supply bias network is respectively connected with a-45 DEG phase-shifting input matching network, a double-path balanced type three-stack power amplification network and a +45 DEG phase-shifting output matching network; the second power supply bias network is respectively connected with the +45 DEG phase-shifting input matching network, the two-way balance type three-stack power amplification network and the-45 DEG phase-shifting output matching network.
As shown in fig. 2, the-45 ° phase-shifted input matching network includes a first T-type LC network circuit; one end of the first T-shaped LC network circuit is used as an input end of the-45 DEG phase-shifting input matching network, and the other end of the first T-shaped LC network circuit is connected in series with the first RC stabilizing circuit and then used as an output end of the-45 DEG phase-shifting input matching network. The +45° phase shift input matching network includes a second T-LC network circuit; one end of the second T-shaped LC network circuit is used as an input end of the +45 DEG phase-shifting input matching network, and the other end of the second T-shaped LC network circuit is connected in series with the second RC stabilizing circuit and then used as an output end of the +45 DEG phase-shifting input matching network.
Wherein the first T-type LC network circuit comprises a series inductance L 1 And L is equal to 2 And is connected in parallel with L 1 And L is equal to 2 Ground capacitance C on connection node 2 The method comprises the steps of carrying out a first treatment on the surface of the The second T-type LC network circuit comprises a capacitor C connected in series 3 And C 4 And is connected in parallel with C 3 And C 4 Grounding inductance L on connection node 3 . The first RC stabilizing circuit and the second RC stabilizing circuit have the same structure; the first RC stabilizing circuit comprises a resistor R connected in parallel gsbu And capacitor C gsbu The method comprises the steps of carrying out a first treatment on the surface of the The second RC stabilizing circuit comprises a resistor R connected in parallel gsbw And capacitor C gsbw 。
The +45° phase-shift output matching network comprises a third T-type LC network circuit; one end of the third T-shaped LC network circuit is used as the output end of the +45 DEG phase-shifting output matching network, and the other end is connected with an inductor L in series 4 Then the phase shift output is used as an input end of a +45° phase shift output matching network; third T-type LC network circuit and L 4 A grounding capacitor C is also connected to the connection node of (2) 5 . The-45 DEG phase-shifting output matching network comprises a fourth T-type LC network circuit; one end of the fourth T-shaped LC network circuit is used as an output end of the-45 DEG phase-shifting output matching network, and the other end is connected with an inductor L in series 8 Then the phase shift output is used as the input end of a-45 DEG phase shift output matching network; fourth T-type LC network circuit and L 8 A grounding capacitor C is also connected to the connection node of (2) 10 。
Wherein the third T-type LC network circuit comprises a capacitor C connected in series 6 And C 7 And is connected in parallel with C 6 And C 7 Grounding inductance L on connection node 5 The method comprises the steps of carrying out a first treatment on the surface of the The fourth T-type LC network circuit comprises an inductor L connected in series 6 And L is equal to 7 And is connected in parallel with L 6 And L is equal to 7 Ground capacitance C on connection node 8 。
The double-path balanced type three-stack power amplification network comprises a first path of three-stack power amplification network and a second path of three-stack power amplification network, the first path of three-stack power amplification network and the second path of three-stack power amplification network have the same structure, and each path of three-stack power amplification network comprises one or more paths of parallel stack structures, and each path of stack structure comprises a group of top layer transistors, middle layer transistors and bottom layer transistors which are formed by sequentially stacking according to source electrode-drain electrode connection. The top layer transistor, the middle layer transistor and the bottom layer transistor are the same in size. In the embodiment of the present invention, as shown in fig. 2, the first path of three-stacked power amplification network and the second path of three-stacked power amplification network both adopt a path of stacked structure.
In the first path of three-stack power amplification network, the drain electrode of the top layer transistor M3u is used as a first output end of the two-path balanced three-stack power amplification network; the grid electrode of the top-layer transistor M3M is respectively connected with a first power supply bias network and is stabilized by a grid electrode stabilizing resistor R g3u And a gate compensation capacitor C with one end grounded g3u And the compensation circuit is formed by series connection. The grid electrode of the middle layer transistor M2u is respectively connected with a first power supply bias network and is stabilized by a grid electrode stabilizing resistor R g2u And a gate compensation capacitor C with one end grounded g2u And the compensation circuit is formed by series connection. The source electrode of the bottom layer transistor M1u is grounded, and the grid electrode is used as a first input end of the two-way balance type three-stack power amplification network.
In the second path three-stack power amplification network, the drain electrode of the top layer transistor M3w is used as a second output end of the two-path balanced three-stack power amplification network; the grid electrode of the top-layer transistor M3w is respectively connected with a second power supply bias network and is stabilized by a grid electrode stabilizing resistor R g3w And a gate compensation capacitor C with one end grounded g3w And the compensation circuit is formed by series connection. The grid electrode of the middle layer transistor M2w is respectively connected with a second power supply bias network and is stabilized by a grid electrode stabilizing resistor R g2w And a gate compensation capacitor C with one end grounded g2w And the compensation circuit is formed by series connection. The source electrode of the bottom transistor M1w is grounded, and the grid electrode is used as the second input end of the two-way balance type three-stack power amplification network.
Because the output impedance of the three-stack power amplification network is higher than that of a traditional common source amplifier, the two-way balance type three-stackThe power amplifying network can also respectively adopt 2 n The double parallel stacked amplifier structure can still ensure relatively high output load impedance.
When the multi-path parallel stacking structure is adopted, in the first path of three-stacking power amplifying network, the drain electrode of each top layer transistor is connected to serve as a first output end of the two-path balanced three-stacking power amplifying network, and the grid electrode of each bottom layer transistor is connected to serve as a first input end of the two-path balanced three-stacking power amplifying network. In the second path three-stack power amplification network, the drain electrode of each top layer transistor is connected as a second output end of the two-path balanced three-stack power amplification network, and the grid electrode of each bottom layer transistor is connected as a second input end of the two-path balanced three-stack power amplification network. The circuit connection mode of each other path of stacking structure is the same as that of one path of stacking structure.
The first power supply bias network and the second power supply bias network have the same structure and both comprise an input power supply bias circuit and an amplifying and output power supply bias circuit.
In the first power supply bias network, the input power supply bias circuit comprises a resistor R connected in series gb1u And inductance L ggu Resistance R gb1u And inductance L ggu A grounding capacitor C is also connected to the connection node of (2) ggu The method comprises the steps of carrying out a first treatment on the surface of the Resistor R gb1u The other end of the first voltage bias power supply VGGu is connected with the other end of the first voltage bias power supply VGGu; inductance L ggu The other end of the first RC stabilizing circuit is connected with a connecting node of a first T-shaped LC network circuit and a first RC stabilizing circuit in a-45 DEG phase-shifting input matching network. In the first power supply bias network, the amplifying and output power supply bias circuit comprises resistors R which are sequentially connected in series gb4u 、R gb5u 、R gb6u Inductance L ddu The method comprises the steps of carrying out a first treatment on the surface of the Resistor R gb4u The other end of the first electrode is grounded; resistor R gb4u And R is R gb5u Through resistor R gb2u The first path of the third stacked power amplification network is connected with the grid electrode of each middle layer transistor in the first path of the third stacked power amplification network respectively; resistor R gb5u And R is R gb6u Through resistor R gb3u The first channel of the third stacked power amplification network is connected with the grid electrode of each top layer transistor in the first channel of the third stacked power amplification network respectively; resistor R gb6u And inductance L ddu The connection nodes of (a) are also respectively connected with a grounding capacitor C ddu And a first high voltage bias power supply VDDu; inductance L ddu The other end of the (C) and +45° phase-shifting output matching network is provided with a third T-shaped LC network circuit and an inductor L 4 Is connected to the connection node of (c).
In the second power supply bias network, the input power supply bias circuit comprises a resistor R connected in series gb1w And inductance L ggw Resistance R gb1w And inductance L ggw A grounding capacitor C is also connected to the connection node of (2) ggw The method comprises the steps of carrying out a first treatment on the surface of the Resistor R gb1w The other end of the first low-voltage bias power supply VGGw is connected with a second low-voltage bias power supply VGGw; inductance L ggw The other end of the first RC stabilizing circuit is connected with a connecting node of a second T-shaped LC network circuit and a second RC stabilizing circuit in the +45 DEG phase-shifting input matching network. In the second power supply bias network, the amplifying and output power supply bias circuit comprises resistors R which are sequentially connected in series gb4w 、R gb5w 、R gb6w Inductance L ddw The method comprises the steps of carrying out a first treatment on the surface of the Resistor R gb4w The other end of the first electrode is grounded; resistor R gb4w And R is R gb5w Through resistor R gb2w The second channel three-stack power amplification network is connected with the grid electrode of each middle layer transistor in the second channel three-stack power amplification network respectively; resistor R gb5w And R is R gb6w Through resistor R gb3w The second channel three-stack power amplification network is connected with the grid electrode of each top layer transistor in the second channel three-stack power amplification network respectively; resistor R gb6w And inductance L ddw The connection nodes of (a) are also respectively connected with a grounding capacitor C ddw And a second high voltage bias power supply VDDw; inductance L ddw The other end of the phase shift output matching network is phase-shifted by-45 degrees, and a fourth T-shaped LC network circuit and an inductor L are arranged in the phase shift output matching network 8 Is connected to the connection node of (c).
The specific working principle and process of the present invention are described below with reference to fig. 2:
the radio frequency input signal enters the power amplifier through the input end IN, and after passing through the input DC blocking coupling capacitor C1, the radio frequency input signal is equally power-distributed into a first signal and a second signal at the point INc. The first signal enters a first path three-stack power amplification network in the two-path balanced three-stack power amplification network after being subjected to-45 DEG phase shift control and input impedance matching by a-45 DEG phase shift input matching network. The first path three-stack power amplification network adopts one or more paths of transistor stack structures connected in parallel to amplify the power of the first signal, and finally enters a +45 DEG phase-shifting output matching network. The first signal reaches the OUTc point after being subjected to +45 DEG phase-shifting control and output impedance matching by a +45 DEG phase-shifting output matching network.
Similarly, the second signal is subjected to +45° phase shift control by +45° phase shift input matching network and then enters a second path three-stack power amplification network in the two-path balanced three-stack power amplification network after input impedance matching. The second three-way stacked power amplification network adopts one or more transistor stacking structures connected in parallel to amplify the power of the second signal, and finally enters a-45 DEG phase-shifting output matching network. The second signal reaches the OUTc point after being subjected to-45 DEG phase-shifting control and output impedance matching by a-45 DEG phase-shifting output matching network.
Finally, after the first signal and the second signal are synthesized at the OUTc point with equal power, the first signal and the second signal enter the output end OUT through the DC-blocking coupling capacitor C9.
The two symmetrically arranged power supply bias networks are used for realizing the bypass function of feeding and stray signals to the grid electrode and the drain electrode of the transistor in the double-path balanced three-stack power amplification network.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (3)
1. The high-efficiency power amplifier is characterized by comprising a-45 DEG phase-shifting input matching network, a +45 DEG phase-shifting input matching network, a two-way balance type three-stacking power amplifying network, a +45 DEG phase-shifting output matching network, a-45 DEG phase-shifting output matching network, a first power supply bias network and a second power supply bias network;
the input end of the-45 DEG phase-shifting input matching network is connected with the input end of the +45 DEG phase-shifting input matching network and used as the input end of the whole power amplifier; the output end of the +45° phase-shifting output matching network is connected with the output end of the-45 ° phase-shifting output matching network to serve as the output end of the whole power amplifier;
the first input end of the two-way balance type three-stack power amplification network is connected with the output end of the-45 DEG phase-shifting input matching network, the second input end of the two-way balance type three-stack power amplification network is connected with the output end of the +45 DEG phase-shifting input matching network, the first output end of the two-way balance type three-stack power amplification network is connected with the input end of the +45 DEG phase-shifting output matching network, and the second output end of the two-way balance type three-stack power amplification network is connected with the input end of the-45 DEG phase-shifting output matching network;
the first power supply bias network is respectively connected with a-45 DEG phase-shifting input matching network, a double-path balanced type three-stack power amplification network and a +45 DEG phase-shifting output matching network; the second power supply bias network is respectively connected with a +45 DEG phase-shifting input matching network, a double-path balanced type three-stack power amplification network and a-45 DEG phase-shifting output matching network;
the-45 DEG phase-shifting input matching network comprises a first T-shaped LC network circuit; one end of the first T-shaped LC network circuit is used as an input end of a-45 DEG phase-shifting input matching network, and the other end of the first T-shaped LC network circuit is connected in series with a first RC stabilizing circuit and then used as an output end of the-45 DEG phase-shifting input matching network;
the +45° phase-shifting input matching network comprises a second T-shaped LC network circuit; one end of the second T-shaped LC network circuit is used as an input end of the +45 DEG phase-shifting input matching network, and the other end of the second T-shaped LC network circuit is connected in series with a second RC stabilizing circuit and then used as an output end of the +45 DEG phase-shifting input matching network;
the first T-shaped LC network circuit comprises an inductance L connected in series 1 And L is equal to 2 And is connected in parallel with L 1 And L is equal to 2 Ground capacitance C on connection node 2 The method comprises the steps of carrying out a first treatment on the surface of the The second T-type LC network circuit comprises a capacitor C connected in series 3 And C 4 And is connected in parallel with C 3 And C 4 Grounding inductance L on connection node 3 ；
The first RC stabilizing circuit and the second RC stabilizing circuit have the same structure; the saidThe first RC stabilizing circuit comprises a resistor R connected in parallel gsbu And capacitor C gsbu The method comprises the steps of carrying out a first treatment on the surface of the The second RC stabilizing circuit comprises a resistor R connected in parallel gsbw And capacitor C gsbw ；
The +45° phase-shifting output matching network comprises a third T-shaped LC network circuit; one end of the third T-shaped LC network circuit is used as an output end of the +45 DEG phase-shifting output matching network, and the other end is connected with an inductor L in series 4 Then the phase shift output is used as an input end of a +45° phase shift output matching network; the third T-shaped LC network circuit and L 4 A grounding capacitor C is also connected to the connection node of (2) 5 ；
The-45-degree phase-shifting output matching network comprises a fourth T-shaped LC network circuit; one end of the fourth T-shaped LC network circuit is used as an output end of the-45 DEG phase-shifting output matching network, and the other end is connected with an inductor L in series 8 Then the phase shift output is used as the input end of a-45 DEG phase shift output matching network; the fourth T-shaped LC network circuit and L 8 A grounding capacitor C is also connected to the connection node of (2) 10 ；
The third T-type LC network circuit comprises a capacitor C connected in series 6 And C 7 And is connected in parallel with C 6 And C 7 Grounding inductance L on connection node 5 The method comprises the steps of carrying out a first treatment on the surface of the The fourth T-type LC network circuit comprises an inductance L connected in series 6 And L is equal to 7 And is connected in parallel with L 6 And L is equal to 7 Ground capacitance C on connection node 8 ；
The double-path balanced type three-stack power amplification network comprises a first path of three-stack power amplification network and a second path of three-stack power amplification network, the first path of three-stack power amplification network and the second path of three-stack power amplification network have the same structure and comprise one or more paths of parallel stack structures, and each path of stack structure comprises a group of top layer transistors, middle layer transistors and bottom layer transistors which are formed by sequentially stacking according to source electrode-drain electrode connection; the top layer transistor, the middle layer transistor and the bottom layer transistor have the same size;
in the first path of three-stack power amplification network, the drain electrode of each top layer transistor is connected to serve as a first output end of the two-path balanced three-stack power amplification network; the grid electrode of each top layer transistor is respectively connected with a first power supply bias network and one path of compensation circuit; the grid electrode of each intermediate layer transistor is respectively connected with a first power supply bias network and one path of compensation circuit; the source electrode of each bottom layer transistor is grounded; the grid electrode of each bottom layer transistor is connected to serve as a first input end of the two-way balance type three-stack power amplification network;
in the second three-stack power amplification network, the drain electrode of each top layer transistor is connected to serve as a second output end of the two-way balance three-stack power amplification network; the grid electrode of each top layer transistor is respectively connected with a second power supply bias network and one path of compensation circuit; the grid electrode of each intermediate layer transistor is respectively connected with a second power supply bias network and one path of compensation circuit; the source electrode of each bottom layer transistor is grounded; the grid electrode of each bottom layer transistor is connected to serve as a second input end of the two-way balance type three-stack power amplification network;
the compensation circuit comprises a grid stabilizing resistor and a grid compensation capacitor which are connected in series, and the other end of the grid compensation capacitor is grounded.
2. The high-efficiency power amplifier of claim 1, wherein the first supply bias network and the second supply bias network are identical in structure and each comprise an input supply bias circuit and an amplifying and output supply bias circuit;
in the first power supply bias network, the input power supply bias circuit comprises a resistor R connected in series gb1u And inductance L ggu The resistance R gb1u And inductance L ggu A grounding capacitor C is also connected to the connection node of (2) ggu The method comprises the steps of carrying out a first treatment on the surface of the The resistor R gb1u The other end of the first voltage bias power supply VGGu is connected with the other end of the first voltage bias power supply VGGu; the inductance L ggu The other end of the first RC stabilizing circuit is connected with a connecting node of a first T-shaped LC network circuit and a first RC stabilizing circuit in the-45 DEG phase-shifting input matching network;
in the second power supply bias network, the input power supply bias circuit comprises a resistor R connected in series gb1w And inductance L ggw The resistance R gb1w And inductance L ggw Is also connected with a jointGround capacitance C ggw The method comprises the steps of carrying out a first treatment on the surface of the The resistor R gb1w The other end of the first low-voltage bias power supply VGGw is connected with a second low-voltage bias power supply VGGw; the inductance L ggw The other end of the first RC stabilizing circuit is connected with a connecting node of a second T-shaped LC network circuit and a second RC stabilizing circuit in the +45 DEG phase-shifting input matching network;
in the first power supply bias network, the amplifying and output power supply bias circuit comprises resistors R which are sequentially connected in series gb4u 、R gb5u 、R gb6u Inductance L ddu The method comprises the steps of carrying out a first treatment on the surface of the The resistor R gb4u The other end of the first electrode is grounded; the resistor R gb4u And R is R gb5u Through resistor R gb2u The first path of the third stacked power amplification network is connected with the grid electrode of each middle layer transistor in the first path of the third stacked power amplification network respectively; the resistor R gb5u And R is R gb6u Through resistor R gb3u The first channel of the third-stack power amplification network is connected with the grid electrode of each top layer transistor in the first channel of the third-stack power amplification network respectively; the resistor R gb6u And inductance L ddu The connection nodes of (a) are also respectively connected with a grounding capacitor C ddu And a first high voltage bias power supply VDDu; the inductance L ddu The other end of the phase shift output matching network is shifted with +45° and a third T-shaped LC network circuit and an inductor L are arranged 4 Is connected with the connecting node of the connecting node;
in the second power supply bias network, the amplifying and output power supply bias circuit comprises resistors R which are sequentially connected in series gb4w 、R gb5w 、R gb6w Inductance L ddw The method comprises the steps of carrying out a first treatment on the surface of the The resistor R gb4w The other end of the first electrode is grounded; the resistor R gb4w And R is R gb5w Through resistor R gb2w The second three-stack power amplification network is connected with the grid electrode of each middle layer transistor in the second three-stack power amplification network respectively; the resistor R gb5w And R is R gb6w Through resistor R gb3w The second-path three-stack power amplification network is connected with the grid electrode of each top-layer transistor in the second-path three-stack power amplification network respectively; the resistor R gb6w And inductance L ddw The connection nodes of (a) are also respectively connected with a grounding capacitor C ddw And a second high voltage bias power supply VDDw; the inductance L ddw Is matched with the other end of the-45 DEG phase-shifting output matching networkfour-T type LC network circuit and inductor L 8 Is connected to the connection node of (c).
3. The high-efficiency power amplifier with strong mismatch resistance according to any one of claims 1-2, wherein the input end of the power amplifier is further connected with a blocking capacitor C 1 The output end of the power amplifier is also connected with a blocking capacitor C 9 。
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| CN108736847B (en) * | 2018-07-24 | 2023-09-01 | 成都嘉纳海威科技有限责任公司 | High-efficiency inverse D-type stacked power amplifier based on accurate resonant circuit control |
| CN108768323B (en) * | 2018-08-14 | 2023-09-01 | 成都嘉纳海威科技有限责任公司 | High-power high-efficiency high-gain reverse F-class stacked power amplifier |
| CN110212874B (en) * | 2019-04-28 | 2023-01-20 | 北京无线电测量研究所 | Millimeter wave linear power amplifier chip |
| CN111682851B (en) * | 2020-08-13 | 2020-12-04 | 成都嘉纳海威科技有限责任公司 | Anti-mismatch broadband low-noise amplifier for 5G communication |
| CN114362685B (en) * | 2021-12-14 | 2022-09-20 | 成都嘉纳海威科技有限责任公司 | Power amplifier based on high Q value differential coupling technology |
| CN114172465B (en) * | 2022-02-09 | 2022-05-13 | 成都嘉纳海威科技有限责任公司 | Ultra-wideband active amplification phase shifter |
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