CN207475494U - A kind of strong anti-mismatch high efficiency power amplifier based on transistor stack technology - Google Patents
A kind of strong anti-mismatch high efficiency power amplifier based on transistor stack technology Download PDFInfo
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Abstract
The utility model discloses a kind of strong anti-mismatch high efficiency power amplifiers based on transistor stack technology, and power amplification network ,+45 ° of phase shift output matching networks, 45 ° of phase shift output matching networks, the first power supply biasing networks and the second power supply biasing networks are stacked including 45 ° of phase shift input matching networks ,+45 ° of phase shift input matching networks, two-way balanced type three.The utility model amplifies the enlarging function of real-time performance balanced type amplifier using three stacked transistors, improve the power gain and power capacity of balanced type power amplifier, ± 45 ° of phase shifting controls of two-way balanced signal are realized using the T-shaped filtering type phase-shift circuit of three-level and output and input impedance matching simultaneously, ensure filter with low insertion loss and it is efficient under the premise of greatly improve the anti-mismatch properties of amplifier, so as to improve the Stability and dependability of circuit.The strong anti-mismatch high efficiency power amplifier chip circuit that the utility model is realized, output power is high, power gain is high, area is small.
Description
Technical field
The utility model belongs to field-effect transistor microwave and millimeter wave power amplifier and technical field of integrated circuits, specifically
It is related to a kind of design of the strong anti-mismatch high efficiency power amplifier based on transistor stack technology.
Background technology
As the fast development in the commercial communications such as 3G, 4G-LTE market and 5G are laid out the early period to communicate, microwave and millimeter wave
Front-end transmitter also develops to microwave and millimeter wave frequency range high-performance, highly integrated, efficient direction；Further, since MIMO technology
Extensive use, system proposes acid test, therefore the need that market is urgent to the anti-mismatch properties of end power amplifier
Ask the strong anti-mismatch for microwave and millimeter wave frequency range, high efficiency power amplifier chip.
However, in the design of microwave and millimeter wave power amplifier chip, some design challenges are always existed, are embodied
For：
(1) strong anti-mismatch properties are mutually restricted with high efficiency index in conventional balanced type amplifier：Due to microwave and millimeter wave
The output terminal of power amplifier in front-end transmitter needs to connect the poor antenna of a stationary wave characteristic, and the antenna is for microwave
The anti-mismatch properties of millimeter-wave power amplifiers propose stern challenge；Existing putting down based on the 90 ° of phase shifts of realization of Lange structure
Weighing apparatus type power amplifier is often being output and input in the larger band of matching network introducing while anti-mismatch properties are enhanced
Insertion Loss, so as to reduce the efficiency of power amplifier.Therefore, strong anti-mismatch properties and high efficiency index in conventional balanced type amplifier
Mutually restrict.
(2) microwave and millimeter wave frequency range conventional balanced type amplifier high power, high-gain index Design difficulty are larger：Due to not
Carry out driving for 5G markets, there is an urgent need to high-gain, high power, high efficiency, strong anti-mismatch power for microwave and millimeter wave front end transmitter
Amplifier, but the application circuit of existing millimeter wave frequency band must use grid to grow smaller semiconductor technology transistor, by
The influence of its low breakdown voltage, the voltage swing of power amplifier will be limited by larger, therefore also limit power crystalline substance
The power capacity of body pipe.
The amplifier of most typical strong anti-mismatch properties is the balanced power amplifiers for using 90 ° of phase shift Lange structures, but
It is that, in microwave and millimeter wave frequency range, traditional Lange balance amplifier still has some design deficiencies, is mainly reflected in：
(1) strong anti-mismatch properties and high efficiency index Design difficulty are larger.
In order to improve the anti-mismatch properties of circuit, designer generally requires to realize that two-way balanced structure is believed using Lange structure
Number 90 ° of phase shift, also to reduce the band internal loss of introducing as far as possible, at the same ensure two-way balanced signal have it is approximately the same
Band internal loss, in addition it is also necessary to coordinate other mating structures realize transistor input and input port impedance matching, this
Considerably increase the design complexities and difficulty of circuit.Designer generally requires to pass through introducing for each design objective of compromising
Certain to realize 90 ° of phase shift and impedance matching with internal loss, this is greatly lowered the efficiency index of power amplifier.
(2) millimere-wave band high-capacity transistor impedance matching difficulty is larger.
Since amplifier operation is in millimere-wave band, the limited power capacity of single transistor, designer is higher in order to obtain
Power capacity, generally require 2n times of power combining structures, this structure often lead to output network have it is very low best
Load impedance, this low-load impedance again increase the impedance matching difficulty for leading to microwave and millimeter wave section balanced type amplifier.
Utility model content
The purpose of this utility model is to provide a kind of strong anti-mismatch high efficiency power amplifier based on transistor stack technology,
Using three transistor stack technologies and corresponding ± 45 ° of phase shift inputs and output matching networks, microwave and millimeter wave frequency is realized
The indexs such as section high-gain, high efficiency, strong anti-mismatch.
The technical solution of the utility model is：A kind of strong anti-mismatch highly efficient power amplification based on transistor stack technology
Device stacks power amplification net including -45 ° of phase shift input matching networks ,+45 ° of phase shift input matching networks, two-way balanced type three
Network ,+45 ° of phase shift output matching networks, -45 ° of phase shift output matching networks, the first power supply biasing networks and second supply electrical bias
Network.
The input terminal of -45 ° of phase shift input matching networks is connected with the input terminal of+45 ° of phase shift input matching networks as whole
The input terminal of a power amplifier；The output of the output terminal of+45 ° of phase shift output matching networks and -45 ° of phase shift output matching networks
The connected output terminal as entire power amplifier in end.The input terminal of power amplifier is also associated with capacitance C1, power puts
The output terminal of big device is also associated with capacitance C9。
Two-way balanced type three stacks the output of the first input end and -45 ° of phase shift input matching networks of power amplification network
End connection, the second input terminal are connect with the output terminal of+45 ° of phase shift input matching networks, the first output terminal and+45 ° of phase shifts
The input terminal connection of output matching network, second output terminal are connect with the input terminal of -45 ° of phase shift output matching networks.
First power supply biasing networks stack power amplification net with -45 ° of phase shift input matching networks, two-way balanced type three respectively
Network and+45 ° of phase shift output matching network connections；Second power supply biasing networks respectively with+45 ° of phase shift input matching networks, double
Road balanced type three stacks power amplification network and -45 ° of phase shift output matching network connections.
The beneficial effects of the utility model are：The utility model is put using three stacked transistors amplification real-time performance balanced type
The enlarging function of big device, improves the power gain and power capacity of balanced type power amplifier, while utilizes the T-shaped filtering of three-level
Type phase-shift circuit realizes ± 45 ° of phase shifting controls of two-way balanced signal and outputs and inputs impedance matching, is ensureing filter with low insertion loss
With it is efficient under the premise of greatly improve the anti-mismatch properties of amplifier, so as to improve the Stability and dependability of circuit.
Further, -45 ° of phase shift input matching networks include the first T-shaped LC lattice networks；First T-shaped LC lattice networks
Input terminal of the one end as -45 ° of phase shift input matching networks, the other end connects -45 ° of shiftings of conduct after the first RC stabilizing circuits
The output terminal of phase input matching network.+ 45 ° of phase shift input matching networks include the second T-shaped LC lattice networks；Second T-shaped LC nets
Input terminal of the one end of network circuit as+45 ° of phase shift input matching networks, the other end connect the 2nd RC stabilizing circuits after conduct
The output terminal of+45 ° of phase shift input matching networks.
Wherein, the first T-shaped LC lattice networks include the inductance L of series connection1With L2And it is connected in parallel on L1With L2In connecting node
Ground capacity C2；Second T-shaped LC lattice networks include the capacitance C of series connection3With C4And it is connected in parallel on C3With C4In connecting node
Grounded inductor L3.First RC stabilizing circuits and the 2nd RC stabilizing circuit structures are identical；First RC stabilizing circuits include electricity in parallel
Hinder RgsbuWith capacitance Cgsbu；2nd RC stabilizing circuits include resistance R in parallelgsbwWith capacitance Cgsbw。
+ 45 ° of phase shift output matching networks include the T-shaped LC lattice networks of third；One end conduct of the T-shaped LC lattice networks of third
The output terminal of+45 ° of phase shift output matching networks, other end series inductance L4Input as+45 ° of phase shift output matching networks afterwards
End；The T-shaped LC lattice networks of third and L4Connecting node on be also associated with ground capacity C5.- 45 ° of phase shift output matching network packets
Include the 4th T-shaped LC lattice networks；Output terminal of the one end of 4th T-shaped LC lattice networks as -45 ° of phase shift output matching networks,
Other end series inductance L8Input terminal as -45 ° of phase shift output matching networks afterwards；4th T-shaped LC lattice networks and L8Connection
Ground capacity C is also associated on node10。
Wherein, the T-shaped LC lattice networks of third include the capacitance C of series connection6With C7And it is connected in parallel on C6With C7In connecting node
Grounded inductor L5；4th T-shaped LC lattice networks include the inductance L of series connection6With L7And it is connected in parallel on L6With L7In connecting node
Ground capacity C8。
The advantageous effect of above-mentioned further scheme is：The T-shaped filtering type phase shift electricity of two three-levels is respectively adopted in the utility model
Road realizes ± 45 ° of phase shifting controls of two-way balanced signal and outputs and inputs impedance matching respectively, and two paths of signals can be independent
Control, this is greatly lowered design complexities, avoids introducing unnecessary band internal loss, so as to improve power amplifier
Efficiency index.
Further, two-way balanced type three, which stacks power amplification network and includes the first via three, stacks power amplification network and the
Two tunnels three stack power amplification network, and the first via three stacks power amplification network and the second tunnel three stacks power amplification network structure
It is identical, including one or more stacked structure in parallel, one group is included per road stacked structure successively according to source drain phase
Even stack top layer transistor, middle layer transistor and the bottom transistor formed；Top layer transistor, middle layer transistor and
The size of bottom transistor is identical.
The first via three is stacked in power amplification network, and the drain electrode of each top layer transistor is connected as three heap of two-way balanced type
First output terminal of folded power amplification network；The grid of each top layer transistor connects the first power supply biasing networks and all the way respectively
Compensation circuit；The grid of each middle layer transistor connects the first power supply biasing networks and all the way compensation circuit respectively；Each bottom
The source grounding of layer transistor；The grid of each bottom transistor is connected stacks power amplification network as two-way balanced type three
First input end.
Second tunnel three is stacked in power amplification network, and the drain electrode of each top layer transistor is connected as three heap of two-way balanced type
The second output terminal of folded power amplification network；The grid of each top layer transistor connects the second power supply biasing networks and all the way respectively
Compensation circuit；The grid of each middle layer transistor connects the second power supply biasing networks and all the way compensation circuit respectively；Each bottom
The source grounding of layer transistor；The grid of each bottom transistor is connected stacks power amplification network as two-way balanced type three
The second input terminal.
Compensation circuit includes the grid steady resistance of series connection and grid compensating electric capacity, another termination of grid compensating electric capacity
Ground.
The advantageous effect of above-mentioned further scheme is：Core amplifier architecture is stacked using three in the utility model amplifies net
Network, it is only necessary to enlarged structure be stacked using level-one three, it is possible to the power gain of 3~5dB is promoted, so as to enormously simplify circuit
Complexity.Meanwhile because the output impedance of three stacking amplification networks is higher than traditional common-source amplifier, three heap of two-way balanced type
Folded power amplification network can also use 2nMultichannel in parallel stacks amplifier architecture again, can still ensure relatively high output
Load impedance.In addition to this, the three grid compensating electric capacities for stacking amplification network are the smaller capacitances of capacitance, are used to implement grid electricity
The synchronous hunting of pressure, and in order to realize the stability under millimeter wave frequency band, needs steady resistance of connecting, and tradition Cascode
The piled grids compensating electric capacity of transistor is the larger capacitance of capacitance, is used to implement the AC earth of grid, also steady without series connection
Determine resistance.
Further, the first power supply biasing networks and the second power supply biasing networks structure are identical, and it is inclined to include input power supply
Circuits and amplification and output power supply biasing circuit.
In first power supply biasing networks, input power supply biasing circuit includes the resistance R of series connectiongb1uWith inductance Lggu, resistance
Rgb1uWith inductance LgguConnecting node on be also associated with ground capacity Cggu；Resistance Rgb1uThe other end connect the first low pressure biasing
Power supply VGGu；Inductance LgguThe other end stablize with the first T-shaped LC lattice networks in -45 ° of phase shift input matching networks and the first RC
The connecting node connection of circuit.In first power supply biasing networks, amplification and output power supply biasing circuit include the electricity being sequentially connected in series
Hinder Rgb4u、Rgb5u、Rgb6uAnd inductance Lddu；Resistance Rgb4uThe other end ground connection；Resistance Rgb4uWith Rgb5uConnecting node pass through electricity
Hinder Rgb2uThe grid for stacking each middle layer transistor in power amplification network with the first via three respectively is connect；Resistance Rgb5uWith
Rgb6uConnecting node pass through resistance Rgb3uThe grid of each top layer transistor in power amplification network is stacked with the first via three respectively
Connection；Resistance Rgb6uWith inductance LdduConnecting node on ground capacity C is also respectively connecteddduWith the first HVB high voltage bias power supply
VDDu；Inductance LdduThe other end and the T-shaped LC lattice networks of third in+45 ° of phase shift output matching networks and inductance L4Connection section
Point connection.
In second power supply biasing networks, input power supply biasing circuit includes the resistance R of series connectiongb1wWith inductance Lggw, resistance
Rgb1wWith inductance LggwConnecting node on be also associated with ground capacity Cggw；Resistance Rgb1wThe other end connect the second low pressure biasing
Power supply VGGw；Inductance LggwThe other end stablize with the second T-shaped LC lattice networks in+45 ° of phase shift input matching networks and the 2nd RC
The connecting node connection of circuit.In second power supply biasing networks, amplification and output power supply biasing circuit include the electricity being sequentially connected in series
Hinder Rgb4w、Rgb5w、Rgb6wAnd inductance Lddw；Resistance Rgb4wThe other end ground connection；Resistance Rgb4wWith Rgb5wConnecting node pass through electricity
Hinder Rgb2wThe grid for stacking each middle layer transistor in power amplification network with the second tunnel three respectively is connect；Resistance Rgb5wWith
Rgb6wConnecting node pass through resistance Rgb3wThe grid of each top layer transistor in power amplification network is stacked with the second tunnel three respectively
Connection；Resistance Rgb6wWith inductance LddwConnecting node on ground capacity C is also respectively connectedddwWith the second HVB high voltage bias power supply
VDDw；Inductance LddwThe other end and the 4th T-shaped LC lattice networks in -45 ° of phase shift output matching networks and inductance L8Connection section
Point connection.
The advantageous effect of above-mentioned further scheme is：Two symmetrically arranged power supply biasing networks are used to implement and two-way are put down
Weighing apparatus type three stacks transistor gate and drain electrode feed and the bypass functionality of spurious signal in power amplification network.
Description of the drawings
Fig. 1 show a kind of strong anti-efficient work(of mismatch based on transistor stack technology of the utility model embodiment offer
Rate amplifier functional block diagram.
Fig. 2 show a kind of strong anti-efficient work(of mismatch based on transistor stack technology of the utility model embodiment offer
Rate amplifier circuit diagram.
Specific embodiment
It is described in detail the illustrative embodiments of the utility model with reference to the drawings.It should be appreciated that show in attached drawing
The embodiment for going out and describing is only exemplary, it is intended that is illustrated the principle and spirit of the utility model, and is not limited this
The range of utility model.
The utility model embodiment provides a kind of strong anti-mismatch high efficiency power amplifier based on transistor stack technology,
As shown in Figure 1, stack power including -45 ° of phase shift input matching networks ,+45 ° of phase shift input matching networks, two-way balanced type three
Amplify network ,+45 ° of phase shift output matching networks, -45 ° of phase shift output matching networks, the first power supply biasing networks and the second confession
Electrical bias network.The input terminal of -45 ° of phase shift input matching networks is connected conduct with the input terminal of+45 ° of phase shift input matching networks
The input terminal of entire power amplifier；The output terminal of+45 ° of phase shift output matching networks is defeated with -45 ° of phase shift output matching networks
Outlet is connected the output terminal as entire power amplifier.The input terminal of power amplifier is also associated with capacitance C1, power
The output terminal of amplifier is also associated with capacitance C9.Two-way balanced type three stack power amplification network first input end with-
The output terminal connection of 45 ° of phase shift input matching networks, the output terminal of the second input terminal and+45 ° of phase shift input matching networks connect
It connects, the first output terminal is connect with the input terminal of+45 ° of phase shift output matching networks, and second output terminal is exported with -45 ° of phase shifts
The input terminal connection of matching network.First power supply biasing networks respectively with -45 ° of phase shift input matching networks, two-way balanced type three
Stack power amplification network and+45 ° of phase shift output matching network connections；Second power supply biasing networks are defeated with+45 ° of phase shifts respectively
Enter matching network, two-way balanced type three stacks power amplification network and -45 ° of phase shift output matching network connections.
As shown in Fig. 2, -45 ° of phase shift input matching networks include the first T-shaped LC lattice networks；First T-shaped LC lattice networks
Input terminal of the one end as -45 ° of phase shift input matching networks, the other end connects -45 ° of shiftings of conduct after the first RC stabilizing circuits
The output terminal of phase input matching network.+ 45 ° of phase shift input matching networks include the second T-shaped LC lattice networks；Second T-shaped LC nets
Input terminal of the one end of network circuit as+45 ° of phase shift input matching networks, the other end connect the 2nd RC stabilizing circuits after conduct
The output terminal of+45 ° of phase shift input matching networks.
Wherein, the first T-shaped LC lattice networks include the inductance L of series connection1With L2And it is connected in parallel on L1With L2In connecting node
Ground capacity C2；Second T-shaped LC lattice networks include the capacitance C of series connection3With C4And it is connected in parallel on C3With C4In connecting node
Grounded inductor L3.First RC stabilizing circuits and the 2nd RC stabilizing circuit structures are identical；First RC stabilizing circuits include electricity in parallel
Hinder RgsbuWith capacitance Cgsbu；2nd RC stabilizing circuits include resistance R in parallelgsbwWith capacitance Cgsbw。
+ 45 ° of phase shift output matching networks include the T-shaped LC lattice networks of third；One end conduct of the T-shaped LC lattice networks of third
The output terminal of+45 ° of phase shift output matching networks, other end series inductance L4Input as+45 ° of phase shift output matching networks afterwards
End；The T-shaped LC lattice networks of third and L4Connecting node on be also associated with ground capacity C5.- 45 ° of phase shift output matching network packets
Include the 4th T-shaped LC lattice networks；Output terminal of the one end of 4th T-shaped LC lattice networks as -45 ° of phase shift output matching networks,
Other end series inductance L8Input terminal as -45 ° of phase shift output matching networks afterwards；4th T-shaped LC lattice networks and L8Connection
Ground capacity C is also associated on node10。
Wherein, the T-shaped LC lattice networks of third include the capacitance C of series connection6With C7And it is connected in parallel on C6With C7In connecting node
Grounded inductor L5；4th T-shaped LC lattice networks include the inductance L of series connection6With L7And it is connected in parallel on L6With L7In connecting node
Ground capacity C8。
Two-way balanced type three stacks power amplification network and includes stacking three heap of power amplification network and the second tunnel of the first via three
Folded power amplification network, the first via three stacks power amplification network and the second tunnel three stacking power amplification network structure is identical,
Include one or more stacked structure in parallel, one group is included per road stacked structure and is connected stacking according to source drain successively
Top layer transistor, middle layer transistor and the bottom transistor of composition.Top layer transistor, middle layer transistor and bottom are brilliant
The size of body pipe is identical.In the utility model embodiment, as shown in Fig. 2, the first via three stacks power amplification network and the second tunnel
Three stack power amplification network using stacked structure all the way.
The first via three is stacked in power amplification network, and the drain electrode of top layer transistor M3u stacks work(as two-way balanced type three
Rate amplifies the first output terminal of network；The grid of top layer transistor M3m connects the first power supply biasing networks and respectively by grid
Steady resistance Rg3uWith the grid compensating electric capacity C of one end ground connectiong3uCompensation circuit in series.The grid of middle layer transistor M2u
Pole connects the first power supply biasing networks and respectively by grid steady resistance Rg2uWith the grid compensating electric capacity C of one end ground connectiong2uString
Join the compensation circuit formed.The source electrode ground connection of bottom transistor M1u, grid stack power amplification network as two-way balanced type three
First input end.
Second tunnel three is stacked in power amplification network, and the drain electrode of top layer transistor M3w stacks work(as two-way balanced type three
Rate amplifies the second output terminal of network；The grid of top layer transistor M3w connects the second power supply biasing networks and respectively by grid
Steady resistance Rg3wWith the grid compensating electric capacity C of one end ground connectiong3wCompensation circuit in series.The grid of middle layer transistor M2w
Pole connects the second power supply biasing networks and respectively by grid steady resistance Rg2wWith the grid compensating electric capacity C of one end ground connectiong2wString
Join the compensation circuit formed.The source electrode ground connection of bottom transistor M1w, grid stack power amplification network as two-way balanced type three
The second input terminal.
Because the output impedance of three stacking power amplification networks is higher than traditional common-source amplifier, three heap of two-way balanced type
Folded power amplification network can also be respectively adopted 2nStacking amplifier architecture in parallel again, can still ensure relatively high output
Load impedance.
When using the stacked structure of multi-channel parallel, the first via three is stacked in power amplification network, each top layer transistor
Drain electrode be connected as two-way balanced type three stacking power amplification network the first output terminal, the grid phase of each bottom transistor
Continuous cropping stacks the first input end of power amplification network for two-way balanced type three.Second tunnel three is stacked in power amplification network, often
The drain electrode of a top layer transistor, which is connected, stacks the second output terminal of power amplification network as two-way balanced type three, and each bottom is brilliant
The grid of body pipe, which is connected, stacks the second input terminal of power amplification network as two-way balanced type three.Other every road stacked structures
Circuit connecting mode is identical with stacked structure all the way.
First power supply biasing networks and the second power supply biasing networks structure are identical, include input power supply biasing circuit and put
Big and output power supply biasing circuit.
In first power supply biasing networks, input power supply biasing circuit includes the resistance R of series connectiongb1uWith inductance Lggu, resistance
Rgb1uWith inductance LgguConnecting node on be also associated with ground capacity Cggu；Resistance Rgb1uThe other end connect the first low pressure biasing
Power supply VGGu；Inductance LgguThe other end stablize with the first T-shaped LC lattice networks in -45 ° of phase shift input matching networks and the first RC
The connecting node connection of circuit.In first power supply biasing networks, amplification and output power supply biasing circuit include the electricity being sequentially connected in series
Hinder Rgb4u、Rgb5u、Rgb6uAnd inductance Lddu；Resistance Rgb4uThe other end ground connection；Resistance Rgb4uWith Rgb5uConnecting node pass through electricity
Hinder Rgb2uThe grid for stacking each middle layer transistor in power amplification network with the first via three respectively is connect；Resistance Rgb5uWith
Rgb6uConnecting node pass through resistance Rgb3uThe grid of each top layer transistor in power amplification network is stacked with the first via three respectively
Connection；Resistance Rgb6uWith inductance LdduConnecting node on ground capacity C is also respectively connecteddduWith the first HVB high voltage bias power supply
VDDu；Inductance LdduThe other end and the T-shaped LC lattice networks of third in+45 ° of phase shift output matching networks and inductance L4Connection section
Point connection.
In second power supply biasing networks, input power supply biasing circuit includes the resistance R of series connectiongb1wWith inductance Lggw, resistance
Rgb1wWith inductance LggwConnecting node on be also associated with ground capacity Cggw；Resistance Rgb1wThe other end connect the second low pressure biasing
Power supply VGGw；Inductance LggwThe other end stablize with the second T-shaped LC lattice networks in+45 ° of phase shift input matching networks and the 2nd RC
The connecting node connection of circuit.In second power supply biasing networks, amplification and output power supply biasing circuit include the electricity being sequentially connected in series
Hinder Rgb4w、Rgb5w、Rgb6wAnd inductance Lddw；Resistance Rgb4wThe other end ground connection；Resistance Rgb4wWith Rgb5wConnecting node pass through electricity
Hinder Rgb2wThe grid for stacking each middle layer transistor in power amplification network with the second tunnel three respectively is connect；Resistance Rgb5wWith
Rgb6wConnecting node pass through resistance Rgb3wThe grid of each top layer transistor in power amplification network is stacked with the second tunnel three respectively
Connection；Resistance Rgb6wWith inductance LddwConnecting node on ground capacity C is also respectively connectedddwWith the second HVB high voltage bias power supply
VDDw；Inductance LddwThe other end and the 4th T-shaped LC lattice networks in -45 ° of phase shift output matching networks and inductance L8Connection section
Point connection.
The concrete operating principle and process of the utility model are introduced with reference to Fig. 2：
Radio-frequency input signals is by input terminal IN ingoing power amplifiers, after inputting blocking coupled capacitor C1, in INc
Point constant power is assigned as the first signal and the second signal two paths of signals.The progress of first -45 ° of signal warp phase shift input matching network -
Enter the first via three that two-way balanced type three is stacked in power amplification network after 45 ° of phase shifting controls and input resistant matching to stack
Power amplification network.The first via three stacks power amplification network using one or more transistor stack structure in parallel to first
Signal carries out power amplification, eventually enters into+45 ° of phase shift output matching networks.First+45 ° of signal warp phase shift output matching network
OUTc points are reached after carrying out+45 ° of phase shifting controls and output impedance matching.
Similarly, second signal is after+45 ° of phase shift input matching networks carry out+45 ° of phase shifting controls and input resistant matching
The second tunnel three stacked into two-way balanced type three in power amplification network stacks power amplification network.Second tunnel three stacks power
Amplify network and power amplification is carried out to second signal using one or more transistor stack structure in parallel, eventually enter into -45 °
Phase shift output matching network.- 45 ° of phase shift output matching networks of second signal warp carry out -45 ° of phase shifting controls and output impedance
OUTc points are reached after matching.
Finally, the first signal and the second signal are entered defeated after the synthesis of OUTc points constant power by blocking coupled capacitor C9
Outlet OUT.
Two symmetrically arranged power supply biasing networks are used to implement and crystalline substance in power amplification network are stacked to two-way balanced type three
Body tube grid and drain electrode feed and the bypass functionality of spurious signal.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this reality
With novel principle, it should be understood that the scope of protection of the utility model is not limited to such specific embodiments and embodiments.
Those of ordinary skill in the art can these technical inspirations according to disclosed in the utility model make and various do not depart from this practicality
Novel substantive other various specific deformations and combination, these deformations and combination are still within the protection scope of the present utility model.
Claims (9)
1. a kind of strong anti-mismatch high efficiency power amplifier based on transistor stack technology, which is characterized in that including -45 ° of phase shifts
Input matching network ,+45 ° of phase shift input matching networks, two-way balanced type three stack power amplification network ,+45 ° of phase shift outputs
Distribution network, -45 ° of phase shift output matching networks, the first power supply biasing networks and the second power supply biasing networks；
The input terminal of -45 ° of phase shifts input matching network is connected with the input terminal of+45 ° of phase shift input matching networks as whole
The input terminal of a power amplifier；The output terminal of+45 ° of phase shifts output matching network exports pair net with -45 ° of phase shifts
The output terminal of network is connected the output terminal as the entire power amplifier；
The two-way balanced type three stacks the output of the first input end and -45 ° of phase shift input matching networks of power amplification network
End connection, the second input terminal are connect with the output terminal of+45 ° of phase shift input matching networks, the first output terminal and+45 ° of phase shifts
The input terminal connection of output matching network, second output terminal are connect with the input terminal of -45 ° of phase shift output matching networks；
The first power supply biasing networks stack power amplification net with -45 ° of phase shift input matching networks, two-way balanced type three respectively
Network and+45 ° of phase shift output matching network connections；The second power supply biasing networks input pair net with+45 ° of phase shifts respectively
Network, two-way balanced type three stack power amplification network and -45 ° of phase shift output matching network connections.
2. strong anti-mismatch high efficiency power amplifier according to claim 1, which is characterized in that -45 ° of phase shifts input
Distribution network includes the first T-shaped LC lattice networks；- 45 ° of phase shift input pair nets of one end conduct of the first T-shaped LC lattice networks
The input terminal of network, the other end are connected output terminal as -45 ° of phase shift input matching networks after the first RC stabilizing circuits；
+ 45 ° of phase shifts input matching network includes the second T-shaped LC lattice networks；One end of the second T-shaped LC lattice networks
As the input terminal of+45 ° of phase shift input matching networks, the other end is connected+45 ° of phase shifts inputs of conduct after the 2nd RC stabilizing circuits
The output terminal of matching network.
3. strong anti-mismatch high efficiency power amplifier according to claim 2, which is characterized in that the first T-shaped LC networks
Circuit includes the inductance L of series connection1With L2And it is connected in parallel on L1With L2Ground capacity C in connecting node2；The second T-shaped LC nets
Network circuit includes the capacitance C of series connection3With C4And it is connected in parallel on C3With C4Grounded inductor L in connecting node3。
4. strong anti-mismatch high efficiency power amplifier according to claim 2, which is characterized in that the first RC stabilizing circuits
It is identical with the 2nd RC stabilizing circuit structures；The first RC stabilizing circuits include resistance R in parallelgsbuWith capacitance Cgsbu；Described
Two RC stabilizing circuits include resistance R in parallelgsbwWith capacitance Cgsbw。
5. strong anti-mismatch high efficiency power amplifier according to claim 2, which is characterized in that+45 ° of phase shifts output
Distribution network includes the T-shaped LC lattice networks of third；+ 45 ° of phase shift output pair nets of one end conduct of the T-shaped LC lattice networks of third
The output terminal of network, other end series inductance L4Input terminal as+45 ° of phase shift output matching networks afterwards；The T-shaped LC nets of third
Network circuit and L4Connecting node on be also associated with ground capacity C5；
- 45 ° of phase shifts output matching network includes the 4th T-shaped LC lattice networks；One end of the 4th T-shaped LC lattice networks
As the output terminal of -45 ° of phase shift output matching networks, other end series inductance L8Afterwards as -45 ° of phase shift output matching networks
Input terminal；The 4th T-shaped LC lattice networks and L8Connecting node on be also associated with ground capacity C10。
6. strong anti-mismatch high efficiency power amplifier according to claim 5, which is characterized in that the T-shaped LC networks of third
Circuit includes the capacitance C of series connection6With C7And it is connected in parallel on C6With C7Grounded inductor L in connecting node5；The 4th T-shaped LC nets
Network circuit includes the inductance L of series connection6With L7And it is connected in parallel on L6With L7Ground capacity C in connecting node8。
7. strong anti-mismatch high efficiency power amplifier according to claim 5, which is characterized in that three heap of two-way balanced type
Folded power amplification network includes that the first via three stacks power amplification network and the second tunnel three stacks power amplification network, and described first
Road three stacks power amplification network and the second tunnel three stacking power amplification network structure is identical, in parallel including one or more
Stacked structure, include per stacked structure described in road one group be connected successively according to source drain stack the top layer transistor formed,
Middle layer transistor and bottom transistor；The size phase of the top layer transistor, middle layer transistor and bottom transistor
Together；
The first via three is stacked in power amplification network, and the drain electrode of each top layer transistor is connected as three heap of two-way balanced type
First output terminal of folded power amplification network；The grid of each top layer transistor connects the first power supply biasing networks and all the way respectively
Compensation circuit；The grid of each middle layer transistor connects the first power supply biasing networks and all the way compensation circuit respectively；Each bottom
The source grounding of layer transistor；The grid of each bottom transistor is connected stacks power amplification network as two-way balanced type three
First input end；
Second tunnel three is stacked in power amplification network, and the drain electrode of each top layer transistor is connected as three heap of two-way balanced type
The second output terminal of folded power amplification network；The grid of each top layer transistor connects the second power supply biasing networks and all the way respectively
Compensation circuit；The grid of each middle layer transistor connects the second power supply biasing networks and all the way compensation circuit respectively；Each bottom
The source grounding of layer transistor；The grid of each bottom transistor is connected stacks power amplification network as two-way balanced type three
The second input terminal；
The compensation circuit includes the grid steady resistance of series connection and grid compensating electric capacity, the other end of the grid compensating electric capacity
Ground connection.
8. strong anti-mismatch high efficiency power amplifier according to claim 7, which is characterized in that described first supplies electrical bias net
Network and the second power supply biasing networks structure are identical, include input power supply biasing circuit and amplification and output power supply biasing circuit；
In the first power supply biasing networks, input power supply biasing circuit includes the resistance R of series connectiongb1uWith inductance Lggu, the electricity
Hinder Rgb1uWith inductance LgguConnecting node on be also associated with ground capacity Cggu；The resistance Rgb1uOther end connection it is first low
Press bias supply VGGu；The inductance LgguThe other end and -45 ° of phase shifts input matching network in the first T-shaped LC networks electricity
Road is connected with the connecting node of the first RC stabilizing circuits；
In the second power supply biasing networks, input power supply biasing circuit includes the resistance R of series connectiongb1wWith inductance Lggw, the electricity
Hinder Rgb1wWith inductance LggwConnecting node on be also associated with ground capacity Cggw；The resistance Rgb1wOther end connection it is second low
Press bias supply VGGw；The inductance LggwThe other end and+45 ° of phase shifts input matching network in the second T-shaped LC networks electricity
Road is connected with the connecting node of the 2nd RC stabilizing circuits；
In the first power supply biasing networks, amplification and output power supply biasing circuit include the resistance R being sequentially connected in seriesgb4u、Rgb5u、
Rgb6uAnd inductance Lddu；The resistance Rgb4uThe other end ground connection；The resistance Rgb4uWith Rgb5uConnecting node pass through resistance
Rgb2uThe grid for stacking each middle layer transistor in power amplification network with the first via three respectively is connect；The resistance
Rgb5uWith Rgb6uConnecting node pass through resistance Rgb3uIt is brilliant that each top layer in power amplification network is stacked with the first via three respectively
The grid connection of body pipe；The resistance Rgb6uWith inductance LdduConnecting node on ground capacity C is also respectively connecteddduWith first
HVB high voltage bias power vd Du；The inductance LdduThe other end and+45 ° of phase shifts output matching network in the T-shaped LC networks of third
Circuit and inductance L4Connecting node connection；
In the second power supply biasing networks, amplification and output power supply biasing circuit include the resistance R being sequentially connected in seriesgb4w、Rgb5w、
Rgb6wAnd inductance Lddw；The resistance Rgb4wThe other end ground connection；The resistance Rgb4wWith Rgb5wConnecting node pass through resistance
Rgb2wThe grid for stacking each middle layer transistor in power amplification network with second tunnel three respectively is connect；The resistance
Rgb5wWith Rgb6wConnecting node pass through resistance Rgb3wIt is brilliant that each top layer in power amplification network is stacked with second tunnel three respectively
The grid connection of body pipe；The resistance Rgb6wWith inductance LddwConnecting node on ground capacity C is also respectively connectedddwWith second
HVB high voltage bias power vd Dw；The inductance LddwThe other end and -45 ° of phase shifts output matching network in the 4th T-shaped LC networks
Circuit and inductance L8Connecting node connection.
9. according to any strong anti-mismatch high efficiency power amplifiers of claim 1-8, which is characterized in that the power amplification
The input terminal of device is also associated with capacitance C1, the output terminal of the power amplifier is also associated with capacitance C9。
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107743021A (en) * | 2017-10-10 | 2018-02-27 | 成都嘉纳海威科技有限责任公司 | A kind of strong anti-mismatch high efficiency power amplifier based on transistor stack technology |
| CN108649911A (en) * | 2018-06-15 | 2018-10-12 | 成都嘉纳海威科技有限责任公司 | A kind of millimeter wave broadband high efficiency transistor stack power amplifier |
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2017
- 2017-10-10 CN CN201721304208.8U patent/CN207475494U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107743021A (en) * | 2017-10-10 | 2018-02-27 | 成都嘉纳海威科技有限责任公司 | A kind of strong anti-mismatch high efficiency power amplifier based on transistor stack technology |
| CN107743021B (en) * | 2017-10-10 | 2024-02-27 | 成都嘉纳海威科技有限责任公司 | High-mismatch-resistance high-efficiency power amplifier based on transistor stacking technology |
| CN108649911A (en) * | 2018-06-15 | 2018-10-12 | 成都嘉纳海威科技有限责任公司 | A kind of millimeter wave broadband high efficiency transistor stack power amplifier |
| CN108649911B (en) * | 2018-06-15 | 2023-10-27 | 成都嘉纳海威科技有限责任公司 | Millimeter wave broadband high-efficiency transistor stacking power amplifier |
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