CN208656727U - A kind of high-power high-efficiency high-gain stacks power amplifier against F class - Google Patents
A kind of high-power high-efficiency high-gain stacks power amplifier against F class Download PDFInfo
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- CN208656727U CN208656727U CN201821310190.7U CN201821310190U CN208656727U CN 208656727 U CN208656727 U CN 208656727U CN 201821310190 U CN201821310190 U CN 201821310190U CN 208656727 U CN208656727 U CN 208656727U
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Abstract
The utility model discloses a kind of high-power high-efficiency high-gains to stack power amplifier against F class, including sequentially connected input resistant matching power distributing network, drain-source offset-type two-way stack amplification network and export inverse F class impedance matching power synthesis network.The utility model uses drain-source offset-type two-way stacked transistors structure, and combines efficient reverse F class output matching and power synthetic technique, so that circuit has high efficiency, high-gain, high-power output ability.
Description
Technical field
The utility model belongs to field effect transistor radio-frequency power amplifier and technical field of integrated circuits, and in particular to one
Kind high-power high-efficiency high-gain stacks the design of power amplifier against F class.
Background technique
With the development of modern military, commercial communication technology, radio-frequency front-end transmitter is also to high efficiency, high-gain, Gao Gong
The direction of rate output is developed.Therefore the urgent demand high efficiency in market, high-gain, high-power power amplifier.However, passing
It unites in the design of high efficiency power amplifier, always exists some design challenges, be mainly reflected in high efficiency index and mutually restrict:
In order to guarantee the efficiency operation of amplifier, transistor will work under the mode of overdriving, and be similar to switch state, but cross and drive
The bandwidth of dynamic switch power amplifier is always the technical bottleneck that circuit is realized.
The circuit structure of common high efficiency power amplifier has very much, most typically tradition AB class, C class, switching mode D
Class, E class, F power-like amplifier etc., still, the broadband character of these high-efficiency amplifiers still have some shortcomings, main body
Present: traditional class ab ammplifier theoretical limit efficiency is 78.5%, relatively low, generally requires to sacrifice output Insertion Loss and efficiency is come
Increase the bandwidth of amplifier；C class A amplifier A limiting efficiency is 100%, but power output capacity is lower, Broadband emission ability and
Efficiency is lower；The needs such as switching mode D class, E class, F power-like amplifier rely on accurate harmonic impedance control or stringent resistance
Anti- matching condition, these controls and condition all greatly limit amplifier operation bandwidth.In addition to this, existing high efficiency field-effect
Tube power amplifier is often based on what single common source transistors were realized, is limited by single transistor, power output capacity
It is all relatively low with power gain ability.
Utility model content
The purpose of this utility model is to propose that a kind of high-power high-efficiency high-gain stacks power amplifier against F class, is utilized
Drain-source offset-type two-way transistor stack technology and efficient reverse F class output matching and power synthetic technique, realize high efficiency, height
Gain, high-power output characteristic.
The technical solution of the utility model are as follows: a kind of high-power high-efficiency high-gain stacks power amplifier against F class, including
Sequentially connected input resistant matching power distributing network, drain-source offset-type two-way stack amplification network and export inverse F class impedance
Mesh power synthesizes network；The input terminal of input resistant matching power distributing network is that entire inverse F class stacks power amplifier
Input terminal, the first output end are connect with the first input end that drain-source offset-type two-way stacks amplification network, second output terminal
The second input terminal for stacking amplification network with drain-source offset-type two-way is connect；Export inverse F class impedance matching power synthesis network
Output end is the output end that entire inverse F class stacks power amplifier, and first input end and drain-source offset-type two-way stack and amplify
First output end of network connects, and the second input terminal and drain-source offset-type two-way stack the second output terminal company for amplifying network
It connects.
The beneficial effects of the utility model are: the utility model uses drain-source offset-type two-way stacked transistors structure, suppression
Grid source leakage phenomenon of the stacked structure under inverse F class operating mode has been made, has exported matching and power in combination with efficient reverse F class
Synthetic technology, so that circuit has high efficiency, high-gain, high-power output ability.
Input resistant matching power distributing network includes capacitance C1, capacitance C1One end be input resistant matching
The input terminal of power distributing network, the other end respectively with microstrip line TL1One end, microstrip line TL2One end and capacitor C2's
One end connection；Microstrip line TL1The other end respectively with microstrip line TL3One end and capacitor C4One end connection, microstrip line TL2
The other end respectively with microstrip line TL4One end and capacitor C5One end connection, capacitor C2The other end, capacitor C4It is another
End and capacitor C5The other end link together and be grounded；Microstrip line TL3The other end respectively with microstrip line TL5One end with
And resistance R1One end connection, resistance R1The other end be input resistant matching power distributing network the first output end, microstrip line
TL5The other end respectively with ground capacity C3And the first low pressure bias supply Vg1Connection；Microstrip line TL4The other end respectively with
Microstrip line TL6One end and resistance R2One end connection, resistance R2The other end be input resistant matching power distributing network
Second output terminal, microstrip line TL6The other end respectively with ground capacity C6And the second low pressure bias supply Vg2Connection.
The beneficial effect of above-mentioned further scheme is: the input resistant matching power distributing network energy that the utility model uses
Enough realize carries out constant power distribution and impedance matching to the signal that radio frequency inputs, while can also stack to drain-source offset-type two-way
The bottom transistor that two-way stacks power amplification circuit in amplification network plays good grid power supply and bias.
It includes that the first via two stacks power amplification circuit and the second tunnel two stacking that drain-source offset-type two-way, which stacks amplification network,
Power amplification circuit, the first via two stacks power amplification circuit and the second tunnel two stacking power amplification circuit structure is identical.First
It includes the top layer transistor M for stacking and constituting that is connected according to source drain that road two, which stacks power amplification circuit,2With bottom transistor M1；
Bottom transistor M1Source electrode ground connection, grid be drain-source offset-type two-way stack amplification network first input end；Bottom is brilliant
Body pipe M1Drain electrode and top layer transistor M2Source electrode between pass through microstrip line TL7Connection；Top layer transistor M2Drain electrode be leakage
Source offset-type two-way stacks the first output end of amplification network, passes through capacitor C between source electrode and drain electrode9Connection, grid point
Not with resistance R4One end and first grid compensation circuit connection；First grid compensation circuit includes that concatenated grid stablizes electricity
Hinder R3With compensation of ground capacitor C8.It includes being connected to stack according to source drain to constitute that second tunnel two, which stacks power amplification circuit,
Top layer transistor M4With bottom transistor M3；Bottom transistor M3Source electrode ground connection, grid be drain-source offset-type two-way heap stack
Second input terminal of big network；Bottom transistor M3Drain electrode and top layer transistor M4Source electrode between pass through microstrip line TL8Even
It connects；Top layer transistor M4Drain electrode be drain-source offset-type two-way stack amplification network second output terminal, source electrode and drain electrode it
Between pass through capacitor C10Connection, grid respectively with resistance R6One end and second grid compensation circuit connection；Second grid is mended
Repaying circuit includes concatenated grid steady resistance R7With compensation of ground capacitor C7.Resistance R4The other end respectively with resistance R6It is another
One end, resistance R8One end and ground resistance R5Connection, resistance R8The other end respectively with resistance R9One end and resistance R10
One end connection, resistance R9The other end and top layer transistor M2Drain electrode connection, resistance R10The other end and top layer transistor M4
Drain electrode connection.
The beneficial effect of above-mentioned further scheme is: the core architecture of the utility model is stacked using drain-source offset-type two-way
Amplify network, high efficiency switch power amplifier hoisting power capacity and power gain can be helped.And the utility model is adopted
Two-way, which stacks amplification network, joined automatic biasing structure, does not need additional piled grids bias voltage, enormously simplifies
The peripheral gates power supply structure of stacked structure.
Exporting inverse F class impedance matching power synthesis network includes capacitance C15, capacitance C15One end be export it is inverse
The output end of F class impedance matching power synthesis network, the other end respectively with microstrip line TL10One end, microstrip line TL11One
End and capacitor C12One end connection；Microstrip line TL10The other end respectively with microstrip line TL9One end and the first resonant network
Circuit connection, microstrip line TL9The other end be the first input end for exporting inverse F class impedance matching power synthesis network, and with electricity
Hold C11One end connection；Microstrip line TL11The other end respectively with microstrip line TL12One end and the second resonant network resistance connect
It connects, microstrip line TL12The other end be the second input terminal for exporting inverse F class impedance matching power synthesis network, and with capacitor C13's
One end connection；Capacitor C11The other end, capacitor C12The other end and capacitor C13The other end link together and be grounded.
The beneficial effect of above-mentioned further scheme is: the output matching network of the utility model is exported using efficient reverse F class
Matching and power combing framework can be realized and stack the amplified two paths of signals progress function of amplification network to drain-source offset-type two-way
Rate synthesis and impedance matching, while can make circuit realize be similar to three ranks against F class working condition output impedance fundamental wave
With harmonic impedance, to realize high power and high efficiency index.
First resonant network resistance includes the first LC resonance circuit, the microstrip line TL being sequentially connected in series13, resistance R11And ground connection
Capacitor C17, the first LC resonance circuit includes inductance L in parallel1With capacitor C14, one end and microstrip line TL13Connection, the other end
With microstrip line TL10Connection；Microstrip line TL13With resistance R11Connecting node also with the first low pressure bias supply Vd1Connection.Second is humorous
The lattice network that shakes includes the second LC resonance circuit, the microstrip line TL being sequentially connected in series14, resistance R12With ground capacity C18, the 2nd LC is humorous
Vibration circuit includes inductance L in parallel2With capacitor C16, one end and microstrip line TL14Connection, the other end and microstrip line TL11Even
It connects；Microstrip line TL14With resistance R12Connecting node also with the second low pressure bias supply Vd2Connection.
The beneficial effect of above-mentioned further scheme is: in the utility model, two resonant network resistances can mend drain-source
It repays type two-way and stacks the amplified two paths of signals of amplification network and realize fundamental frequency radio frequency open circuit, second harmonic open circuit and three times
Harmonic short circuits, to realize the fundamental wave and harmonic impedance for the output impedance for being similar to three ranks against F class working condition.
Detailed description of the invention
Fig. 1 show a kind of high-power high-efficiency high-gain provided by the embodiment of the utility model and puts against F class stacking power
Big device functional block diagram.
Fig. 2 show a kind of high-power high-efficiency high-gain provided by the embodiment of the utility model and puts against F class stacking power
Big device circuit diagram.
Specific embodiment
It is described in detail the illustrative embodiments of the utility model with reference to the drawings.It should be appreciated that showing in attached drawing
It is only exemplary out with the embodiment of description, it is intended that illustrate the principles of the present invention and spirit, and not limit this
The range of utility model.
The utility model embodiment provides a kind of high-power high-efficiency high-gain and stacks power amplifier, such as Fig. 1 against F class
It is shown, including sequentially connected input resistant matching power distributing network, drain-source offset-type two-way stacking amplification network and output
Inverse F class impedance matching power synthesis network；The input terminal of input resistant matching power distributing network is that entire inverse F class stacks function
The input terminal of rate amplifier, the first output end are connect with the first input end that drain-source offset-type two-way stacks amplification network,
Second output terminal is connect with the second input terminal that drain-source offset-type two-way stacks amplification network；Export inverse F class impedance matching power
The output end for synthesizing network is the output end of entire inverse F class stacking power amplifier, and first input end and drain-source offset-type are double
Road stacks the first output end connection of amplification network, and the second input terminal and drain-source offset-type two-way stack the second of amplification network
Output end connection.
As shown in Fig. 2, input resistant matching power distributing network includes capacitance C1, capacitance C1One end be it is defeated
Enter the input terminal of impedance matching power distributing network, the other end respectively with microstrip line TL1One end, microstrip line TL2One end with
And capacitor C2One end connection；Microstrip line TL1The other end respectively with microstrip line TL3One end and capacitor C4One end connection,
Microstrip line TL2The other end respectively with microstrip line TL4One end and capacitor C5One end connection, capacitor C2The other end, capacitor
C4The other end and capacitor C5The other end link together and be grounded；Microstrip line TL3The other end respectively with microstrip line TL5
One end and resistance R1One end connection, resistance R1The other end be input resistant matching power distributing network first output
End, microstrip line TL5The other end respectively with ground capacity C3And the first low pressure bias supply Vg1Connection；Microstrip line TL4It is another
End respectively with microstrip line TL6One end and resistance R2One end connection, resistance R2The other end be input resistant matching power point
The second output terminal of distribution network, microstrip line TL6The other end respectively with ground capacity C6And the second low pressure bias supply Vg2Even
It connects.
It includes that the first via two stacks power amplification circuit and the second tunnel two stacking that drain-source offset-type two-way, which stacks amplification network,
Power amplification circuit, the first via two stacks power amplification circuit and the second tunnel two stacking power amplification circuit structure is identical.
It includes the top layer transistor M for stacking and constituting that is connected according to source drain that the first via two, which stacks power amplification circuit,2With
Bottom transistor M1；Bottom transistor M1Source electrode ground connection, grid is that drain-source offset-type two-way stacks the first defeated of amplification network
Enter end；Bottom transistor M1Drain electrode and top layer transistor M2Source electrode between pass through microstrip line TL7Connection；Top layer transistor M2
Drain electrode be the first output end that drain-source offset-type two-way stacks amplification network, pass through capacitor C between source electrode and drain electrode9Even
Connect, grid respectively with resistance R4One end and first grid compensation circuit connection；First grid compensation circuit includes series connection
Grid steady resistance R3With compensation of ground capacitor C8。
It includes the top layer transistor M for stacking and constituting that is connected according to source drain that second tunnel two, which stacks power amplification circuit,4With
Bottom transistor M3；Bottom transistor M3Source electrode ground connection, grid is that drain-source offset-type two-way stacks the second defeated of amplification network
Enter end；Bottom transistor M3Drain electrode and top layer transistor M4Source electrode between pass through microstrip line TL8Connection；Top layer transistor M4
Drain electrode be second output terminal that drain-source offset-type two-way stacks amplification network, pass through capacitor C between source electrode and drain electrode10Even
Connect, grid respectively with resistance R6One end and second grid compensation circuit connection；Second grid compensation circuit includes series connection
Grid steady resistance R7With compensation of ground capacitor C7.Resistance R4The other end respectively with resistance R6The other end, resistance R8One
End and ground resistance R5Connection, resistance R8The other end respectively with resistance R9One end and resistance R10One end connection, resistance
R9The other end and top layer transistor M2Drain electrode connection, resistance R10The other end and top layer transistor M4Drain electrode connection.
Exporting inverse F class impedance matching power synthesis network includes capacitance C15, capacitance C15One end be export it is inverse
The output end of F class impedance matching power synthesis network, the other end respectively with microstrip line TL10One end, microstrip line TL11One
End and capacitor C12One end connection；Microstrip line TL10The other end respectively with microstrip line TL9One end and the first resonant network
Circuit connection, microstrip line TL9The other end be the first input end for exporting inverse F class impedance matching power synthesis network, and with electricity
Hold C11One end connection；Microstrip line TL11The other end respectively with microstrip line TL12One end and the second resonant network resistance connect
It connects, microstrip line TL12The other end be the second input terminal for exporting inverse F class impedance matching power synthesis network, and with capacitor C13's
One end connection；Capacitor C11The other end, capacitor C12The other end and capacitor C13The other end link together and be grounded.
First resonant network resistance includes the first LC resonance circuit, the microstrip line TL being sequentially connected in series13, resistance R11And ground connection
Capacitor C17, the first LC resonance circuit includes inductance L in parallel1With capacitor C14, one end and microstrip line TL13Connection, the other end
With microstrip line TL10Connection；Microstrip line TL13With resistance R11Connecting node also with the first low pressure bias supply Vd1Connection.
Second resonant network resistance includes the second LC resonance circuit, the microstrip line TL being sequentially connected in series14, resistance R12And ground connection
Capacitor C18, the second LC resonance circuit includes inductance L in parallel2With capacitor C16, one end and microstrip line TL14Connection, the other end
With microstrip line TL11Connection；Microstrip line TL14With resistance R12Connecting node also with the second low pressure bias supply Vd2Connection.
It is introduced below with reference to concrete operating principle and process of the Fig. 2 to the utility model:
Radio frequency inputs fundamental signal and enters input resistant matching power distributing network progress constant power point by input terminal IN
Match and input resistant matching after, formed two paths of signals respectively enter drain-source offset-type two-way stack amplification network amplify, pass through
Drain-source offset-type two-way stacks the amplification amplified two paths of signals of network and enters back into the inverse F class impedance matching power synthesis network of output
Output impedance matching and constant power synthesis are carried out, radio frequency output signal is ultimately formed and reaches output end OUT.
Wherein input resistant matching power distributing network uses capacitor C2、C4And C5And microstrip line TL1And TL2Constitute two
A π shape CLC match circuit is realized and carries out impedance matching to the two paths of signals after power distribution.Simultaneously by capacitor C3/C6And micro-strip
Line TL5/TL6Two minor matters constituted can stack amplification network indsole layer transistor M to drain-source offset-type two-way respectively1/M3
Play good grid power supply and bias.
Drain-source offset-type two-way stacks core architecture of the amplification network as the utility model, after to power distribution
Two paths of signals amplifies, and can help high efficiency switch power amplifier hoisting power capacity and power gain.Drain-source simultaneously
Offset-type two-way stacks in amplification network, by resistance R4~R6And R8~R10Automatic biasing structure is constituted, additional heap is not needed
Folded gate bias voltage, enormously simplifies the peripheral gates power supply structure of stacked structure.
Output matching network can be realized using efficient reverse F class output matching and power combing framework to drain-source offset-type
Two-way stacks the amplified two paths of signals of amplification network and carries out power combing and impedance matching, meanwhile, the first resonant network resistance
The amplified two paths of signals of amplification network can be stacked to drain-source offset-type two-way respectively with the second resonant network resistance and realize base
Wave frequency rate radio frequency open circuit, second harmonic open circuit and triple-frequency harmonics short circuit, are similar to three ranks against F class working condition to realize
The fundamental wave and harmonic impedance of output impedance, and then realize high power and high efficiency index.
In the utility model embodiment, the size of the size of transistor and other DC feedback resistance, compensating electric capacity is comprehensive
It is determined after the indices such as gain, efficiency and the output power of the entire circuit of conjunction consideration, passes through the layout design and conjunction in later period
Required indices can be better achieved in removing the work office, realize high efficiency under the conditions of circuit miniaturization, high-gain,
High-power output ability.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this reality
With novel principle, it should be understood that the scope of the present invention is not limited to such specific embodiments and embodiments.
Those skilled in the art can be made according to the technical disclosures disclosed by the utility model it is various do not depart from it is practical
Novel substantive various other specific variations and combinations, these variations and combinations are still within the protection scope of the present invention.
Claims (5)
1. a kind of high-power high-efficiency high-gain stacks power amplifier against F class, which is characterized in that including sequentially connected input
Impedance matching power distributing network, drain-source offset-type two-way stack amplification network and export inverse F class impedance matching power combing net
Network；
The input terminal of the input resistant matching power distributing network is the input that the entire inverse F class stacks power amplifier
End, the first output end are connect with the first input end that drain-source offset-type two-way stacks amplification network, second output terminal and leakage
Source offset-type two-way stacks the second input terminal connection of amplification network；
The output end for exporting inverse F class impedance matching power synthesis network is that the entire inverse F class stacks power amplifier
Output end, first input end are connect with the first output end that drain-source offset-type two-way stacks amplification network, the second input terminal
The second output terminal for stacking amplification network with drain-source offset-type two-way is connect.
2. inverse F class according to claim 1 stacks power amplifier, which is characterized in that the input resistant matching power
Distributing network includes capacitance C1, the capacitance C1One end be input resistant matching power distributing network input terminal,
Its other end respectively with microstrip line TL1One end, microstrip line TL2One end and capacitor C2One end connection；
The microstrip line TL1The other end respectively with microstrip line TL3One end and capacitor C4One end connection, the microstrip line
TL2The other end respectively with microstrip line TL4One end and capacitor C5One end connection, the capacitor C2The other end, capacitor C4
The other end and capacitor C5The other end link together and be grounded；
The microstrip line TL3The other end respectively with microstrip line TL5One end and resistance R1One end connection, the resistance R1's
The other end is the first output end of input resistant matching power distributing network, the microstrip line TL5The other end respectively with ground connection
Capacitor C3And the first low pressure bias supply Vg1Connection；
The microstrip line TL4The other end respectively with microstrip line TL6One end and resistance R2One end connection, the resistance R2's
The other end is the second output terminal of input resistant matching power distributing network, the microstrip line TL6The other end respectively with ground connection
Capacitor C6And the second low pressure bias supply Vg2Connection.
3. inverse F class according to claim 1 stacks power amplifier, which is characterized in that the drain-source offset-type two-way heap
Stacking big network includes that the first via two stacks power amplification circuit and the second tunnel two stacking power amplification circuit, the first via two
It stacks power amplification circuit and the second tunnel two stacking power amplification circuit structure is identical；
It includes the top layer transistor M for stacking and constituting that is connected according to source drain that the first via two, which stacks power amplification circuit,2With
Bottom transistor M1；The bottom transistor M1Source electrode ground connection, grid is that drain-source offset-type two-way stacks the of amplification network
One input terminal；The bottom transistor M1Drain electrode and top layer transistor M2Source electrode between pass through microstrip line TL7Connection；It is described
Top layer transistor M2Drain electrode be the first output end that drain-source offset-type two-way stacks amplification network, lead between source electrode and drain electrode
Cross capacitor C9Connection, grid respectively with resistance R4One end and first grid compensation circuit connection；The first grid compensation
Circuit includes concatenated grid steady resistance R3With compensation of ground capacitor C8；
It includes the top layer transistor M for stacking and constituting that is connected according to source drain that second tunnel two, which stacks power amplification circuit,4With
Bottom transistor M3；The bottom transistor M3Source electrode ground connection, grid is that drain-source offset-type two-way stacks the of amplification network
Two input terminals；The bottom transistor M3Drain electrode and top layer transistor M4Source electrode between pass through microstrip line TL8Connection；It is described
Top layer transistor M4Drain electrode be second output terminal that drain-source offset-type two-way stacks amplification network, lead between source electrode and drain electrode
Cross capacitor C10Connection, grid respectively with resistance R6One end and second grid compensation circuit connection；The second grid is mended
Repaying circuit includes concatenated grid steady resistance R7With compensation of ground capacitor C7；
The resistance R4The other end respectively with resistance R6The other end, resistance R8One end and ground resistance R5Connection, it is described
Resistance R8The other end respectively with resistance R9One end and resistance R10One end connection, the resistance R9The other end and top layer
Transistor M2Drain electrode connection, the resistance R10The other end and top layer transistor M4Drain electrode connection.
4. inverse F class according to claim 1 stacks power amplifier, which is characterized in that described to export inverse F class impedance matching
Power synthesis network includes capacitance C15, the capacitance C15One end be to export inverse F class impedance matching power combing net
The output end of network, the other end respectively with microstrip line TL10One end, microstrip line TL11One end and capacitor C12One end connect
It connects；
The microstrip line TL10The other end respectively with microstrip line TL9One end and the first resonant network resistance connection, it is described micro-
Band line TL9The other end be the first input end for exporting inverse F class impedance matching power synthesis network, and with capacitor C11One end connect
It connects；The microstrip line TL11The other end respectively with microstrip line TL12One end and the second resonant network resistance connection, it is described micro-
Band line TL12The other end be the second input terminal for exporting inverse F class impedance matching power synthesis network, and with capacitor C13One end
Connection；The capacitor C11The other end, capacitor C12The other end and capacitor C13The other end link together and be grounded.
5. inverse F class according to claim 4 stacks power amplifier, which is characterized in that first resonant network resistance
Including the first LC resonance circuit, the microstrip line TL being sequentially connected in series13, resistance R11With ground capacity C17, the first LC resonance circuit
Including inductance L in parallel1With capacitor C14, one end and microstrip line TL13Connection, the other end and microstrip line TL10Connection；It is described
Microstrip line TL13With resistance R11Connecting node also with the first low pressure bias supply Vd1Connection；
Second resonant network resistance includes the second LC resonance circuit, the microstrip line TL being sequentially connected in series14, resistance R12With ground connection electricity
Hold C18, the second LC resonance circuit includes inductance L in parallel2With capacitor C16, one end and microstrip line TL14Connection, it is another
End and microstrip line TL11Connection；The microstrip line TL14With resistance R12Connecting node also with the second low pressure bias supply Vd2Connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821310190.7U CN208656727U (en) | 2018-08-14 | 2018-08-14 | A kind of high-power high-efficiency high-gain stacks power amplifier against F class |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821310190.7U CN208656727U (en) | 2018-08-14 | 2018-08-14 | A kind of high-power high-efficiency high-gain stacks power amplifier against F class |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108768323A (en) * | 2018-08-14 | 2018-11-06 | 成都嘉纳海威科技有限责任公司 | A kind of high-power high-efficiency high-gain stacks power amplifier against F classes |
| CN111934632A (en) * | 2020-09-27 | 2020-11-13 | 成都嘉纳海威科技有限责任公司 | Ultra-wideband high-power amplifier |
-
2018
- 2018-08-14 CN CN201821310190.7U patent/CN208656727U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108768323A (en) * | 2018-08-14 | 2018-11-06 | 成都嘉纳海威科技有限责任公司 | A kind of high-power high-efficiency high-gain stacks power amplifier against F classes |
| CN108768323B (en) * | 2018-08-14 | 2023-09-01 | 成都嘉纳海威科技有限责任公司 | High-power high-efficiency high-gain reverse F-class stacked power amplifier |
| CN111934632A (en) * | 2020-09-27 | 2020-11-13 | 成都嘉纳海威科技有限责任公司 | Ultra-wideband high-power amplifier |
| CN111934632B (en) * | 2020-09-27 | 2021-02-09 | 成都嘉纳海威科技有限责任公司 | Ultra-wideband high-power amplifier |
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