CN208656726U - A kind of high-frequency high-power high efficiency Darlington tube core based on four Stack Technologies - Google Patents
A kind of high-frequency high-power high efficiency Darlington tube core based on four Stack Technologies Download PDFInfo
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- CN208656726U CN208656726U CN201821310204.5U CN201821310204U CN208656726U CN 208656726 U CN208656726 U CN 208656726U CN 201821310204 U CN201821310204 U CN 201821310204U CN 208656726 U CN208656726 U CN 208656726U
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Abstract
The utility model discloses a kind of high-frequency high-power high efficiency Darlington tube core based on four Stack Technologies, including input that odd mould resistor network, matching four stacks that amplification networks, matching four stacks that amplification networks, matching four stacks that amplification networks, matching four stacks amplification networks, three-level self-bias potential-divider network and exports odd mould resistor network in the 4th in third in second in first.The high-frequency high-power high efficiency Darlington tube core that the utility model is realized has the advantages such as output power is high, optimum load impedance is high, die area is small.
Description
Technical field
The utility model belongs to radio-frequency power amplifier transistor dies and integrated circuit and SiP technical field, specifically relates to
And a kind of design of the high-frequency high-power high efficiency Darlington tube core based on four Stack Technologies.
Background technique
With the fast development of the wireless communications markets such as mobile communication, software radio, WLAN (WLAN), radio frequency
Front end assemblies also require to develop to highly integrated, low-power consumption, compact-sized, cheap direction therewith.Radio frequency and microwave power
Important module of the amplifier as transmitter, is most circuit that consumes energy in entire transmitter, mainly by power amplifier transistor
Pipe tube core and periphery match circuit are constituted.When realizing power amplifier tube core using semiconductor integrated circuit technique design,
Performance and cost receive certain restriction, are mainly reflected in following several respects:
(1) high-frequency high-power ability is limited: by the development of semiconductor technology and the shadow of transistor size scaled down
It rings, when the grid length of transistor is shorter and shorter, the high-frequency gain characteristic of transistor is better, but its breakdown voltage can reduce, from
And transistor drain output voltage swing is limited, and then limit the high frequency power capacity of one-transistor.Currently, in order to obtain
High-frequency high-power characteristic is obtained, typical solution uses the transistor of big grid width size, before guaranteeing that drain voltage is constant
It puts, increases power capacity in the way of electric current synthesis.But this solution but increases gate-source capacitance, reduces
Input impedance and optimum load impedance increase the matched design difficulty of circuit impedance.
(2) high-frequency wideband high efficiency ability is limited: under conditions of guaranteeing the high-power output of high frequency, since tradition solves
Scheme causes Transistor Impedance to substantially reduce, and circuit designers have to realize 50 ohmages to extremely low in very wide frequency band
The impedance of impedance converts, and introducing as small as possible, with interior Insertion Loss, this brings severe design to broadband high-efficiency index
Test.
(3) high-frequency high-power gain is limited: receiving the influence of transistor parasitic parameter, radio frequency and microwave power amplifier are brilliant
Body pipe tube core working frequency is lower, and power gain is lower, in order to obtain good high gain characteristics, generally requires to select breakdown
The low transistor types of voltage are to obtain high gain characteristics to sacrifice the cost of power capacity in this way.
Currently, the structure of common high-frequency high-power amplifier tube core is relatively simple, it is all often using one-transistor
The structure that multichannel longitudinally synthesizes, or the transistor of big grid width size is directlyed adopt, it is efficient to meet every high power simultaneously
The requirement of rate is very difficult, in general, the realization of its impedance matching is to reduce efficiency, or reduction bandwidth of operation etc. and come for cost
It obtains.
It can thus be seen that radio frequency and microwave power amplifier transistor dies design difficulty are as follows: (1) high-frequency high-power is defeated
Difficulty is larger out；(2) high-frequency wideband high efficiency difficulty is larger；(3) high-frequency high-power gain is limited.
Utility model content
The purpose of this utility model is to propose a kind of high-frequency high-power high efficiency Darlington based on four Stack Technologies
Tube core has many advantages, such as that high-power output ability, high power gain, high optimum load impedance, chip area are small and at low cost.
A kind of the technical solution of the utility model are as follows: high-frequency high-power high efficiency Darlington based on four Stack Technologies
Tube core, including input odd mould resistor network, in first matching four stack amplification networks, in second matching four stack amplification networks,
Matching four stacks amplification network in third, the 4th interior matching four stacks amplification network, three-level self-bias potential-divider network and exports surprise mould
Resistor network；It is entire high-frequency high-power high efficiency Darlington tube core that matching four, which stacks the input terminal of amplification network, in first
First input end, output end be entire high-frequency high-power high efficiency Darlington tube core the first output end；In second
The input terminal that matching four stacks amplification network is the second input terminal of entire high-frequency high-power high efficiency Darlington tube core,
Output end is the second output terminal of entire high-frequency high-power high efficiency Darlington tube core；Matching four stacks amplification net in third
The input terminal of network is the third input terminal of entire high-frequency high-power high efficiency Darlington tube core, and output end is entire high frequency
The third output end of high-power high-efficiency Darlington tube core；The input terminal that matching four stacks amplification network in 4th is entire
4th input terminal of high-frequency high-power high efficiency Darlington tube core, output end are that entire high-frequency high-power high efficiency is compound
4th output end of transistor dies；Input odd mould resistor network respectively with the inputs that matchs four stackings in first and amplify networks
It holds, the second interior matching four stacks the input terminal of amplification networks, the input terminals and the 4th of four stacking amplification networks are matched in third
Interior matching four stacks the input terminal connection of amplification network；Three-level self-bias potential-divider network respectively with matched in first four stacking amplification nets
Network, matching four stacks that amplification networks, matching four stacks matching four in amplification networks and the 4th and stacks amplification in third in second
Network connection；Export odd mould resistor network respectively with match four stackings in first and amplifies the output end of networks, matches four in second
Stack that the amplification output end of network, matching four stacks that the output end of amplification networks, matching four stacks amplification nets in the 4th in third
The output end connection of the output end and three-level self-bias potential-divider network of network.
The beneficial effects of the utility model are: the high-frequency high-power high efficiency Darlington pipe that the utility model is realized
Core has the advantages such as output power is high, optimum load impedance is high, die area is small.
Further, matching four stacks that amplification networks, matching four stacks amplification networks, matches in third in second in first
Four stack matching four in amplification networks and the 4th, and to stack amplification network structures all the same, includes according to source drain successively phase
Even stack top layer transistor, the first middle layer transistor, the second middle layer transistor and the bottom transistor constituted；Bottom is brilliant
The source grounding of body pipe, grid match the input terminal of four stacking amplification networks for it inside；Top layer transistor, in first
The grid of interbed transistor and the second middle layer transistor is all connected with two-way grid compensation circuit, and passes through resistance and three-level self-bias
Potential-divider network connection；Grid compensation circuit includes concatenated grid steady resistance and compensation of ground capacitor；The leakage of top layer transistor
Extremely its output end for matching four stacking amplification networks inside；The drain electrode of bottom transistor and the source of the second middle layer transistor
L-type matching is respectively connected between pole and between the drain electrode of the second middle layer transistor and the source electrode of the first middle layer transistor
Minor matters；L-type matching minor matters include being connected between the drain electrode and source electrode of two adjacent transistors microstrip line and to be connected in parallel on this micro-
With the open circuit microstrip line between line and transistor drain；Between the drain electrode of first middle layer transistor and the source electrode of top layer transistor
It is respectively connected with microstrip line, and is connected with CL resonance minor matters between the microstrip line and the drain electrode of the first middle layer transistor；CL resonance
Minor matters include concatenated microstrip line and ground capacity.
The beneficial effect of above-mentioned further scheme is: the core architecture of the utility model uses interior matching four and stacks amplification
Network, saves the area of chip, while realizing good high frequency power fan-out capability and power gain ability, avoids collection
At the low breakdown voltage characteristic of circuit technology, the Stability and dependability of circuit is improved.
Further, three-level self-bias potential-divider network includes the resistance R being sequentially connected in series31, resistance R28, resistance R25With ground connection electricity
Hinder R22, resistance R31One end connect resistance R28, the other end is the output end of three-level self-bias potential-divider network；Resistance R31And resistance
R28Connecting node also respectively with resistance R29One end and resistance R30One end connection, resistance R29The other end pass through electricity respectively
It hinders and matches the grid company that four stackings amplify networks and the second interior matching four stacks top layer transistor in amplification network in first
It connects, resistance R30The other end pass through match in resistance and third respectively and match four heaps in four stacking amplification networks and the 4th and stack
The grid connection of top layer transistor in big network；Resistance R28With resistance R25Connecting node also respectively with resistance R26One end and
Resistance R27One end connection, resistance R26The other end pass through resistance respectively and amplify networks and the with four stackings matchs in first
Matching four stacks the grid connection of the first middle layer transistor in amplification network, resistance R in two27The other end pass through resistance respectively
The grid that matching four in four stacking amplification networks and the 4th stacks the first middle layer transistor in amplification network are matched in third
Pole connection；Resistance R25With ground resistance R22Connecting node also respectively with resistance R23One end and resistance R24One end connection, electricity
Hinder R23The other end pass through respectively resistance with first in match four stacking amplification networks and second in matching four stack amplify nets
The grid connection of second middle layer transistor, resistance R in network24The other end pass through respectively and match four heaps in resistance and third and stack
Matching four stacks the grid connection of the second middle layer transistor in amplification network in big network and the 4th.
The beneficial effect of above-mentioned further scheme is: the utility model uses three-level self-bias potential-divider network, which exists
Matching four stacks in four shares between amplification network, so that the stacked transistors in stacked structure in addition to bottom transistor
Grid power supply realizes voltage self-bias, enormously simplifies peripheral power supply structure；And the conventional amplification network that stacks is using periphery
Potential-divider network stacks network implementations to multichannel and independently powers, and complexity is relatively high.
Further, inputting odd mould resistor network includes resistance R1, resistance R2With resistance R3；Resistance R1It is connected in first
Matching four stacks matching four in the input terminal and second of amplification network and stacks between the input terminal of amplification network, resistance R2It is connected to
Matching four stacks matching four in the input terminal and third of amplification network and stacks between the input terminal of amplification network in second, resistance R3
The input terminal of four stacking amplification network of matching and the 4th interior matching four in third is connected to stack between the input terminal for amplifying network.
Exporting odd mould resistor network includes resistance R50, resistance R51, resistance R52With resistance R53；Resistance R50It is connected in first
Matching four stacks matching four in the output end and second of amplification network and stacks between the output end of amplification network, resistance R51It is connected to
Matching four stacks between the output end of amplification network and the output end of three-level self-bias potential-divider network in second, resistance R52It is connected to three
Matching four stacks between the output end of amplification network in the output end and third of grade self-bias potential-divider network, resistance R53It is connected to third
Interior matching four stacks matching four in the output end and the 4th of amplification network and stacks between the output end of amplification network.
The beneficial effect of above-mentioned further scheme is: the utility model is electric using the odd mould resistor network of input and the odd mould of output
Network is hindered to inhibit the odd mould of transistor dies to shake.
Detailed description of the invention
It is multiple that Fig. 1 show a kind of high-frequency high-power high efficiency based on four Stack Technologies provided by the embodiment of the utility model
Close transistor dies functional block diagram.
It is multiple that Fig. 2 show a kind of high-frequency high-power high efficiency based on four Stack Technologies provided by the embodiment of the utility model
Close transistor die circuitry figure.
Specific embodiment
It is described in detail the illustrative embodiments of the utility model with reference to the drawings.It should be appreciated that showing in attached drawing
It is only exemplary out with the embodiment of description, it is intended that illustrate the principles of the present invention and spirit, and not limit this
The range of utility model.
The utility model embodiment provides a kind of high-frequency high-power high efficiency Darlington based on four Stack Technologies
Tube core, as shown in Figure 1, amplifying networks including four stacking of matching in input surprise mould resistor network, first, the second interior matching four stacks
Amplify network, in third matching four stack amplification networks, in the 4th matching four stack amplification networks, three-level self-bias potential-divider network and
Export odd mould resistor network.
It is entire high-frequency high-power high efficiency Darlington tube core that matching four, which stacks the input terminal of amplification network, in first
First input end, output end be entire high-frequency high-power high efficiency Darlington tube core the first output end；In second
The input terminal that matching four stacks amplification network is the second input terminal of entire high-frequency high-power high efficiency Darlington tube core,
Output end is the second output terminal of entire high-frequency high-power high efficiency Darlington tube core；Matching four stacks amplification net in third
The input terminal of network is the third input terminal of entire high-frequency high-power high efficiency Darlington tube core, and output end is entire high frequency
The third output end of high-power high-efficiency Darlington tube core；The input terminal that matching four stacks amplification network in 4th is entire
4th input terminal of high-frequency high-power high efficiency Darlington tube core, output end are that entire high-frequency high-power high efficiency is compound
4th output end of transistor dies.
Input odd mould resistor network respectively with match four stackings in first and amplifies the input terminal of networks, matches four heaps in second
Stack that the input terminal of big network, matching four stacks matching four in the input terminal and the 4th of amplification networks and stacks amplification nets in third
The input terminal of network connects；Three-level self-bias potential-divider network respectively with match four stacking amplification networks in first, match four heaps in second
Stack that big network, matching four stacks matching four in amplification networks and the 4th and stacks amplification network connection in third；Export odd mould
Resistor network respectively with match that the output end of four stacking amplification networks, matching four stacks the outputs of amplification networks in second in first
It holds, matching four stacks the output end of amplification networks in third, the 4th interior matching four stacks the output ends and three-level of amplification networks
The output end of self-bias potential-divider network connects.
As shown in Fig. 2, matching four stacks that amplification networks, matching four stacks amplification networks, in third in second in first
It is all the same that four stacking amplification network structure of matching in amplification network and the 4th is stacked with four.
It includes being sequentially connected according to source drain that matching four, which stacks amplification network, in the utility model embodiment, in first
Stack the top layer transistor M constituted4, the first middle layer transistor M3, the second middle layer transistor M2And bottom transistor M1。
Bottom transistor M1Source electrode ground connection, grid be first in matching four stack amplification networks input terminals.
Second middle layer transistor M2Grid connection first grid compensation circuit and second grid compensation circuit, and pass through
Resistance R6It is connect with three-level self-bias potential-divider network；First grid compensation circuit includes concatenated grid steady resistance R4It is connect with compensation
Ground capacitor C1, second grid compensation circuit includes concatenated grid steady resistance R5With compensation of ground capacitor C2。
First middle layer transistor M3Grid connection third grid compensation circuit and the 4th grid compensation circuit, and pass through
Resistance R7It is connect with three-level self-bias potential-divider network；Third grid compensation circuit includes concatenated grid steady resistance R8It is connect with compensation
Ground capacitor C3, the 4th grid compensation circuit includes concatenated grid steady resistance R9With compensation of ground capacitor C4。
Top layer transistor M4Drain electrode be first in matching four stack amplification networks output ends, grid connect the 5th grid
Pole compensation circuit and the 6th grid compensation circuit, and pass through resistance R10It is connect with three-level self-bias potential-divider network；The compensation of 5th grid
Circuit includes concatenated grid steady resistance R11With compensation of ground capacitor C5, the 6th grid compensation circuit includes that concatenated grid is steady
Determine resistance R12With compensation of ground capacitor C6。
Bottom transistor M1Drain electrode and the second middle layer transistor M2Source electrode between be connected with the first L-type matching minor matters；
First L-type matching minor matters include being connected on bottom transistor M1Drain electrode and the second middle layer transistor M2Source electrode between micro-strip
Line TL2And it is connected in parallel on microstrip line TL2With bottom transistor M1Drain electrode between open circuit microstrip line TL1。
Second middle layer transistor M2Drain electrode and the first middle layer transistor M3Source electrode between be connected with the second L-type
With minor matters；Second L-type matching minor matters include being connected on the second middle layer transistor M2Drain electrode and the first middle layer transistor M3's
Microstrip line TL between source electrode4And it is connected in parallel on microstrip line TL4With the second middle layer transistor M2Drain electrode between open circuit microstrip line
TL3。
First middle layer transistor M3Drain electrode and top layer transistor M4Source electrode between be connected with microstrip line TL6, and micro-strip
Line TL6With the first middle layer transistor M3Drain electrode between be connected with the first CL resonance minor matters；First CL resonance minor matters include series connection
Microstrip line TL5With ground capacity C28。
It includes that the top layer transistor for stacking and constituting is sequentially connected according to source drain that matching four, which stacks amplification network, in second
M8, the first middle layer transistor M7, the second middle layer transistor M6And bottom transistor M5。
Bottom transistor M5Source electrode ground connection, grid be second in matching four stack amplification networks input terminals.
Second middle layer transistor M6Grid connect the 7th grid compensation circuit and the 8th grid compensation circuit, and pass through
Resistance R13It is connect with three-level self-bias potential-divider network；7th grid compensation circuit includes concatenated grid steady resistance R14And compensation
Ground capacity C7, the 8th grid compensation circuit includes concatenated grid steady resistance R15With compensation of ground capacitor C8。
First middle layer transistor M7Grid connect the 9th grid compensation circuit and the tenth grid compensation circuit, and pass through
Resistance R16It is connect with three-level self-bias potential-divider network；9th grid compensation circuit includes concatenated grid steady resistance R17And compensation
Ground capacity C9, the tenth grid compensation circuit includes concatenated grid steady resistance R18With compensation of ground capacitor C10。
Top layer transistor M8Drain electrode be second in matching four stack amplification networks output ends, grid connection the 11st
Grid compensation circuit and the 12nd grid compensation circuit, and pass through resistance R19It is connect with three-level self-bias potential-divider network；11st grid
Pole compensation circuit includes concatenated grid steady resistance R20With compensation of ground capacitor C11, the 12nd grid compensation circuit includes string
The grid steady resistance R of connection21With compensation of ground capacitor C12。
Bottom transistor M5Drain electrode and the second middle layer transistor M6Source electrode between be connected with third L-type matching minor matters；
Third L-type matching minor matters include being connected on bottom transistor M5Drain electrode and the second middle layer transistor M6Source electrode between micro-strip
Line TL8And it is connected in parallel on microstrip line TL8With bottom transistor M5Drain electrode between open circuit microstrip line TL7。
Second middle layer transistor M6Drain electrode and the first middle layer transistor M7Source electrode between be connected with the 4th L-type
With minor matters；4th L-type matching minor matters include being connected on the second middle layer transistor M6Drain electrode and the first middle layer transistor M7's
Microstrip line TL between source electrode10And it is connected in parallel on microstrip line TL10With the second middle layer transistor M6Drain electrode between open circuit micro-strip
Line TL9。
First middle layer transistor M7Drain electrode and top layer transistor M8Source electrode between be connected with microstrip line TL12, and it is micro-
Band line TL12With the first middle layer transistor M7Drain electrode between be connected with the 2nd CL resonance minor matters；2nd CL resonance minor matters include
Concatenated microstrip line TL11With ground capacity C17。
It includes that the top layer transistor for stacking and constituting is sequentially connected according to source drain that matching four, which stacks amplification network, in third
M12, the first middle layer transistor M11, the second middle layer transistor M10And bottom transistor M9。
Bottom transistor M9Source electrode ground connection, grid be third in matching four stack amplification networks input terminals.
Second middle layer transistor M10Grid connect the 13rd grid compensation circuit and the 14th grid compensation circuit, and
Pass through resistance R32It is connect with three-level self-bias potential-divider network；13rd grid compensation circuit includes concatenated grid steady resistance R33
With compensation of ground capacitor C13, the 14th grid compensation circuit includes concatenated grid steady resistance R34With compensation of ground capacitor C14。
First middle layer transistor M11Grid connect the 15th grid compensation circuit and the 16th grid compensation circuit, and
Pass through resistance R35It is connect with three-level self-bias potential-divider network；15th grid compensation circuit includes concatenated grid steady resistance R36
With compensation of ground capacitor C15, the 16th grid compensation circuit includes concatenated grid steady resistance R37With compensation of ground capacitor C16。
Top layer transistor M12Drain electrode be third in matching four stack amplification networks output ends, grid connection the 17th
Grid compensation circuit and the 18th grid compensation circuit, and pass through resistance R38It is connect with three-level self-bias potential-divider network；17th grid
Pole compensation circuit includes concatenated grid steady resistance R39With compensation of ground capacitor C19, the 18th grid compensation circuit includes string
The grid steady resistance R of connection40With compensation of ground capacitor C20。
Bottom transistor M9Drain electrode and the second middle layer transistor M10Source electrode between be connected with the 5th L-type matching branch
Section；5th L-type matching minor matters include being connected on bottom transistor M9Drain electrode and the second middle layer transistor M10Source electrode between
Microstrip line TL14And it is connected in parallel on microstrip line TL14With bottom transistor M9Drain electrode between open circuit microstrip line TL13。
Second middle layer transistor M10Drain electrode and the first middle layer transistor M11Source electrode between be connected with the 6th L-type
Match minor matters；6th L-type matching minor matters include being connected on the second middle layer transistor M10Drain electrode and the first middle layer transistor
M11Source electrode between microstrip line TL16And it is connected in parallel on microstrip line TL16With the second middle layer transistor M10Drain electrode between open circuit
Microstrip line TL15。
First middle layer transistor M11Drain electrode and top layer transistor M12Source electrode between be connected with microstrip line TL18, and it is micro-
Band line TL18With the first middle layer transistor M11Drain electrode between be connected with the 3rd CL resonance minor matters；3rd CL resonance minor matters include
Concatenated microstrip line TL17With ground capacity C18。
It includes that the top layer transistor for stacking and constituting is sequentially connected according to source drain that matching four, which stacks amplification network, in 4th
M16, the first middle layer transistor M15, the second middle layer transistor M14And bottom transistor M13。
Bottom transistor M13Source electrode ground connection, grid be the 4th in matching four stack amplification networks input terminals.
Second middle layer transistor M14Grid connect the 19th grid compensation circuit and the 20th grid compensation circuit, and
Pass through resistance R41It is connect with three-level self-bias potential-divider network；19th grid compensation circuit includes concatenated grid steady resistance R42
With compensation of ground capacitor C21, the 20th grid compensation circuit includes concatenated grid steady resistance R43With compensation of ground capacitor C22。
First middle layer transistor M15Grid connect the 21st grid compensation circuit and the 22nd grid compensation electricity
Road, and pass through resistance R44It is connect with three-level self-bias potential-divider network；21st grid compensation circuit includes that concatenated grid is stablized
Resistance R45With compensation of ground capacitor C23, the 22nd grid compensation circuit includes concatenated grid steady resistance R46It is connect with compensation
Ground capacitor C24。
Top layer transistor M16Drain electrode be the 4th in matching four stack amplification networks output ends, grid connection the 20th
Three grid compensation circuits and the 24th grid compensation circuit, and pass through resistance R47It is connect with three-level self-bias potential-divider network；Second
13 grid compensation circuits include concatenated grid steady resistance R48With compensation of ground capacitor C26, the 24th grid compensation electricity
Road includes concatenated grid steady resistance R49With compensation of ground capacitor C27。
Bottom transistor M13Drain electrode and the second middle layer transistor M14Source electrode between be connected with the 7th L-type matching branch
Section；7th L-type matching minor matters include being connected on bottom transistor M13Drain electrode and the second middle layer transistor M14Source electrode between
Microstrip line TL20And it is connected in parallel on microstrip line TL20With bottom transistor M13Drain electrode between open circuit microstrip line TL19。
Second middle layer transistor M14Drain electrode and the first middle layer transistor M15Source electrode between be connected with the 8th L-type
Match minor matters；8th L-type matching minor matters include being connected on the second middle layer transistor M14Drain electrode and the first middle layer transistor
M15Source electrode between microstrip line TL22And it is connected in parallel on microstrip line TL22With the second middle layer transistor M14Drain electrode between open circuit
Microstrip line TL21。
First middle layer transistor M15Drain electrode and top layer transistor M16Source electrode between be connected with microstrip line TL24, and it is micro-
Band line TL24With the first middle layer transistor M15Drain electrode between be connected with the 4th CL resonance minor matters；4th CL resonance minor matters include
Concatenated microstrip line TL23With ground capacity C25。
In the utility model embodiment, three-level self-bias potential-divider network includes the resistance R being sequentially connected in series31, resistance R28, resistance
R25With ground resistance R22, resistance R31One end connect resistance R28, the other end is the output end of three-level self-bias potential-divider network.Electricity
Hinder R31With resistance R28Connecting node also respectively with resistance R29One end and resistance R30One end connection, resistance R29The other end
It is separately connected resistance R10With resistance R19, resistance R30The other end be separately connected resistance R38With resistance R47.Resistance R28With resistance R25
Connecting node also respectively with resistance R26One end and resistance R27One end connection, resistance R26The other end be separately connected resistance
R7With resistance R16, resistance R27The other end be separately connected resistance R35With resistance R44.Resistance R25With ground resistance R22Connection section
Point also respectively with resistance R23One end and resistance R24One end connection, resistance R23The other end be separately connected resistance R6And resistance
R13, resistance R24The other end be separately connected resistance R32With resistance R41。
Inputting odd mould resistor network includes resistance R1, resistance R2With resistance R3；Resistance R1Matching four in first is connected to stack
Amplify matching four in the input terminal and second of network to stack between the input terminal of amplification network, resistance R2It is connected to matching in second
Four, which stack matching four in the input terminal of amplification network and third, stacks between the input terminal of amplification network, resistance R3It is connected to third
Interior matching four stacks matching four in the input terminal and the 4th of amplification network and stacks between the input terminal of amplification network.
Exporting odd mould resistor network includes resistance R50, resistance R51, resistance R52With resistance R53；Resistance R50It is connected in first
Matching four stacks matching four in the output end and second of amplification network and stacks between the output end of amplification network, resistance R51It is connected to
Matching four stacks between the output end of amplification network and the output end of three-level self-bias potential-divider network in second, resistance R52It is connected to three
Matching four stacks between the output end of amplification network in the output end and third of grade self-bias potential-divider network, resistance R53It is connected to third
Interior matching four stacks matching four in the output end and the 4th of amplification network and stacks between the output end of amplification network.
It is introduced below with reference to concrete operating principle and process of the Fig. 2 to the utility model:
The core architecture of the utility model stacks amplification network using the identical interior matching four of four structures, respectively to by four
The radiofrequency signal of a input terminal IN1~IN4 input amplifies, and four road radio frequency output signals is obtained, respectively by four output ends
OUT1~OUT4 output.
The interior matching four that the utility model uses stacks amplification network and saves the area of chip, while realizing good
High frequency power fan-out capability and power gain ability avoid the low breakdown voltage characteristic of integrated circuit technology, improve circuit
Stability and dependability.Matching four stacks in amplification network in each, the drain electrode of bottom transistor and the second middle layer transistor
Source electrode between and the second middle layer transistor drain electrode and the first middle layer transistor source electrode between be respectively connected with L-type
Minor matters are matched, impedance matching of the stacked structure between stacked transistors is enhanced.Meanwhile first middle layer transistor drain electrode and
It is respectively connected with CL resonance minor matters between the source electrode of top layer transistor, resonance stabilization is played to the source electrode of top layer transistor.
The utility model uses three-level self-bias potential-divider network, which stacks between amplification network in matching four in four
It shares, so that the grid power supply of the stacked transistors in stacked structure in addition to bottom transistor realizes voltage self-bias, significantly
Simplify peripheral power supply structure.
In addition, the utility model inhibits transistor dies using inputting odd mould resistor network and exporting odd mould resistor network
Odd mould concussion.
In the utility model embodiment, the size of the size of transistor and other DC feedback resistance, compensating electric capacity is comprehensive
It is determined after the indices such as gain, bandwidth and the output power of the entire circuit of conjunction consideration, passes through the layout design and conjunction in later period
Required indices can be better achieved in removing the work office, realize high-power output ability under high frequency condition, high power
Gain, high optimum load impedance, chip area are small and at low cost.
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this reality
With novel principle, it should be understood that the scope of the present invention is not limited to such specific embodiments and embodiments.
Those skilled in the art can be made according to the technical disclosures disclosed by the utility model it is various do not depart from it is practical
Novel substantive various other specific variations and combinations, these variations and combinations are still within the protection scope of the present invention.
Claims (5)
1. a kind of high-frequency high-power high efficiency Darlington tube core based on four Stack Technologies, which is characterized in that including input
Odd mould resistor network, matching four stacks that amplification networks, matching four stacks amplification networks, matches four heaps in third in second in first
Stack big network, the 4th interior matching four stacks amplification networks, three-level self-bias potential-divider network and exports surprise mould resistor network；
It is the entire high-frequency high-power high efficiency Darlington that matching four, which stacks the input terminal of amplification network, in described first
The first input end of tube core, output end are the first output of the entire high-frequency high-power high efficiency Darlington tube core
End；It is the entire high-frequency high-power high efficiency Darlington pipe that matching four, which stacks the input terminal of amplification network, in described second
Second input terminal of core, output end are the second output terminal of the entire high-frequency high-power high efficiency Darlington tube core；
It is the entire high-frequency high-power high efficiency Darlington tube core that matching four, which stacks the input terminal of amplification network, in the third
Third input terminal, output end is the third output end of the entire high-frequency high-power high efficiency Darlington tube core；Institute
Stating matching four in the 4th and stacking the input terminal of amplification network is the entire high-frequency high-power high efficiency Darlington tube core
4th input terminal, output end are the 4th output end of the entire high-frequency high-power high efficiency Darlington tube core；
It is described input odd mould resistor network respectively with match four stackings in first and amplifies the input terminal of networks, matches four heaps in second
Stack that the input terminal of big network, matching four stacks matching four in the input terminal and the 4th of amplification networks and stacks amplification nets in third
The input terminal of network connects；
The three-level self-bias potential-divider network respectively with match that four stacking amplification networks, matching four stacks amplification nets in second in first
Matching four stacks matching four in amplification network and the 4th and stacks amplification network connection in network, third；
It is described export odd mould resistor network respectively with match four stackings in first and amplifies the output end of networks, matches four heaps in second
Stack that the output end of big network, matching four stacks that the output end of amplification networks, matching four stacks amplification networks in the 4th in third
Output end and three-level self-bias potential-divider network output end connection.
2. high-frequency high-power high efficiency Darlington tube core according to claim 1, which is characterized in that in described first
Matching four stacks that amplification networks, matching four stacks that amplification networks, matching four stacks in amplification networks and the 4th in third in second
Matching four stack amplification network structures it is all the same, include be sequentially connected according to source drain stack constitute top layer transistor,
First middle layer transistor, the second middle layer transistor and bottom transistor；
The source grounding of the bottom transistor, grid match the input terminal of four stacking amplification networks for it inside；
The grid of the top layer transistor, the first middle layer transistor and the second middle layer transistor is all connected with the compensation of two-way grid
Circuit, and connect by resistance with three-level self-bias potential-divider network；The grid compensation circuit includes concatenated grid steady resistance
With compensation of ground capacitor；
The drain electrode of the top layer transistor matches the output end of four stacking amplification networks for it inside；
Between the drain electrode of the bottom transistor and the source electrode of the second middle layer transistor and the leakage of the second middle layer transistor
L-type matching minor matters are respectively connected between pole and the source electrode of the first middle layer transistor；The L-type matching minor matters include being connected on two
Microstrip line and the open circuit being connected in parallel between the microstrip line and transistor drain are micro- between the drain electrode and source electrode of a adjacent transistor
Band line；
Microstrip line, and the microstrip line are respectively connected between the drain electrode of the first middle layer transistor and the source electrode of top layer transistor
And first middle layer transistor drain electrode between be connected with CL resonance minor matters；The CL resonance minor matters include concatenated microstrip line and
Ground capacity.
3. high-frequency high-power high efficiency Darlington tube core according to claim 2, which is characterized in that the three-level is certainly
Inclined potential-divider network includes the resistance R being sequentially connected in series31, resistance R28, resistance R25With ground resistance R22, the resistance R31One end connect
Connecting resistance R28, the other end is the output end of three-level self-bias potential-divider network；
The resistance R31With resistance R28Connecting node also respectively with resistance R29One end and resistance R30One end connection, it is described
Resistance R29The other end pass through respectively resistance with first in match four stacking amplification networks and second in matching four stack amplifications
The grid connection of top layer transistor, the resistance R in network30The other end pass through respectively and match four heaps in resistance and third and stack
Matching four stacks the grid connection of top layer transistor in amplification network in big network and the 4th；
The resistance R28With resistance R25Connecting node also respectively with resistance R26One end and resistance R27One end connection, it is described
Resistance R26The other end pass through respectively resistance with first in match four stacking amplification networks and second in matching four stack amplifications
The grid connection of first middle layer transistor, the resistance R in network27The other end pass through in resistance and third respectively and match four
Stack the grid connection that matching four in amplification network and the 4th stacks the first middle layer transistor in amplification network；
The resistance R25With ground resistance R22Connecting node also respectively with resistance R23One end and resistance R24One end connection,
The resistance R23The other end pass through respectively resistance with first in match four stacking amplification networks and second in matching four stackings
Amplify the grid connection of the second middle layer transistor in network, the resistance R24The other end pass through in resistance and third respectively
The grid connection that matching four in amplification network and the 4th stacks the second middle layer transistor in amplification network is stacked with four.
4. high-frequency high-power high efficiency Darlington tube core according to claim 1, which is characterized in that the input is odd
Mould resistor network includes resistance R1, resistance R2With resistance R3；The resistance R1It is connected to matching four in first and stacks amplification network
Matching four stacks between the input terminal of amplification network in input terminal and second, the resistance R2Matching four in second is connected to stack
Amplify matching four in the input terminal and third of network to stack between the input terminal of amplification network, the resistance R3It is connected in third
Matching four stacks matching four in the input terminal and the 4th of amplification network and stacks between the input terminal of amplification network.
5. high-frequency high-power high efficiency Darlington tube core according to claim 1, which is characterized in that the output is odd
Mould resistor network includes resistance R50, resistance R51, resistance R52With resistance R53；The resistance R50Matching four in first is connected to stack
Amplify matching four in the output end and second of network to stack between the output end of amplification network, the resistance R51It is connected in second
Matching four stacks between the output end of amplification network and the output end of three-level self-bias potential-divider network, the resistance R52It is connected to three-level
Matching four stacks between the output end of amplification network in the output end and third of self-bias potential-divider network, the resistance R53It is connected to
Matching four stacks matching four in the output end and the 4th of amplification network and stacks between the output end of amplification network in three.
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| CN201821310204.5U CN208656726U (en) | 2018-08-14 | 2018-08-14 | A kind of high-frequency high-power high efficiency Darlington tube core based on four Stack Technologies |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108768316A (en) * | 2018-08-14 | 2018-11-06 | 成都嘉纳海威科技有限责任公司 | A kind of high-frequency high-power high efficiency Darlington tube core based on four Stack Technologies |
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2018
- 2018-08-14 CN CN201821310204.5U patent/CN208656726U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108768316A (en) * | 2018-08-14 | 2018-11-06 | 成都嘉纳海威科技有限责任公司 | A kind of high-frequency high-power high efficiency Darlington tube core based on four Stack Technologies |
| CN108768316B (en) * | 2018-08-14 | 2023-09-01 | 成都嘉纳海威科技有限责任公司 | High-frequency high-power high-efficiency composite transistor die based on four-stacking technology |
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