CN106206706A - 形成晶体管的方法 - Google Patents

形成晶体管的方法 Download PDF

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CN106206706A
CN106206706A CN201510252854.3A CN201510252854A CN106206706A CN 106206706 A CN106206706 A CN 106206706A CN 201510252854 A CN201510252854 A CN 201510252854A CN 106206706 A CN106206706 A CN 106206706A
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raceway groove
source electrode
drain electrode
transistor
electrode
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CN106206706B (zh
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让-皮埃尔·科林格
卡洛斯·H.·迪亚兹
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

根据另一实施例，提供了形成晶体管的方法。该方法包括以下操作：提供衬底；在衬底上方提供源极；提供连接至源极的沟道；提供连接至沟道的漏极；提供邻近沟道的栅极绝缘体；提供邻近栅极绝缘体的栅极；在源极和栅极之间提供第一层间电介质；以及在漏极和栅极之间提供第二层间电介质，其中，形成的源极、漏极和沟道中的至少一个包括约20％至95％原子百分比的Sn。本发明涉及形成晶体管的方法。

Description

形成晶体管的方法
技术领域
本发明涉及形成晶体管的方法。
背景技术
诸如全环栅(GAA)晶体管的半导体器件是半导体产业中新兴的研究领域。然而，因为材料的限制，器件的速度是挑战。因此，需要改进以上缺陷。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种晶体管，包括：源极；漏极；以及沟道，位于所述源极和所述漏极之间，其中，所述源极、所述漏极和所述沟道中的至少一个含有约20％至95％原子百分比的Sn。
在上述晶体管中，所述源极、所述漏极和所述沟道由GeSn制成并且含有约20％至90％原子百分比的Sn。
在上述晶体管中，所述源极、所述漏极和所述沟道由SiSn制成。
在上述晶体管中，所述源极、所述漏极和所述沟道由SiGeSn制成。
在上述晶体管中，所述源极、所述漏极和所述沟道由相同的材料制成并且含有约70％原子百分比的Sn，并且其中，所述源极和所述漏极的截面大于所述沟道的截面。
在上述晶体管中，所述源极和所述漏极是金属化的，并且所述沟道是半导化的。
在上述晶体管中，所述源极和所述漏极具有约5纳米至30纳米的直径，并且所述沟道具有约1纳米至15纳米的直径。
在上述晶体管中，所述源极、所述漏极和所述沟道具有约5纳米至30纳米的厚度。
在上述晶体管中，还包括位于所述源极和所述沟道之间以及位于所述漏极和所述沟道之间的结。
在上述晶体管中，还包括：邻近所述沟道的栅极绝缘体；以及邻近所述栅极绝缘体的栅极。
根据本发明的另一方面，还提供了一种形成晶体管的方法，包括：形成源极；形成漏极；以及在所述源极和所述漏极之间形成沟道，其中，形成的所述源极、所述漏极和所述沟道中的至少一个含有约20％至95％原子百分比的Sn。
在上述方法中，形成所述源极、所述漏极和所述沟道包括形成为具有GeSn并且含有约20％至90％的原子百分比的Sn。
在上述方法中，形成所述源极、所述漏极和所述沟道包括形成为具有SiSn。
在上述方法中，形成所述源极、所述漏极和所述沟道包括形成为具有SiGeSn。
在上述方法中，形成所述源极、所述漏极和所述沟道包括形成为具有约70％原子百分比的Sn的相同的材料，并且其中，形成所述源极和所述漏极还包括在所述源极和所述漏极中形成比所述沟道中的截面更大的截面。
在上述方法中，形成所述源极和所述漏极包括形成具有约5纳米至30纳米的直径的所述源极和所述漏极，并且形成所述沟道还包括形成具有约1纳米至15纳米的直径的所述沟道。
在上述方法中，形成所述源极、所述漏极和所述沟道包括将所述源极、所述漏极和所述沟道形成至约5纳米至30纳米的厚度。
在上述方法中，，还包括：形成邻近所述沟道的栅极绝缘体；以及形成邻近所述栅极绝缘体的栅极。
根据本发明的又一方面，还提供了一种形成晶体管的方法，包括：提供衬底；在所述衬底上方提供源极；提供连接至所述源极的沟道；提供连接至所述沟道的漏极；提供邻近所述沟道的栅极绝缘体；提供邻近所述栅极绝缘体的栅极；在所述源极和所述栅极之间提供第一层间电介质；以及在所述漏极和所述栅极之间提供第二层间电介质，其中，形成的所述源极、所述漏极和所述沟道中的至少一个包括约20％至95％原子百分比的Sn。
在上述方法中，还包括：形成的所述源极、所述漏极和所述沟道包括具有约70％原子百分比的Sn的相同的材料，并且其中，形成所述源极和所述漏极还包括在所述源极和所述漏极中形成比所述沟道中的截面更大的截面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的在制造期间的第一阶段的示例性垂直全环栅结构的三维图。
图2是根据一些实施例的在制造期间的第二阶段的示例性垂直全环栅结构的三维图。
图3是根据一些实施例的在制造期间的第三阶段的示例性垂直全环栅结构的三维图。
图4是根据一些实施例的在制造期间的第四阶段的示例性垂直全环栅结构的三维图。
图5是根据一些实施例的在制造期间的第五阶段的示例性垂直全环栅结构的三维图。
图6是根据一些实施例的在制造期间的第六阶段的示例性垂直全环栅结构的三维图。
图7是根据一些实施例的在制造期间的第七阶段的示例性垂直全环栅结构的三维图。
图8是根据一些实施例的在制造期间的第八阶段的示例性垂直全环栅结构的三维图。
图9是根据一些实施例的示例性垂直全环栅结构的三维图。
图10是根据一些实施例的示例性垂直全环栅结构的三维图。
图11A是根据一些实施例的示例性垂直纳米线结构的三维图。
图11B是根据一些实施例的示例性水平纳米线结构而非垂直纳米线结构的三维图。
图12是形成晶体管的方法的流程图。
图13是形成晶体管的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的许多不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
本发明提供了用于晶体管的合金，该合金(例如，SiSn、GeSn和SiGeSn)具有约20％至约90％原子百分比的Sn以形成源极/漏极和沟道，从而使得晶体管能够承受高温处理。仔细选择Sn的原子百分比，使得具有由相同的材料制成的金属化源极、漏极和半导体沟道的晶体管成为可能。例如，具有70％原子百分比的Sn和30％原子百分比的Ge的GeSn提供了650℃的熔点并且可以用于制造晶体管。
晶体管包括具有不同截面的合金。在中心区域，合金的截面足够小以变为半导化并且限定沟道区。与沟道相关联的截面增大以形成金属化源极/漏极。源极/漏极区比沟道区具有更大的截面。当在全环栅MOSFET中时，沟道区在垂直或水平方向上被栅极堆叠件围绕。夹在源极和漏极之间的沟道具有由纳米线截面限定的带隙。例如，通过使用具有70％原子百分比的Sn和30％原子百分比的Ge的GeSn，具有4纳米至5纳米的截面的沟道提供了正带隙，并且具有例如10纳米的更大截面的源极/漏极区提供了零或负带隙。在该实施例中，由于源极/漏极区是由相同的金属合金制成的，所以不必形成结，但是如果期望，制造结是可能的。
图1是根据一些实施例的在制造期间的第一阶段的示例性垂直全环栅结构的三维图。如图1所示，在衬底102上方提供块状材料106(例如，SiSn、GeSn或SiGeSn)。在该实施例中，在衬底102和块状材料106之间提供用于外延生长的额外的缓冲件104(例如，SiGe、Ge)。在一些实施例中，额外的缓冲件104是可以忽略的。例如，衬底102包括任何数量的材料，诸如单独的硅、多晶硅、锗等或其组合。在一些实施例中，衬底102包括外延层、绝缘体上硅(SOI)结构、晶圆、或由晶圆形成的管芯。
在一些实施例中，块状材料106的材料是由SiSn制成的并且含有约20％至95％原子百分比的Sn。例如，具有约70％原子百分比的Sn和约30％原子百分比的Si的SiSn合金提供1300℃的熔点并且可以用作材料来制造经受得起高温处理(例如，900℃至1000℃)的晶体管。在一些实施例中，由SiSn制成的块状材料106的Sn的原子百分比为约以下中的至少一种：20％至30％、30％至40％、40％至50％、50％至60％、60％至70％、70％至80％、80％至90％、90％至95％、25％至35％、35％至45％、45％至55％、55％至65％、65％至75％、75％至85％、和85％至95％。
在一些实施例中，块状材料106的材料由GeSn制成并且含有约20％至90％原子百分比的Sn。例如，具有约70％原子百分比的Sn和约30％原子百分比的Ge的GeSn合金提供650℃的熔点并且可以用作材料来制造经受得起高温处理(例如，450℃至500℃)的晶体管。在一些实施例中，由GeSn制成的块状材料106的Sn的原子百分比为约以下中的至少一种：20％至30％、30％至40％、40％至50％、50％至60％、60％至70％、70％至80％、80％至90％、25％至35％、35％至45％、45％至55％、55％至65％、65％至75％、和75％至85％。
图2是根据一些实施例的在制造期间的第二阶段的示例性垂直全环栅结构的三维图。如图2所示，蚀刻块状材料106以形成源极202和纳米线204。可以使用本领域已知的任何数量的方式形成纳米线204，诸如通过图案化和蚀刻。
图3是根据一些实施例的在制造期间的第三阶段的示例性垂直全环栅结构的三维图。如图3所示，在源极202上方形成第一层间电介质302。第一层间电介质302的形成可以包括：沉积第一层间电介质302；对第一层间电介质302实施CMP，CMP停止于纳米线204；以及回蚀刻第一层间电介质302以暴露纳米线204的一部分。第一层间电介质302的沉积可以以任意数量的方式实现，诸如通过热生长、化学生长、原子层沉积(ALD)、化学汽相沉积(CVD)、旋涂沉积或等离子体增强化学汽相沉积(PECVD)。
图4是根据一些实施例的在制造期间的第四阶段的示例性垂直全环栅结构的三维图。如图4所示，邻近纳米线204并且在第一层间电介质302上方形成栅极绝缘体402。栅极绝缘体402可以是单层或具有HfO2、ZrO2、HfZrO2、Ga2O3、Gd2O3、TaSiO2、Al2O3、SiO2、LaLuO2、TmO2、TiO2或其他高k电介质的多层结构。
图5是根据一些实施例的在制造期间的第五阶段的示例性垂直全环栅结构的三维图。如图5所示，邻近栅极绝缘体402形成栅极502。栅极502的形成可以包括：沉积栅极502；对栅极502实施CMP，CMP停止于栅极绝缘体402；以及回蚀刻栅极502以暴露将被去除的栅极绝缘体402的一部分。栅极502可以包括功函金属(“WFM”)和金属栅极(“MG”)材料。例如，功函金属可以是TiN、W、WN、Mo、MoN、TiAl、TiAlC、或TaAlC；金属栅极材料可以是Al、W、Co、Cu、或掺杂的多晶硅。
图6是根据一些实施例的在制造期间的第六阶段的示例性垂直全环栅结构的三维图。如图6所示，蚀刻栅极绝缘体402以暴露纳米线204的除了被栅极502围绕的部分。被栅极502围绕的纳米线204的部分指的是沟道602。沟道602可以具有4纳米至5纳米的截面和提供正带隙。
图7是根据一些实施例的在制造期间的第七阶段的示例性垂直全环栅结构的三维图。如图7所示，在栅极502上方形成第二层间电介质702。第二层间电介质702的形成可以包括：沉积第二层间电介质702；对第二层间电介质702实施CMP，CMP停止于纳米线204；以及回蚀刻第二层间电介质702以暴露纳米线204的部分。第二层间电介质702的沉积可以以任意数量的方式实现，诸如通过热生长、化学生长、原子层沉积(ALD)、化学汽相沉积(CVD)、等离子体增强化学汽相沉积(PECVD)或旋涂沉积。
图8是根据一些实施例的在制造期间的第八阶段的示例性垂直全环栅结构的三维图。如图8所示，在第二层间电介质702和纳米线204上方提供漏极802(例如，SiSn、GeSn、或SiGeSn)。在一些实施例中，漏极802的材料是由SiSn制成的并且含有约20％至95％原子百分比的Sn。例如，具有约70％原子百分比的Sn和约30％原子百分比的Si的SiSn提供1300℃的熔点并且可以用作材料来制造经受得起高温处理(例如，900℃至1000℃)的晶体管。在一些实施例中，由SiSn制成的漏极802的Sn的原子百分比为约以下中的至少一种：20％至30％、30％至40％、40％至50％、50％至60％、60％至70％、70％至80％、80％至90％、90％至95％、25％至35％、35％至45％、45％至55％、55％至65％、65％至75％、75％至85％、和85％至95％。
在一些实施例中，该漏极802的材料由GeSn制成并且含有约20％至90％原子百分比的Sn。例如，具有约70％原子百分比的Sn和约30％原子百分比的Ge的GeSn提供650℃的熔点并且可以用作材料来制造经受得起高温处理(例如，450℃至500℃)的晶体管。在一些实施例中，由GeSn制成的漏极802的Sn的原子百分比为约以下中的至少一种：20％至30％、30％至40％、40％至50％、50％至60％、60％至70％、70％至80％、80％至90％、25％至35％、35％至45％、45％至55％、55％至65％、65％至75％、和75％至85％。
继续图8，提供具有带隙调制的晶体管800。晶体管800包括源极202、漏极802、沟道602和栅极502。沟道602夹在源极202和漏极802之间。栅极502控制晶体管800以导通或截止。源极202、漏极802和沟道602中的至少一种含有约20％至95％原子百分比的Sn。
在一些实施例中，源极202、漏极802和沟道602的材料中的至少一种是由SiSn制成的并且含有约20％至95％原子百分比的Sn。在一些实施例中，由SiSn制成的漏极802的Sn的原子百分比为约以下中的至少一种：20％至30％、30％至40％、40％至50％、50％至60％、60％至70％、70％至80％、80％至90％、90％至95％、25％至35％、35％至45％、45％至55％、55％至65％、65％至75％、75％至85％、和85％至95％。
在一些实施例中，源极202、漏极802和沟道602的材料中的至少一种是由SiGeSn制成的并且含有约20％至95％原子百分比的Sn。在一些实施例中，由SiGeSn制成的漏极802的Sn的原子百分比为约以下中的至少一种：20％至30％、30％至40％、40％至50％、50％至60％、60％至70％、70％至80％、80％至90％、90％至95％、25％至35％、35％至45％、45％至55％、55％至65％、65％至75％、75％至85％、和85％至95％。
在一些实施例中，源极202、漏极802和沟道602的材料中的至少一种是由GeSn制成的并且含有约20％至90％原子百分比的Sn。在一些实施例中，由GeSn制成的漏极802的Sn的原子百分比为约以下中的至少一种：20％至30％、30％至40％、40％至50％、50％至60％、60％至70％、70％至80％、80％至90％、25％至35％、35％至45％、45％至55％、55％至65％、65％至75％、和75％至85％。
晶体管800包括具有不同截面的合金。在中心区域，合金的截面足够小以变为半导化并且限定沟道区602。与沟道602相关联的截面增大以形成金属化源极/漏极202、208。金属化源极/漏极区202、208比沟道区602具有更大的截面。当在全环栅MOSFET中时，沟道区602在垂直或水平方向上被栅极502围绕。夹在源极202和漏极802之间的沟道602具有由纳米线截面限定的带隙。例如，通过使用具有70％原子百分比的Sn和30％原子百分比的Ge的GeSn，具有4纳米至5纳米的截面的沟道提供了正带隙，并且具有例如10纳米的更大截面的源极/漏极区提供了零或负带隙。
图9是根据一些实施例的示例性垂直全环栅结构的三维图。如图9所示，提供了具有带隙调制的半导体结构900。半导体结构900包括源极904、漏极902、和位于纳米线906中的沟道907。沟道907夹在源极904和漏极902之间。栅极(未示出)控制晶体管900以使其导通或截止。源极904、漏极902、和沟道907中的至少一种含有约20％至95％原子百分比的Sn。半导体结构900的典型尺寸如下。具有5纳米至30纳米的直径903、905的源极/漏极902、904可以提供零或负带隙，并且具有1纳米至15纳米的直径的沟道907可以提供正带隙。源极/漏极902、904和沟道907可以具有5纳米至30纳米的厚度。在实施例中，由于源极/漏极902、904是由金属合金制成的，因此不必形成PN结或肖特基结，但是如果期望，制造PN结或肖特基结是可能的。
图10是根据一些实施例的示例性垂直全环栅结构的三维图。如图10所示，提供了一种具有带隙调制的半导体结构1000。半导体结构1000包括源极1004、漏极1002、直径变化区域1012、1014以及纳米线1006中的沟道1007。沟道1007夹在源极1004和漏极1002之间。栅极(未示出)控制晶体管1000以导通或截止。相比于图9，半导体结构1000包括额外的直径变化区域1012、1014。每个结1012、1014分别连接源极/漏极1002、1004。该半导体结构1000的尺寸可以类似于图9，并且本文不再重复。
图11A是根据一些实施例的示例性垂直纳米线结构的三维图。如图11A所示，根据实施例，可以将垂直于衬底(未示出)的各种垂直纳米线施加于具有带隙调制的晶体管，垂直纳米线诸如圆形纳米线1102、椭圆形纳米线1104、条形纳米线1106、圆角正方形纳米线1108、方形纳米线1110、三角形纳米线1112或六边形纳米线1114。典型的纳米线不限于上述并且可以具有任何可能。
图11B是根据一些实施例的示例性水平纳米线结构而非垂直纳米线结构的三维图。如图11B所示，根据实施例，可以将平行于衬底(未示出)的各种水平纳米线施加于具有带隙调制的晶体管，水平纳米线诸如圆形纳米线1122、椭圆形纳米线1124、条形纳米线1126、圆角正方形纳米线1128、方形纳米线1130、三角形纳米线1132或六边形纳米线1134。
图12是形成晶体管的方法的流程图。方法1200包括以下操作：提供衬底(1202)；在衬底上方提供源极(1204)；提供连接至源极的沟道(1206)；提供连接至沟道的漏极(1208)；提供邻近沟道的栅极绝缘体(1210)；提供邻近栅极绝缘体的栅极(1212)；在源极和栅极之间提供第一层间电介质(1214)；以及在漏极和栅极之间提供第二层间电介质，其中形成的源极、漏极和沟道中的至少一个包括约20％至95％原子百分比的Sn(1216)。
方法1200还包括使用具有约70％原子百分比的Sn的相同的材料形成源极、漏极和沟道，并且其中，形成源极和漏极还包括在源极和漏极中形成比沟道中的截面更大的截面。
图13是形成晶体管的方法的流程图。方法1300包括以下操作：形成源极(1302)；形成漏极(1304)；和形成夹在源极和漏极之间的沟道，其中形成的源极、漏极和沟道中的至少一个包括约20％至95％原子百分比的Sn(1306)。
形成源极、漏极和沟道包括形成为具有GeSn并且含有约20％至90％的原子百分比的Sn。形成源极、漏极和沟道包括形成为具有SiSn。形成源极、漏极和沟道包括形成为具有SiGeSn。形成源极、漏极和沟道包括形成为具有约70％原子百分比的Sn的相同的材料，并且其中，形成源极和漏极还包括在源极和漏极中形成比沟道中的截面更大的截面。形成源极和漏极包括形成具有约5纳米至30纳米的直径的源极和漏极，并且形成沟道还包括形成具有约1纳米至15纳米的直径的沟道。形成源极、漏极和沟道包括将源极、漏极和沟道形成为具有约5纳米至30纳米的厚度。方法130还包括：形成邻近沟道的栅极绝缘体，以及形成邻近栅极绝缘体的栅极。
晶体管包括具有不同截面的合金。在中心区域，合金的截面足够小以变为半导化并且限定沟道区。与沟道相关联的截面增大以形成金属化源极/漏极。源极/漏极区比沟道具有更大的截面。当在全环栅MOSFET中时，沟道区在垂直或水平方向上被栅极堆叠件围绕。另一方面，夹在源极和漏极之间的沟道具有由纳米线截面限定的带隙。
根据实施例，提供了一种晶体管。该晶体管包括：源极；漏极；以及夹在源极和漏极之间的沟道，其中，源极、漏极和沟道中的至少一个含有约20％至95％原子百分比的Sn。
根据另一实施例，提供了一种形成晶体管的方法。该方法包括以下操作：提供衬底；在衬底上方提供源极；提供连接至源极的沟道；提供连接至沟道的漏极；提供邻近沟道的栅极绝缘体；提供邻近栅极绝缘体的栅极；在源极和栅极之间提供第一层间电介质；以及在漏极和栅极之间提供第二层间电介质，其中，形成的源极、漏极和沟道中的至少一个包括约20％至95％原子百分比的Sn。
根据另一实施例，提供了一种形成晶体管的方法。该方法包括以下操作：形成源极；形成漏极；以及形成夹在源极和漏极之间的沟道，其中，形成的源极、漏极和沟道中的至少一个包括约20％至95％原子百分比的Sn。
漏极可以是指已被作为漏极处理的区域，或未被处理但将被作为漏极处理的区域。源极可以是指已被作为源极处理的区域，或未被处理但将被作为源极处理的区域。沟道可以是指已被作为沟道处理的区域，或未被处理但将被作为沟道处理的区域。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种晶体管，包括：
源极；
漏极；以及
沟道，位于所述源极和所述漏极之间，其中，所述源极、所述漏极和所述沟道中的至少一个含有约20％至95％原子百分比的Sn。
2.根据权利要求1所述的晶体管，其中，所述源极、所述漏极和所述沟道由GeSn制成并且含有约20％至90％原子百分比的Sn。
3.根据权利要求1所述的晶体管，其中，所述源极、所述漏极和所述沟道由SiSn制成。
4.根据权利要求1所述的晶体管，其中，所述源极、所述漏极和所述沟道由SiGeSn制成。
5.根据权利要求1所述的晶体管，其中，所述源极、所述漏极和所述沟道由相同的材料制成并且含有约70％原子百分比的Sn，并且其中，所述源极和所述漏极的截面大于所述沟道的截面。
6.根据权利要求1所述的晶体管，其中，所述源极和所述漏极是金属化的，并且所述沟道是半导化的。
7.根据权利要求5所述的晶体管，其中，所述源极和所述漏极具有约5纳米至30纳米的直径，并且所述沟道具有约1纳米至15纳米的直径。
8.根据权利要求5所述的晶体管，其中，所述源极、所述漏极和所述沟道具有约5纳米至30纳米的厚度。
9.一种形成晶体管的方法，包括：
形成源极；
形成漏极；以及
在所述源极和所述漏极之间形成沟道，其中，形成的所述源极、所述漏极和所述沟道中的至少一个含有约20％至95％原子百分比的Sn。
10.一种形成晶体管的方法，包括：
提供衬底；
在所述衬底上方提供源极；
提供连接至所述源极的沟道；
提供连接至所述沟道的漏极；
提供邻近所述沟道的栅极绝缘体；
提供邻近所述栅极绝缘体的栅极；
在所述源极和所述栅极之间提供第一层间电介质；以及
在所述漏极和所述栅极之间提供第二层间电介质，其中，形成的所述源极、所述漏极和所述沟道中的至少一个包括约20％至95％原子百分比的Sn。
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