CN104134697B - 一种非对称肖特基源漏晶体管及其制备方法 - Google Patents
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Abstract
一种结合垂直沟道和非对称肖特基势垒源/漏结构的环栅MOS晶体管，包括一个垂直方向的环状半导体沟道(4)，一个环状栅电极(6)，一个环状栅介质层(5)，一个源区(2)，一个漏区(3)，一个半导体衬底(1)；其中，源区位于垂直沟道(4)的底部，与衬底相接；漏区位于垂直沟道的顶部；栅介质层和栅电极呈环状围绕住垂直沟道；源区和漏区分别与沟道形成不同势垒高度的肖特基接触；源漏所用金属材料不同。在与现有CMOS工艺兼容并且保持了传统GAA各种优点的条件下，该结构利用非对称肖特基势垒源/漏结构减小了漏电流、简化了工艺要求，并利用垂直沟道、环形栅结构突破了集成加工光刻极限限制，提高了集成度。
Description
技术领域
本发明属于CMOS超大集成电路(ULSI)中的场效应晶体管逻辑器件与电路领域，具体涉及一种结合垂直沟道和非对称肖特基势垒源/漏结构的环栅MOS晶体管及其制备方法。
背景技术
在摩尔定律的驱动下，传统MOSFET的特征尺寸不断缩小，如今已经到进入纳米尺度，随之而来，器件的短沟道效应等负面影响也愈加严重。漏致势垒降低、带带隧穿等效应使得器件关态漏泄电流不断增大。在对新型器件结构的研究中，源漏掺杂环栅(Gate AllAround transistor，GAA)结构是目前最受关注的一种。GAA器件具有更好的栅控特性，可以满足最尖锐的特性需求，从而适应器件尺寸缩小的需求，提高集成度。器件由于环形栅结构和纳米线沟道的特点，表现出很好的抑制短沟道效应性能。在制成水平沟道GAA器件的同时，可以注意到纳米线(NW)的排列方式决定了GAA结构存在应用垂直沟道的可能，目前已有关于掺杂源漏垂直沟道GAA器件的实验报道，相较水平沟道GAA器件，垂直沟道GAA器件的优势突出在两点：(1)可实现更高的集成度，(2)垂直沟道GAA的栅长不再由光刻能力决定，而是由栅材料的纵向厚度决定，这就可能突破集成加工的光刻极限。需要指出的是，此时单个垂直沟道GAA在栅长和栅宽(即纳米线的周长)两个维度都进入纳米尺度，而两个维度上都可以突破纳米加工的光刻极限。因此，垂直沟道GAA相较水平沟道GAA更具研发价值，也更富挑战性。
需要指出的是，垂直沟道的GAA结构具有良好的栅控能力，同样也面对着源漏设计的问题。对于传统的MOS场效应晶体管，为了抑制短沟道效应，必须采用超浅结和陡变掺杂的源/漏区，因而对热预算的要求极为苛刻。此外，纳米线的引入，使得GAA源漏设计较平面器件和多栅器件更为复杂。而High-K栅介质(介电常数K>3.9)与金属栅组合(HKMG)的热稳定问题，以及此后可能应用的SiGe、Ge和其他宽禁带材料对源漏设计同样存在热预算的需求。
发明内容
本发明的目的是提供一种结合垂直沟道和非对称肖特基势垒源/漏结构的环栅MOS场效应晶体管及其制备方法。在与现有CMOS工艺兼容并且保持了传统GAA各种优点的条件下，该结构利用非对称肖特基势垒源/漏结构减小了漏电流、简化了工艺要求，并利用垂直沟道、环形栅结构突破了集成加工光刻极限限制，提高了集成度。
本发明提供的技术方案如下：
一种结合垂直沟道和非对称肖特基势垒源/漏结构的环栅MOS晶体管，包括一个垂直方向的环状半导体沟道4，一个环状栅电极6，一个环状栅介质层5，一个源区2，一个漏区3，一个半导体衬底1；其中，源区2位于垂直沟道4的底部，与衬底1相接，漏区3位于垂直沟道4的顶部，栅介质层5和栅电极6呈环状围绕住垂直沟道4；源区2和漏区3分别与沟道4形成不同势垒高度的肖特基接触；源漏所用金属材料不同。
所述源区和漏区可为任何导电性良好的金属或金属与衬底材料形成的化合物。
本发明所述MOS晶体管的制备方法，包括以下步骤：
(1)在半导体衬底上通过半导体线条应力限制氢化或氧化工艺获取垂直纳米线；
(2)在衬底与纳米线表面沉积双层介质并光刻加工窗口；
(3)湿法腐蚀暴露源端纳米线，金属和硅固相反应(Solid Phase Reaction，SPR)形成埋源区；
(4)高密度等离子体(HDP)淀积回刻介质至填满为源区固相反应(SPR)打开的加工窗口，选择性腐蚀纳米线上介质层后淀积HKMG(High-K栅介质与金属栅组合)层，并形成栅极引线；
(5)沉积介质至将栅电极覆盖，此时沉积的介质厚度对应于MOS晶体管器件的设计栅长；
(6)选择性腐蚀High-K栅介质及栅电极层至漏极纳米线漏出；
(7)沉积介质形成栅/漏隔离，用和源区不同的金属和Si固相反应(SPR)形成漏极结构；
(8)最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得所述的MOS晶体管。
上述的制备方法中，所述步骤(1)中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅(SOI)或绝缘体上的锗(GOI)。
上述的制备方法中，所述步骤(2)中的双层介质层材料，外层选自SiNx，内层选自二氧化硅、二氧化铪或氮化铪等。
上述的制备方法中，所述步骤(3)、(7)中的SPR金属材料选自Pt、Er、Co、Ni以及其他可与衬底半导体材料通过退火形成化合物的金属；两步中，金属选自不同种。
上述的制备方法中，所述步骤(4)中的High-K栅介质与金属栅组合层材料选自典型组合HfO2/TiN，也包括其他的系列氧化物，如HfSiON、HfZrO、HfMgO、HfAlO等材料。
上述的制备方法中，所述步骤(4)(5)中的介质层材料选自二氧化硅、二氧化铪或氮化铪等。
上述的制备方法中，所述步骤(7)中的介质层材料选自二氧化硅、二氧化铪或氮化铪等。
本发明的优点和积极效果：
(1)本发明继承了传统环栅结构晶体管的优点，例如良好的栅控能力、抑制短沟效应等；继承了垂直沟道结构的优点，突破纳米加工的光刻极限，极大提高了器件的集成度。
(2)本发明采用了肖特基势垒源/漏结构代替传统PN结，在High-K栅介质与金属栅组合层形成后不再需要注入和高温退火，彻底解决热稳定问题，也免除了潜在的GAA源漏的复杂掺杂设计，是一种具有优势的源漏解决方案。
(3)本发明采用了不对称肖特基势垒源/漏结构，即源漏材料由异种金属硅化物构成，形成不同肖特基势垒高度(SBH)，这种结构通过调制源漏结SBH的配置，可以获得极小的关态电流，是一种很有价值的低功耗应用器件。
总而言之，该器件结构采用了垂直沟道结合不对称肖特基势垒源/漏结构，在继承传统GAA的优点的基础上，减小了漏电流，简化了工艺，并且提高了集成度。
附图说明
图1是本发明的垂直沟道非对称肖特基势垒源漏环栅晶体管的器件示意图；
图2是半导体线条应力限制氢化/氧化工艺获取垂直纳米线后，沿图1中AA’方向的器件剖面图；
图3是在衬底与纳米线表面沉积双层介质并光刻加工窗口后，沿图1中AA’方向的器件剖面图；
图4是湿法腐蚀衬底上介质层后进行金属和Si固相反应(SPR)形成埋源区后，沿图1中AA’方向的器件剖面图；
图5是在高密度等离子体(HDP)淀积回刻介质至填满为源区SPR打开的加工窗口，选择性腐蚀纳米线上介质层后淀积HKMG层，形成栅极引线，沿图1中AA’方向的器件剖面图；
图6是沉积介质至将栅电极覆盖后，沿图1中AA’方向的器件剖面图；
图7是选择性腐蚀High-K栅介质及栅电极层至漏极纳米线漏出，沉积介质形成栅/漏隔离后，沿图1中AA’方向的器件剖面图；
图8是金属(异于源区材料)和Si固相反应(SPR)形成漏极结构后，本发明的垂直沟道非对称肖特基势垒源漏环栅晶体管沿图1中AA’方向的器件剖面图；
图中：
1-----------半导体衬底 2-------------肖特基源区
3-----------肖特基漏区 4-------------沟道区
5-----------High-K栅介质层 6-------------Metal Gate栅电极层
7-----------二氧化硅介质层 8-------------SiNx介质层
具体实施方式
本发明提供了一种新型结构的MOS晶体管，具体为一种结合垂直沟道和非对称肖特基势垒源/漏结构的环栅MOS晶体管(如图1所示)，包括一个垂直方向的环状半导体沟道4，一个环状栅电极6，一个环状栅介质层5，一个源区2，一个漏区3，一个半导体衬底1；其中，源区2位于垂直沟道4的底部，与衬底1相接，漏区3位于垂直沟道4的顶部，栅介质层5和栅电极6呈环状围绕住垂直沟道4；源区2和漏区3分别与沟道4形成不同势垒高度的肖特基接触。
所述源区和漏区可为任何导电性良好的金属或金属与衬底材料形成的化合物，并且源漏材料不同。
本发明制备方法的具体实例包括图2至图8所示的工艺步骤：
(1)在晶向为(100)的体硅硅片硅衬底1上采用Si线条应力限制氢化或氧化工艺获取垂直Si纳米线4，直径5nm，长度100nm，如图2所示；
(2)在衬底与纳米线表面沉积双层介质7(SiO2)和8(SiNx)，围绕纳米线光刻加工窗口(包含后续电极引出图形，不需要精细尺寸加工)，纳米线上方的硬刻蚀掩蔽层保证纳米线不会受损，如图3所示；
(3)打开上层介质8(SiNx)之后，湿法腐蚀去除底层介质7(SiO2)，至衬底表面，此过程对Si材料无损伤，在保证源端部分纳米线暴露出来后，进行金属(如Ni)和硅固相反应(SPR)，在暴露Si的对应区域形成源端硅化物2。此过程中，沟道区域的纳米线有介质包裹不会受到影响，如图4所示；
(4)采用高密度等离子体(HDP)淀积回刻介质7(SiO2)至填满为源区SPR打开的加工窗口，选择性腐蚀纳米线上包裹介质8(SiNx)，之后低温原子层沉积法(ALD法)沉积HKMG材料5和6(如HfO2/TiN)，对HKMG的图形化形成了栅极的引线(无需精细尺寸加工)，HKMG厚度约为20nm，如图5所示；
(5)沉积介质7(SiO2)至将栅电极覆盖起来(HDP法沉积)，此时沉积的介质厚度50nm对应了器件的设计栅长，如图6所示；
(6)选择性腐蚀HKMG，至漏极NW露出，沉积介质7(SiO2)形成栅/漏隔离，如图7所示；
(7)再进行金属(异于源区，如Pt)和硅固相反应(SPR)并完成图形化就可以获得漏极结构3。如图8所示；
(8)最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得所述的结合垂直沟道和非对称肖特基势垒源/漏结构的环栅MOS场效应晶体管。
Claims (7)
1.一种环栅MOS晶体管的制备方法，其特征是，包括以下步骤：
(1)在半导体衬底上通过半导体线条应力限制氢化或氧化工艺获取垂直纳米线；
(2)在衬底与纳米线表面沉积双层介质并光刻加工窗口；
(3)湿法腐蚀暴露源端纳米线，金属和硅固相反应形成埋源区；
(4)高密度等离子体淀积回刻介质至填满为源区固相反应打开的加工窗口，选择性腐蚀纳米线上介质层后淀积High-K栅介质与金属栅组合层，并形成栅极引线；
(5)沉积介质至将栅电极覆盖，此时沉积的介质厚度对应于MOS晶体管器件的设计栅长；
(6)选择性腐蚀High-K栅介质及栅电极层至漏极纳米线漏出；
(7)沉积介质形成栅/漏隔离，用和源区不同的金属和Si固相反应形成漏极结构；
(8)最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化，即可制得所述的MOS晶体管。
2.如权利要求1所述的制备方法，其特征是，所述步骤(1)中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
3.如权利要求1所述的制备方法，其特征是，所述步骤(2)中的双层介质层材料，外层选自SiNx，内层选自二氧化硅、二氧化铪或氮化铪。
4.如权利要求1所述的制备方法，其特征是，所述步骤(3)和(7)中的SPR金属材料选自Pt、Er、Co、Ni以及其他可与衬底半导体材料通过退火形成化合物的金属；两步中，金属选自不同种。
5.如权利要求1所述的制备方法，其特征是，所述步骤(4)中的High-K栅介质与金属栅组合层材料选自HfO2/TiN。
6.如权利要求1所述的制备方法，其特征是，所述步骤(4)和(5)中的介质层材料选自二氧化硅、二氧化铪或氮化铪。
7.如权利要求1所述的制备方法，其特征是，所述步骤(7)中的介质层材料选自二氧化硅、二氧化铪或氮化铪。
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