CN106158958A - 具有源极/漏极覆盖层的FinFET - Google Patents
具有源极/漏极覆盖层的FinFET Download PDFInfo
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- CN106158958A CN106158958A CN201510172108.3A CN201510172108A CN106158958A CN 106158958 A CN106158958 A CN 106158958A CN 201510172108 A CN201510172108 A CN 201510172108A CN 106158958 A CN106158958 A CN 106158958A
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Classifications
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract
一种器件包括半导体衬底以及延伸至半导体衬底内的隔离区。半导体鳍位于隔离区的相对部分之间,其中,半导体鳍位于隔离区的顶面上方。栅极堆叠件与半导体鳍重叠。源极/漏极区位于栅极堆叠件的侧部上并且连接至半导体鳍。源极/漏极区包括比半导体鳍薄的内部以及位于内部外侧的外部。半导体鳍和源极/漏极区的内部具有相同的IV族半导体的组分。本发明还涉及具有源极/漏极覆盖层的FinFET。
Description
优先权声明和交叉引用
本申请与2014年8月5日提交的标题为“Nonplanar Device andStrain-Generating Channel Dielectric”的以下共同受让的美国专利申请第14/451,503号相关,其全部内容结合于此作为参考。
技术领域
本发明涉及集成电路器件,更具体地,涉及具有源极/漏极覆盖层的FinFET。
背景技术
IC材料和设计中的技术进步已经产生了数代的IC,其中每代IC都具有比上一代IC更小和更复杂的电路。功能密度(即,每一芯片面积上互连器件的数量)通常已经增加而几何尺寸(即,使用制造工艺可以制造的最小部件(或线))却已减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本而提供益处。
这种按比例缩小也增大了加工和制造IC的复杂度,并且为了继续实现这些进步,也需要IC加工和制造中的进一步发展。例如,已经引入诸如鳍式场效应晶体管(FinFET)的三维晶体管以代替平面晶体管。虽然现有的FinFET器件及其制造方法通常已经能够满足它们的预期目的,但是它们不是在所有方面都已完全令人满意。期望该领域中的改进。
发明内容
为了解决现有技术中存在的问题,本发明提供了一种器件,包括:半导体衬底;隔离区,延伸至所述半导体衬底内;半导体鳍,位于所述隔离区的相对部分之间,其中,所述半导体鳍位于所述隔离区的顶面上方;栅极堆叠件,与所述半导体鳍重叠;以及源极/漏极区,位于所述栅极堆叠件的侧部上并且连接至所述半导体鳍,其中,所述源极/漏极区包括:内部,比所述半导体鳍薄,其中,所述半导体鳍和所述源极/漏极区的所述内部具有相同的IV族半导体的组分;和外部,位于所述内部外侧。
在上述器件中,其中,所述内部的顶面低于所述半导体鳍的顶面。
在上述器件中,其中,所述源极/漏极区的所述内部的第一宽度为所述半导体鳍的第二宽度的约50%至约70%,其中,在与包括所述源极/漏极区的鳍式场效应晶体管(FinFET)的源极至漏极方向垂直的方向上测量所述第一宽度和所述第二宽度。
在上述器件中,其中,所述栅极堆叠件和所述源极/漏极区包括在n型鳍式场效应晶体管(FinFET)中,并且所述内部包括硅且不含锗,并且其中,所述外部包括硅磷。
在上述器件中,其中,所述栅极堆叠件和所述源极/漏极区包括在n型鳍式场效应晶体管(FinFET)中,并且所述内部包括硅且不含锗,并且其中,所述外部包括硅磷,其中,所述器件还包括:两个SiGeOx区,其中,所述SiGeOx区的内部与所述半导体鳍重叠。
在上述器件中,其中,所述栅极堆叠件和所述源极/漏极区包括在n型鳍式场效应晶体管(FinFET)中,并且所述内部包括硅且不含锗,并且其中,所述外部包括硅磷,其中,所述器件还包括:两个SiGeOx区,其中,所述SiGeOx区的内部与所述半导体鳍重叠,其中,所述器件还包括:硅锗区,位于所述两个SiGeOx区之间。
在上述器件中,其中,所述栅极堆叠件和所述源极/漏极区包括在p型鳍式场效应晶体管(FinFET)中,并且所述内部包括具有第一锗百分比的硅锗,并且所述外部包括具有大于所述第一锗百分比的第二锗百分比的硅锗。
在上述器件中,其中,所述栅极堆叠件和所述源极/漏极区包括在p型鳍式场效应晶体管(FinFET)中,并且所述内部包括具有第一锗百分比的硅锗,并且所述外部包括具有大于所述第一锗百分比的第二锗百分比的硅锗,其中,所述器件还包括:硅层,位于所述源极/漏极区的所述内部下面;以及附加硅锗层,位于所述硅层下面并且位于所述半导体衬底上面。
根据本发明的另一实施例,提供了一种器件,包括:硅衬底;隔离区,延伸至所述硅衬底内;以及p型鳍式场效应晶体管(FinFET),包括:硅锗鳍,所述硅锗鳍包括中间部分和位于所述中间部分的相对两侧上的端部,其中,所述中间部分的顶面高于所述端部的顶面,并且其中,所述硅锗鳍具有第一锗百分比;栅极堆叠件,与所述硅锗鳍的所述中间部分重叠;和源极/漏极区,包括作为内部的所述硅锗鳍的所述端部中的一个以及位于所述内部外侧的硅锗区,其中,所述硅锗区具有高于所述第一锗百分比的第二锗百分比。
在上述器件中,其中,所述源极/漏极区还包括位于所述硅锗区外侧的附加硅锗区,其中,所述附加硅锗区具有高于所述第二锗百分比的第三锗百分比。
在上述器件中,其中,所述硅锗鳍延伸至低于所述隔离区的顶面的水平面,并且所述器件还包括:硅层,位于所述硅锗鳍下面;附加硅锗层,位于所述硅层下面;以及硅条,位于所述附加硅锗层下面,其中,所述硅条连续地连接至所述硅衬底。
在上述器件中,其中,所述硅锗鳍的所述端部比所述硅锗鳍的所述中间部分薄。
在上述器件中,其中,所述硅锗鳍的所述端部比所述硅锗鳍的所述中间部分薄,其中,所述硅锗鳍的所述端部的第一宽度小于所述硅锗鳍的所述中间部分的第二宽度,其中,在与包括所述源极/漏极区的鳍式场效应晶体管(FinFET)的源极至漏极方向垂直的方向上测量所述第一宽度和所述第二宽度。
在上述器件中,其中,所述硅锗鳍的所述端部比所述硅锗鳍的所述中间部分薄,其中,所述硅锗鳍的所述端部的第一宽度小于所述硅锗鳍的所述中间部分的第二宽度,其中,在与包括所述源极/漏极区的鳍式场效应晶体管(FinFET)的源极至漏极方向垂直的方向上测量所述第一宽度和所述第二宽度,其中,所述第一宽度介于所述第二宽度的约50%和约70%之间。
根据本发明的又一实施例,提供了一种方法,包括:使半导体条的相对两侧上的隔离区凹进以形成半导体鳍,其中,所述半导体鳍位于所述隔离区的顶面上方;在所述半导体鳍的中间部分的顶面和侧壁上形成栅极堆叠件;减薄所述半导体鳍的端部;以及实施外延以在所述半导体鳍的减薄的端部上生长半导体区,其中,所述半导体鳍的所述减薄的端部和所述半导体区组合形成鳍式场效应晶体管(FinFET)的源极/漏极区。
在上述方法中,其中,在形成所述栅极堆叠件之后实施所述减薄。
在上述方法中,其中,所述FinFET是n型FinFET,并且所述半导体鳍是不含锗的硅鳍,并且其中,所述外延包括生长硅磷区。
在上述方法中,其中,所述半导体条包括与硅锗条重叠的硅条,并且所述方法还包括:对所述硅锗条的外部实施氧化,其中,在所述氧化中,所述硅锗条的内部中的锗浓缩。
在上述方法中,其中,所述FinFET是p型FinFET,并且所述半导体鳍包括具有第一锗百分比的硅锗鳍,并且其中,所述外延包括生长具有高于所述第一锗百分比的第二锗百分比的硅锗硼区。
在上述方法中,其中,所述FinFET是p型FinFET,并且所述半导体鳍包括具有第一锗百分比的硅锗鳍,并且其中,所述外延包括生长具有高于所述第一锗百分比的第二锗百分比的硅锗硼区,其中,还包括,在使所述隔离区凹进之前:蚀刻所述隔离区之间的硅条的顶部以形成凹槽;以及在所述凹槽中生长硅锗条,从所述硅条的底部生长所述硅锗条,其中,所述硅锗条具有所述第一锗百分比。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图4A、图5至图10A以及图11至图12A是在示例性鳍式场效应晶体管(FinFET)的制造中的中间阶段的立体图,而图4B、图10B和图12B至图12C是在示例性鳍式场效应晶体管(FinFET)的制造中的中间阶段的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作相应的解释。
在论述示出的实施例之前,将大体上讨论本发明的特征和方面。通常地,本发明涉及但不限于包括P型金属氧化物半导体(PMOS)FinFET器件和N型金属氧化物半导体(NMOS)FinFET器件的互补金属氧化物半导体(CMOS)器件。根据各个示例性实施例提供了形成CMOS器件的方法。示出并且讨论了形成示例性FinFET的中间阶段,包括实施例的变化。贯穿各个视图和说明性实施例,相同的参考标号用于表示相同的元件。
图1示出了包括衬底20以及位于衬底20上方的半导体层22和24的晶圆10。根据一些实施例,衬底20包括晶体硅并且可以不含锗。在一些实施例中,晶圆10是块状的单晶半导体晶圆。在其他实施例中,晶圆10包括如本领域已知的绝缘体上硅(SOI)晶圆。半导体层22包括硅锗(SiGe)。根据本发明的一些实施例,半导体层22中的锗百分比介于约30%和约80%的范围内。半导体层22的厚度可以介于约20nm和约90nm的范围内。根据一些实施例,半导体层24可以是不含锗的硅层。在可选实施例中,半导体层24可以包括硅磷(SiP)。
晶圆10包括说明性的区域100和200。区域100是n型FinFET区域,其中将形成n型FinFET。区域200是p型FinFET区域,其中将形成p型FinFET。虽然贯穿本发明中的图将区域100和200示出为彼此分隔开,但是区域100和200是同一晶圆10的部分并且可以位于同一芯片中。例如,区域100和200中示出的衬底20是同一连续的衬底的部分,并且半导体层22和24也是同一连续的层的部分。
参照图2,层22和24经受图案化工艺以形成延伸至晶圆10内的多个沟槽26。沟槽26将半导体衬底20以及半导体层22和24的一些未图案化的部分限定为分别位于区域100和200中的多个半导体条128和228。半导体条128包括图案化的衬底20的部分120、图案化的半导体层22的部分122和图案化的半导体层24的部分124。半导体条228包括图案化的衬底20的部分220、图案化的半导体层22的部分222和图案化的半导体层24的部分224。根据一些实施例,半导体条128和228具有介于约4nm和约10nm之间的相应的宽度。贯穿说明书,条120、220、124和224称为硅条,而条122和222称为SiGe条。
图3示出了硬掩模30的形成以及随后的氧化工艺。如图3所示,硬掩模30形成在半导体条128和228的顶面和侧壁上并且覆盖半导体衬底20的暴露的顶面(即,沟槽26的相应底部)。此外,硬掩模30形成在n型FinFET区域100和p型FinFET区域200中。接下来,实施图案化工艺以从半导体条128的中间部分去除硬掩模30的部分。半导体条128的相对端部上的硬掩模30的部分保持完整。此外,未图案化p型FinFET区域200中的硬掩模30的部分。如图3所示,区域200中的整个鳍228均被覆盖,但是区域100中的鳍128的中间部分未被覆盖。
硬掩模30形成为共形层,该共形层具有厚度彼此相对接近的水平部分和垂直部分。根据一些实施例,硬掩模30包括氮化硅、碳化硅、氮氧化硅、氮化钛、氮化钽或者相对于半导体条128和228以及相对于氧化硅具有高蚀刻选择性的其他材料。
接下来,实施氧化,从而使得氧化未由硬掩模30覆盖的SiGe条122(图2)的中间部分以形成氧化硅锗(SiGeOx)区132。SiGe条222以及更具体地SiGe条122的端部受到硬掩模30的保护,并且因此不被氧化。在氧化之后,去除硬掩模30,并且图4A中示出了产生的结构,图4A示出,SiGeOx区132位于半导体条128的中间。
图4B示出了条128中的一个的截面图,其中,从图4A中的包含线4B-4B的垂直面获得该截面图。为了清楚的目的,示出了单个半导体条128。如图4B所示,SiGe条122的内部保持未被氧化。也可以部分地氧化未由硬掩模30(图3)覆盖的硅条120和124的中间部分。然而,SiGe条122的中间部分的氧化速率比硅条120和124的氧化高得多(有时高30倍)。因此在硅条120和124的表面上产生的氧化物(未示出)非常薄(其可以具有小于约的厚度),并且因此在本文中未示出。例如,可以通过炉氧化来实施氧化,例如,通过将晶圆10暴露于具有介于约400℃和约600℃之间的氧化温度的氧气环境中。氧化工艺的持续时间可以介于约20分钟和约40分钟的范围内。氧化工艺的持续时间取决于温度。较低的温度需要较长的氧化持续时间,反之亦然。可选地,可以使用低温下(例如,介于约20℃和80℃)的化学氧化方法来实施氧化,例如,将过氧化氢(H2O2)溶液用作氧化剂。产生的SiGeOx区132可以包括形成在剩余的SiGe条122的相对两侧上的两个部分。根据一些实施例,SiGeOx区132具有介于约3nm和约10nm之间的相应的厚度。
虽然预期受到任何特定的以下理论的约束,但是认为,在氧化工艺期间,SiGe条122中的锗原子趋于从SiGeOx区132向内迁移并且朝向相应的SiGe条122的中心(内部)迁移,从而导致SiGe条122的内部的锗浓缩。结果,SiGe条122的剩余的部分(即,未氧化部分)的锗浓度高于SiGe条222(图4A)中的相应的锗浓度。
由于氧化工艺,SiGeOx区132的体积扩展为大于生成SiGeOx区132的SiGe条122的部分的体积。因此,材料的膨胀导致生成横向拉伸应变以驱使源极/漏极区154(图12A)彼此分离。也生成垂直应变以向上推硅条124,其中硅条124将用于形成产生的n型FinFET的沟道。因此,SiGe条122的氧化有利地使得在产生的n型FinFET中生成期望的应变。相反,掩蔽区域200中的SiGe条222以防止在产生的p型FinFET中形成不期望的应变。
参照图5,在半导体条128和228的顶面和侧壁上分别形成介电衬垫134和234。此外,介电衬垫134和234延伸至SiGeOx区132(图4A)的侧壁上并且与SiGeOx区132的侧壁接触。根据本发明的一些实施例,介电衬垫134和234由氮化硅、氧化铝(Al2O3)、氮氧化硅、碳化硅、它们的组合或它们的多层形成。在一些实施例中,例如,可以使用相同的工艺和材料在区域100和200中同时形成介电衬垫134和234。介电衬垫134和234形成为共形层,该共形层具有厚度彼此相等或基本接近(例如,厚度差小于约20%)的垂直部分和水平部分。介电衬垫134和234的厚度可以介于约2nm和约6nm的范围内。
接下来,在区域100和200中的沟槽26中形成隔离区。产生的隔离区136和236在图6中示出并且在整个说明书中也称为浅沟槽隔离(STI)区136和236。在STI区136和236的形成中,首先用介电材料填充沟槽26(图5)。例如,可以使用选自旋涂、可流动化学汽相沉积(FCVD)等的方法形成介电材料。介电材料可以包括如本领域已知的高度可流动材料。根据可选实施例,使用诸如高密度等离子体化学汽相沉积(HDPCVD)和高高宽比工艺(HARP)的沉积方法来沉积介电材料。
在一些实施例中,然后可以对晶圆10实施退火步骤,由此使介电材料固化。例如,退火可以包括使用原位蒸汽生成(ISSG)的蒸汽退火,其中氢气(H2)和氧气(O2)的组合气体用于生成蒸汽。
在形成介电材料之后,实施化学机械抛光(CMP)以去除位于介电衬垫134和234的顶面部分上方的介电材料的过量部分,并且因此形成STI区136和236。根据本发明的一些实施例,介电衬垫134和234的顶面部分用作CMP停止层。介电材料的剩余部分形成STI区136和236。例如,STI区136和236可以包括氧化硅,但是也可以使用其他介电材料。STI区136和236的顶面可以彼此基本平齐并且与介电衬垫134和234的顶面平齐。
还参照图6,形成并且图案化硬掩模138。在示出的实施例中,由硬掩模138覆盖n型FinFET区域100中的结构,并且使得p型FinFET区域200中的结构暴露。在图6和随后的图中,为了示出另外的隐藏的部件,从图中省略诸如STI区136和236的前面的部件的一些部分,从而使得可以示出另外的部件。将理解,这些部件的省略部分仍然存在。根据本发明的一些实施例,硬掩模138由氮化硅、氧化硅或其他合适的材料形成。此外,在一些实施例中,硬掩模138可以由与介电衬垫134和234的材料不同的材料形成,从而使得可以在不蚀刻硬掩模138的情况下蚀刻介电衬垫134和234,反之亦然。
图7示出了硅条224的凹进,因此在区域200中形成凹槽240。作为实例,可以使用诸如氢氧化钾(KOH)或四甲基氢氧化铵(TMAH)的湿蚀刻来实施蚀刻。根据本发明的一些实施例,在暴露SiGe条222之前停止蚀刻。因此,在蚀刻之后,硅条224的底部仍然覆盖SiGe条222。应该理解,虽然剩余的硅条224示出为具有平坦的顶面,但是在可选实施例中,该顶面也可以形成V形。根据其他实施例,在蚀刻之后,去除硅条224,并且暴露SiGe条222。硬掩模138确保在该工艺期间不蚀刻条128。
接下来,如图8所示,在凹槽240(图7)中外延生长SiGe条242。因此,取决于实施例,SiGe条242生长在硅条224或SiGe条222上方并且与硅条224或SiGe条222接触。根据本发明的一些实施例,SiGe条242具有介于约30%和约50%的范围内的第一锗(原子)百分比。SiGe可以外延生长至与STI区236的顶面齐平,或者可以生长至高于STI区236的顶面的水平面,并且然后CMP工艺用于平坦化SiGe的顶面与STI区236的顶面。外延生长的SiGe材料的剩余部分形成SiGe条242。
接下来,去除硬掩模138,随后使STI区136和236凹进。图9中示出了产生的结构。在区域100中,硅条124具有高于剩余的STI区136的顶面的顶部,其中硅条124的顶部此后称为半导体鳍(硅鳍)144。根据本发明的一些实施例,剩余的STI区136的顶面与由图9中的介电衬垫134覆盖的SiGeOx区132(图4A和图4B)的顶端齐平或高于SiGeOx区132的顶端。
在使STI区136凹进的同时,也使STI区236凹进。SiGe条242具有高于剩余的STI区236的顶面的顶部,其中SiGe条242的顶部此后称为半导体鳍(SiGe鳍)244。根据一些实施例,半导体鳍144和244具有介于约20nm和约40nm之间的高度。剩余的STI区236的顶面可以与剩余的硅条224(如果存在)的顶端齐平或高于剩余的硅条224的顶端,或者如果硅条224在先前步骤中被完全去除,则剩余的STI区236的顶面可以与SiGe条222的顶面齐平或高于SiGe条222的顶面。
如图9所示,暴露介电衬垫134和234的一些部分。然后去除介电衬垫134和234的这些部分。接下来,如图10A所示,形成伪栅极堆叠件146和246以分别覆盖半导体鳍144和244(图9)的中间部分。未覆盖半导体鳍144和244的端部。根据一些实施例,栅极堆叠件146包括伪栅极148以及掩模层150和/或152,并且栅极堆叠件246包括伪栅极248以及掩模层250和/或252。根据一些实施例,伪栅极148和248可以由多晶硅形成,但是可以使用其他材料。在一些示例性实施例中,掩模层150和250由氮化硅形成,并且掩模层152和252由氧化硅形成。虽然在图9中未示出,但是可以在伪栅极148和248下面形成诸如氧化硅层的伪栅极电介质。伪栅极148和248分别形成在半导体鳍144和244(图9)的顶面和侧壁上。此外,栅极堆叠件146和246可以分别包括栅极间隔件153和253,栅极间隔件153和253分别形成在伪栅极148和248的侧壁上。
图10A也示出了区域100中的源极和漏极区(此后称为源极/漏极区)154的形成以及区域200中的源极/漏极区254的形成。源极/漏极区154包括作为中心部分的硅条124以及位于硅条124的外部的外延区156。源极/漏极区254包括作为中心部分的SiGe条242以及位于SiGe条242的外部的外延区256。参照图10B讨论了源极/漏极区154和254的形成。
图10B包括源极/漏极区154和254的截面图,其中,从图10A中的包含线10BN-10BN的垂直面获得源极/漏极区154的截面图,并且从图10A中的包含线10BP-10BP的垂直面获得源极/漏极区254的截面图。
在源极/漏极区154的形成中,首先减薄半导体鳍144,在一些实施例中,半导体鳍144包括硅条124。例如,该减薄可以包括湿蚀刻,并且蚀刻剂可以包括HF、过氧化氢(H2O2)和醋酸(CH3COOH)的溶液。虚线158示出了在减薄之前的硅条124的边缘和顶面的位置。由于减薄,减薄的硅条124(鳍144)的宽度从减薄之前的原始宽度W2减小至减薄之后的宽度W1。根据一些实施例,宽度W1介于宽度W2的约50%和约70%之间,但是宽度W1可以更大或更小。可以从硅条124的中间高度测量宽度W1和W2。如图10B所示,在STI区136的顶面之上的1/2高度H处测量宽度W1和W2。也如图10B所示,原始半导体鳍144的虚线侧壁从STI区136的侧壁延伸。然而,朝着硅条124的中心线160使减薄的硅条124的侧壁124A凹进。由于减薄,也降低了硅条124的顶面。
从减薄的硅条124外延生长n型外延区156。根据一些实施例,n型外延区156包括SiP,其中,当生长n型外延区156时,可以原位掺杂磷。也可以使用除了磷之外的其他n型杂质(诸如砷)。由于n型外延区156的晶格常数小于下面的SiGe条122的晶格常数,通过源极/漏极区154在相应的n型FinFET的沟道区中生成拉伸应变。有利地,通过在外延生长工艺之前减薄半导体条124,产生的n型外延区156的轮廓更像椭圆形而不是金刚石形。根据一些示例性实施例,产生的源极/漏极区154中的磷的浓度介于约5E20/cm3和约2E21/cm3的范围内。此外,当在图1和图2中示出的步骤中形成硅条124时,硅条124可以不掺杂磷。然而,在图10A和图10B中示出的步骤之后的热工艺中,磷扩散至减薄的硅条124内。位于SiP区156和减薄的硅条124之间的界面处的磷浓度可能或可能不存在显著下降。而且,可以生成掺杂浓度的梯度,其中,邻接SiP区156的硅条124的外部比硅条124的内部具有更高的n型杂质(磷)浓度。n型掺杂浓度可以从减薄的硅条124的内部区至外部区逐渐并且连续地增大。
也如图10B所示,在源极/漏极区254的形成中,首先减薄半导体鳍244,在一些实施例中,半导体鳍244包括SiGe条242。在一些实施例中,该减薄可以包括湿蚀刻,并且蚀刻剂可以包括包含NH3OH和H2O2的溶液。在可选实施例中,例如,蚀刻剂包括HF、过氧化氢(H2O2)和醋酸(CH3COOH)。虚线258示出了在减薄之前的SiGe条242的边缘和顶面的位置。由于减薄,减薄的半导体鳍244的宽度从减薄之前的原始宽度W2’减小至宽度W1’。根据一些实施例,宽度W1’介于宽度W2’的约50%和约70%之间,但是宽度W1’可以更大或更小。可以从SiGe条242的中间高度测量宽度W1’和W2’。如图10B所示,原始半导体鳍244的虚线侧壁258从STI区236的侧壁延伸。然而,使减薄的SiGe条242的侧壁242A朝着SiGe条242的中心线260凹进。由于减薄,也降低了减薄的SiGe条242的顶面。
从减薄的SiGe条242外延生长p型外延区256。根据一些实施例,p型外延区256包括SiGeB,其中,当生长p型外延区256时,可以原位掺杂硼。也可以使用除了硼之外的其他p型杂质(诸如铟)。由于p型外延区256的晶格常数大于下面的Si条224和/或SiGe条222的晶格常数,通过源极/漏极区254在相应的p型FinFET的沟道区中生成压缩应变。根据一些示例性实施例,产生的源极/漏极区254中的p型杂质(诸如硼)的浓度介于约5E20/cm3和约2E21/cm3的范围内。此外,当外延生长SiGe条242时,可以不用p型杂质(诸如硼)掺杂SiGe条242。然而,在图10A和图10B中的步骤之后的热工艺中,硼扩散至减薄的SiGe条242内。而且,可以形成掺杂浓度的梯度,其中,邻接SiGeB区256的SiGe条242的外部比内部具有更高的p型杂质浓度。p型掺杂浓度可以从减薄的SiGe条242的内部区至外部区逐渐地增大。
SiGeB区256可以是具有比SiGe条242的第一锗百分比高的高锗百分比的均质区。SiGeB区256的锗百分比可以介于约70%和约100%(这是指没有硅的锗)的范围内。根据可选实施例,SiGeB区256包括具有比SiGe条242的第一锗百分比高的第二锗百分比的SiGeB区256A。第二锗百分比可以介于约60%和约80%的范围内。在SiGeB区256A外部形成SiGeB区256B,SiGeB区256B具有比SiGeB区256A的第二锗百分比高的第三锗百分比。根据一些实施例,第三锗百分比可以介于约80%和约100%的范围内。SiGeB区256、256A和256B可以具有梯度锗百分比,其中外部比内部具有越来越高的锗百分比。
图11示出了在形成层间电介质(ILD)62之后的结构的立体图。ILD 62包括诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等的介电材料。可以实施CMP以使ILD 62的顶面与伪栅极堆叠件146和246(图10A)的顶面齐平。接下来,如图11所示,通过蚀刻步骤去除伪栅极堆叠件146和246,从而使得在ILD 62中形成凹槽164和264。凹槽164和264分别位于区域100和200中。因此,半导体鳍144和244的中间部分分别暴露于凹槽164和264。
图12A和图12B示出了替代栅极165和265的形成,替代栅极165和265包括栅极电介质166和266以及栅电极168和268。由此形成FinFET 170和270。图12A示出了立体图。图12B示出了从与FinFET 170和270的源极至漏极方向垂直的平面获得的截面图。如图12B所示,硅条124包括与替代栅极堆叠件165重叠的部分124-1(其为鳍144的部分)以及用作源极/漏极区154的内部的减薄的部分124-2。例如,部分124-1和124-2具有诸如硅的相同的IV族半导体元素的组分。此外,减薄的部分124-2的顶面低于未减薄的部分124-1的顶面。
SiGe条242包括与替代栅极堆叠件265重叠的部分242-1以及用作源极/漏极区254的内部的减薄的部分242-2。例如,部分242-1和242-2具有诸如硅和锗的相同的IV族半导体元素的组分,其中部分242-1中的锗百分比和硅百分比等于部分242-2中的相应的锗百分比和硅百分比。贯穿说明书,当两个区域称为具有相同的IV族半导体元素的组分时,这两个区域具有相同的硅百分比和相同的锗百分比。此外,减薄的部分242-2的顶面低于未减薄的部分242-1的顶面。图12B中也示出了硅化物区172和272以及源极/漏极接触插塞174和274。
图12C示出了FinFET 170和270的截面图,其中,横切替代栅极165和265并且在垂直于源极至漏极方向的方向上获得该截面图。如图12C所示,SiGeOx区132具有与硅条124重叠的一些部分。
本发明的实施例具有一些有利特征。源极/漏极区的形成包括减薄、但不完全去除半导体鳍的原始部分,以及然后在减薄的半导体鳍上外延生长外延区。这具有保持沟道区中的应变的有利特征。作为比较,如果在重新生长源极/漏极区之后完全去除半导体鳍的原始部分,则可以使应变松弛。另一方面,如果在生长外延区之前不减薄原始半导体鳍,则源极/漏极区的相应的n型或p型掺杂剂不能在整个源极/漏极区中有效地扩散。
根据本发明的一些实施例,一种器件包括半导体衬底以及延伸至半导体衬底内的隔离区。半导体鳍位于隔离区的相对部分之间,其中,半导体鳍位于隔离区的顶面上方。栅极堆叠件与半导体鳍重叠。源极/漏极区位于栅极堆叠件的侧部上并且连接至半导体鳍。源极/漏极区包括比半导体鳍薄的内部以及位于内部外侧的外部。半导体鳍和源极/漏极区的内部具有相同的IV族半导体的组分。
根据本发明的可选实施例,一种器件包括硅衬底、延伸至硅衬底内的隔离区以及p型FinFET。p型FinFET包括硅锗鳍,硅锗鳍包括中间部分和位于中间部分的相对两侧上的端部。中间部分的顶面高于端部的顶面。硅锗鳍具有第一锗百分比。p型FinFET还包括与硅锗鳍的中间部分重叠的栅极堆叠件以及源极/漏极区。源极/漏极区包括作为内部的硅锗鳍的端部的一个以及位于内部外侧的硅锗区。硅锗区具有高于第一锗百分比的第二锗百分比。
根据本发明的又可选实施例,一种方法包括:使半导体条的相对两侧上的隔离区凹进以形成半导体鳍,其中,半导体鳍位于隔离区的顶面上方;在半导体鳍的中间部分的顶面和侧壁上形成栅极堆叠件;减薄半导体鳍的端部;以及实施外延以在半导体鳍的减薄的端部上生长半导体区。半导体鳍的减薄的端部和半导体区组合形成FinFET的源极/漏极区。取决于FinFET的类型,半导体区包括硅磷或硅锗硼。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种器件,包括:
半导体衬底;
隔离区,延伸至所述半导体衬底内;
半导体鳍,位于所述隔离区的相对部分之间,其中,所述半导体鳍位于所述隔离区的顶面上方;
栅极堆叠件,与所述半导体鳍重叠;以及
源极/漏极区,位于所述栅极堆叠件的侧部上并且连接至所述半导体鳍,其中,所述源极/漏极区包括:
内部,比所述半导体鳍薄,其中,所述半导体鳍和所述源极/漏极区的所述内部具有相同的IV族半导体的组分;和
外部,位于所述内部外侧。
2.根据权利要求1所述的器件,其中,所述内部的顶面低于所述半导体鳍的顶面。
3.根据权利要求1所述的器件,其中,所述源极/漏极区的所述内部的第一宽度为所述半导体鳍的第二宽度的约50%至约70%,其中,在与包括所述源极/漏极区的鳍式场效应晶体管(FinFET)的源极至漏极方向垂直的方向上测量所述第一宽度和所述第二宽度。
4.根据权利要求1所述的器件,其中,所述栅极堆叠件和所述源极/漏极区包括在n型鳍式场效应晶体管(FinFET)中,并且所述内部包括硅且不含锗,并且其中,所述外部包括硅磷。
5.根据权利要求4所述的器件,还包括:
两个SiGeOx区,其中,所述SiGeOx区的内部与所述半导体鳍重叠。
6.根据权利要求5所述的器件,还包括:
硅锗区,位于所述两个SiGeOx区之间。
7.根据权利要求1所述的器件,其中,所述栅极堆叠件和所述源极/漏极区包括在p型鳍式场效应晶体管(FinFET)中,并且所述内部包括具有第一锗百分比的硅锗,并且所述外部包括具有大于所述第一锗百分比的第二锗百分比的硅锗。
8.根据权利要求7所述的器件,还包括:
硅层,位于所述源极/漏极区的所述内部下面;以及
附加硅锗层,位于所述硅层下面并且位于所述半导体衬底上面。
9.一种器件,包括:
硅衬底;
隔离区,延伸至所述硅衬底内;以及
p型鳍式场效应晶体管(FinFET),包括:
硅锗鳍,所述硅锗鳍包括中间部分和位于所述中间部分的相对两侧上的端部,其中,所述中间部分的顶面高于所述端部的顶面,并且其中,所述硅锗鳍具有第一锗百分比;
栅极堆叠件,与所述硅锗鳍的所述中间部分重叠;和
源极/漏极区,包括作为内部的所述硅锗鳍的所述端部中的一个以及位于所述内部外侧的硅锗区,其中,所述硅锗区具有高于所述第一锗百分比的第二锗百分比。
10.一种方法,包括:
使半导体条的相对两侧上的隔离区凹进以形成半导体鳍,其中,所述半导体鳍位于所述隔离区的顶面上方;
在所述半导体鳍的中间部分的顶面和侧壁上形成栅极堆叠件;
减薄所述半导体鳍的端部;以及
实施外延以在所述半导体鳍的减薄的端部上生长半导体区,其中,所述半导体鳍的所述减薄的端部和所述半导体区组合形成鳍式场效应晶体管(FinFET)的源极/漏极区。
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