CN103579176B - 半导体器件的接触结构 - Google Patents

半导体器件的接触结构 Download PDF

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Publication number
CN103579176B
CN103579176B CN201210424958.4A CN201210424958A CN103579176B CN 103579176 B CN103579176 B CN 103579176B CN 201210424958 A CN201210424958 A CN 201210424958A CN 103579176 B CN103579176 B CN 103579176B
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strain gauge
dielectric layer
semiconductor device
gauge material
layer containing
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CN103579176A (zh
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万幸仁
叶凌彦
施启元
陈彦友
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

本发明涉及半导体器件。一种用于半导体器件的接触结构的示例性结构包括：衬底，该衬底包括主表面和主表面之下的腔；腔中的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数；位于应变材料上方的含Ge介电层；以及位于含Ge介电层上方的金属层。

Description

半导体器件的接触结构
技术领域
本发明涉及集成电路制造，具体来说，指具有接触结构的半导体器件。
背景技术
在追求更高的器件密度、更高的性能以及更低的成本的过程中，随着半导体产业已经发展到纳米技术工艺节点，来自制造和设计问题两方面的挑战引起三维设计诸如鳍状场效应晶体管(FinFET)的发展。示例性的FinFET是用从衬底延伸的薄的垂直“鳍”(或鳍结构)(例如通过蚀刻掉衬底的硅层的一部分而形成)制造的。在该垂直鳍中形成FinFET的沟道。栅极形成(例如覆盖)在鳍上方。沟道的两侧都具有栅极允许从两侧对沟道栅极控制。此外，利用选择性生长的硅锗(SiGe)的FinFET的源极/漏极(S/D)部分中的应变材料可以用于提高载流子移动率。
然而，在互补金属氧化物半导体(CMOS)制造中实施这些部件和工艺存在挑战。例如，应变材料上的硅化物的形成引起FinFET的源极/漏极区的高接触电阻，从而使器件性能退化。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种用于半导体器件的接触结构，包括：衬底，包括主表面和位于所述主表面之下的腔；所述腔中的应变材料，其中所述应变材料的晶格常数不同于所述衬底的晶格常数；含Ge介电层，位于所述应变材料上方；以及金属层，位于所述含Ge介电层上方。
在上述接触结构中，其中，所述应变材料包含SiGe或SiGeB。
在上述接触结构中，其中，所述含Ge介电层具有介于约1nm至约10nm范围内的厚度。
在上述接触结构中，其中，所述含Ge介电层包含GeNx。
在上述接触结构中，其中，所述含Ge介电层包含GeOx或GeOxNy。
在上述接触结构中，其中，所述金属层包含Co、Ni或TiN。
在上述接触结构中，其中，所述金属层具有介于约5nm至约10nm范围内的厚度。
根据本发明的另一方面，还提供了一种p型金属氧化物半导体场效应晶体管(pMOSFET)，包括：衬底，包括主表面和位于所述主表面之下的腔；栅极堆叠件，位于所述衬底的主表面上；浅沟槽隔离(STI)区，设置在所述栅极堆叠件的一侧上，其中所述STI区位于所述衬底内；以及接触结构，分布在所述栅极堆叠件和所述STI区之间，其中所述接触结构包括：所述腔中的应变材料，其中所述应变材料的晶格常数不同于所述衬底的晶格常数；位于所述应变材料上方的含Ge介电层；以及位于所述含Ge介电层上方的金属层。
在上述pMOSFET中，其中，所述应变材料包含SiGe或SiGeB。
在上述pMOSFET中，其中，所述含Ge介电层具有介于约1nm至约10nm范围内的厚度。
在上述pMOSFET中，其中，所述含Ge介电层包含GeNx。
在上述pMOSFET中，其中，所述含Ge介电层包含GeOx或GeOxNy。
在上述pMOSFET中，其中，所述金属层包含Co、Ni或TiN。
在上述pMOSFET中，其中，所述金属层具有介于约5nm至约10nm范围内的厚度。
根据本发明的又一方面，还提供了一种制造半导体器件的方法，包括：提供衬底，所述衬底包括主表面和位于所述主表面之下的腔；在所述腔中外延生长应变材料，其中所述应变材料的晶格常数不同于所述衬底的晶格常数；在所述应变材料上方外延生长Ge层；处理所述Ge层以在所述应变材料上方形成含Ge介电层；以及在所述含Ge介电层上方形成金属层。
在上述方法中，还包括：在所述应变材料上方外延生长所述Ge层之前修剪所述应变材料。
在上述方法中，还包括：在所述应变材料上方外延生长所述Ge层之前修剪所述应变材料，其中，使用HCl作为蚀刻气体执行修剪所述应变材料的步骤。
在上述方法中，其中，通过将所述Ge层暴露于包含N2、NH3、H2O、O2或O3的蒸汽来执行处理所述Ge层的步骤。
在上述方法中，其中，通过等离子体掺杂或离子注入执行处理所述Ge层的步骤。
在上述方法中，其中，通过CVD、ALD或溅射执行在所述介电层上方形成金属层的步骤。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1是根据本发明的各方面示出制造半导体器件的接触结构的方法的流程图；
图2A-12是根据本发明的各方面的处于各个制造阶段的包含接触结构的半导体器件的透视图和截面图。
具体实施方式
应当了解，为了实施本发明的不同部件，以下公开内容提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不打算限定。再者，在下面的描述中第一部件在第二部件上或者上方的形成可以包括其中第一和第二部件以直接接触形成的实施例，并且也可以包括其中可以形成介入第一和第二部件中的额外的部件，使得第一和第二部件不直接接触的实施例。此外，在各个实例中本发明可能重复参考编号/或字母。该重复是为了简明和清楚的目的并且它本身并不表示所论述的各个实施例和/或配置之间的关系。
参考图1，示出根据本发明的各方面制造半导体器件的接触结构的方法100的流程图。方法100开始于步骤102，其中提供衬底，该衬底包括主要表面和主要表面下方的腔。方法100继续步骤104，其中在腔中外延生长应变材料，其中应变材料的晶格常数不同于衬底的晶格常数。方法100继续步骤106，其中在应变材料上方外延生长Ge层。方法100继续步骤108，其中处理Ge层以在应变材料上方形成含Ge的介电层。方法100继续步骤110，其中在含Ge的介电层上方形成金属层。以下论述示出根据图1的方法100可制造的半导体器件的实施例。
图2A-图12是根据本发明的各种实施例的处于制造的各个阶段的包含接触结构230的半导体器件200的透视图和截面图。诸如本文中所描述的那些实施例涉及鳍状场效应晶体管(FinFET)。该FinFET指任何以鳍为基础的多栅极晶体管。在一些可选的实施例中，诸如本文中所描述的那些实施例涉及平面金属氧化物半导体场效应晶体管(平面MOSFET)。半导体器件200可以被包括在微处理器、存储单元和/或其他集成电路(IC)中。
需要注意的是，在一些实施例中，图1中提到的步骤的实施并不产生完整的半导体器件200。可以使用互补金属氧化物半导体(CMOS)工艺流程制造完整的半导体器件200。因此，应该理解，可以在图1的方法100之前、期间和/或之后提供额外的工艺，并且本文中仅简略地描述一些其他的实施例。而且，为了更好地理解本发明的构思，对图2A至图12作了简化。例如，尽管附图示出半导体器件200，但应该理解，IC可以包括若干其他的器件，这些器件包含电阻器、电容器、电感器、保险丝等。
参考图2A和图2B以及图1的步骤102，提供衬底202。图2A是根据实施例处于制造的其中一个阶段的具有衬底202的半导体器件200的透视图，并且图2B是沿着图2A的线a-a获得的半导体器件200的截面图。在至少一个实施例中，衬底202包括晶体硅衬底(例如，晶圆)。取决于设计要求(例如，p型衬底或n型衬底)，衬底202可以包括各种掺杂区。在一些实施例中，掺杂区可以掺杂p型或n型掺杂物。例如，掺杂区可以掺杂诸如硼或BF2的p型掺杂物；诸如磷或砷的n型掺杂物，和/或它们的组合。可以配置掺杂区用于n型MOSFET(nMOSFET)，或可选地配置用于p型MOSFET(pMOSFET)。
在一些可选的实施例中，衬底202可以由诸如金刚石或锗的一些其他合适的元素半导体；诸如砷化镓、碳化硅、砷化铟或磷化铟的合适的化合物半导体；或诸如碳化硅锗、磷化砷镓或磷化铟镓的合适的合金半导体制成。而且衬底202可以包括外延层(epi层)(可以应变用于性能提高)，和/或可以包括绝缘体上硅(SOI)结构。
在一个实施例中，垫层204a和掩模层204b形成在半导体衬底202的主要表面202s上。垫层204a可以是薄膜，该薄膜包括例如使用热氧化工艺形成的氧化硅。垫层204a可以充当半导体衬底202和掩模层204b之间的粘附层。垫层204a还可以充当用于蚀刻掩模层204b的蚀刻终止层。在实施例中，掩模层204b由氮化硅形成，例如使用低压化学汽相沉积(LPCVD)或等离子体增强化学汽相沉积(PECVD)。掩模层204b在后续的光刻工艺期间用作硬掩模。感光层206形成在掩模层204b上，然后被图案化，从而在感光层206中形成开口208。
参考图3A和图3B，在感光层206中形成开口208后，通过在衬底202中形成多个鳍212来制造图3A和图3B中的结构。图3A是根据实施例的处于制造的其中一个阶段的半导体器件200的透视图，并且图3B是沿着图3A的线a-a获得的半导体器件200的截面图。通过开口208蚀刻掩模层204b和垫层204a以暴露下面的半导体衬底202。然后蚀刻暴露的半导体衬底202以形成低于半导体衬底202的主表面202s的沟槽210。沟槽210之间的半导体衬底202的部分形成半导体鳍212。
在所描述的实施例中，半导体鳍212从衬底主表面202s向下延伸至第一高度H1。沟槽210可以是相互平行的带(从半导体200的顶部观察)，并且彼此紧密间隔。每一个沟槽210都具有宽度W，第一高度H1，并且通过间距S与相邻的沟槽隔开。例如，沟槽210之间的间距S可以小于约30nm。然后去除感光层206。接下来，可以实施清洗以去除半导体衬底202的自然氧化物。可以使用稀释的氢氟(DHF)酸实施清洗。
在一些实施例中，沟槽210的第一高度H1可以介于约2100埃至约2500埃的范围内，而沟槽210的宽度W可以介于约300埃至约1500埃的范围内。在示例性实施例中，沟槽210的纵横比(H/W)大于约7.0。在一些其他的实施例中，纵横比还可以大于约8.0。在另一些实施例中，纵横比小于约7.0或者介于约7.0至8.0之间。然而，本领域的普通技术人员将认识到，整个说明书中所引用的尺寸和数值仅是实例，并且可以被更改以适合集成电路的不同比例。
然后在沟槽210中可选地形成衬垫氧化物(未示出)。在实施例中，衬垫氧化物可以是厚度介于约20埃至约500埃范围内的热氧化物。在一些实施例中，可以使用原位蒸汽产生(ISSG)等形成衬垫氧化物。衬垫氧化物的形成使沟槽210圆角化，这减小了电场，因此提高了所形成的集成电路的性能。
图4A是根据实施例的处于制造的其中一个阶段的半导体器件200的透视图，图4B是沿着图4A的线a-a获得的半导体器件200的截面图。用介电材料214填充沟槽210。介电材料214可以包括氧化硅，因此本发明中也称为氧化物214。在一些实施例中，还可以使用诸如氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)或低k介电材料的其他介电材料。在实施例中，可以使用高密度等离子体(HDP)CVD工艺用硅烷(SiH4)和氧气(O2)作为反应前体形成氧化物214。在其他的实施例中，可以使用次大气压CVD(SACVD)工艺或高纵横比工艺(HARP)形成氧化物214，其中工艺气体可以包括正硅酸乙酯(TEOS)和臭氧(O3)。在其他的实施例中，可以使用旋涂电介质(SOD)工艺诸如氢硅倍半氧烷(HSQ)或甲基硅倍半氧烷(MSQ)形成氧化物214。
图4A和图4B描述介电材料214沉积之后所形成的结构。然后实施化学机械抛光，之后去除掩模层204b和垫层204a。图5A和图5B示出形成的结构。图5A是根据实施例的处于制造的其中一个阶段的半导体器件200的透视图，并且图5B是沿着图5A的线a-a获得的半导体器件200的截面图。沟槽210中的氧化物214的余留部分在下文中被称为绝缘层216。在一个实施例中，掩模层204b由氮化硅形成，并且可以使用湿式工艺利用热H3PO4去除掩模层204b；如果垫层204a由氧化硅形成，则可以使用稀释的HF酸去除垫层204a。在一些可选的实施例中，可以在凹进绝缘层216后实施掩模层204b和垫层204a的去除，图6A和图6B示出凹进步骤。
如图6A和图6B所示，在去除掩模层204b和垫层204a之后，通过蚀刻步骤凹进绝缘层216，形成凹槽218和包括顶面216t的剩余绝缘层216a。图6A是根据实施例的处于其中一个阶段的半导体器件200的透视图，图6B是沿着图6A的线a-a获得的半导体器件200的截面图。在一个实施例中，可以使用湿式蚀刻工艺例如通过在氢氟酸(HF)中浸渍衬底202实施蚀刻步骤。在另一实施例中，可以使用干式蚀刻工艺实施蚀刻步骤，例如可以使用CHF3或BF3作为蚀刻气体实施干式蚀刻工艺。
在所描述的实施例中，鳍212的上部222从衬底主表面202s向下延伸到顶面216t至小于第一高度H1的第二高度H2，从而鳍212的上部222延伸超出绝缘层216的顶面216t。在一个实施例中，第二高度H2与第一高度H1的比值介于约0.2至约0.5之间。鳍212的上部222的第二高度H2可以介于约15nm和约50nm之间，但也可以大于或小于这个值。在所描述的实施例中，鳍212的上部222可以包括沟道部分222a和源极/漏极(S/D)部分222b。沟道部分222a用于形成半导体器件200的沟道区。
图7A是根据实施例的处于制造的其中一个阶段的半导体器件200的透视图，并且图7B是沿着图7A的线a-a获得的半导体器件200的截面图。栅极堆叠件220形成在鳍212的上部222的沟道部分222a的上方，并且延伸至绝缘层216a的顶面216t。在一些实施例中，栅极堆叠件220通常包括栅极介电层220a和位于栅极介电层220a上方的栅极电极层220b。
在图7A和图7B中，形成栅极介电层220a以覆盖鳍212的上部222的沟道部分222a。在一些实施例中，栅极介电层220a可以包括氧化硅、氮化硅、氮氧化硅或高k电介质。高k电介质包括金属氧化物。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物以及它们的混合物。在本实施例中，栅极介电层220a是厚度介于约10埃至约30埃范围内的高k介电层。可以使用合适的工艺诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV臭氧氧化或它们的组合形成栅极介电层220a。栅极介电层220a还可以包括界面层(未示出)以减小栅极介电层220a和鳍212的上部222的沟道部分222a之间的损坏。界面层可以包括氧化硅。
然后在栅极介电层220a上形成栅极电极层220b。在一个实施例中，栅极电极层220b覆盖一个以上的半导体鳍212的上部222，从而使得形成的半导体器件200包括一个以上的鳍。在一些可选的实施例中，半导体鳍212的上部222的每一个都可以用于形成单独的半导体器件200。在一些实施例中，栅极电极层220b可以包括单层或多层结构。在本实施例中，栅极电极层220b可以包括多晶硅。而且，栅极电极层220b可以均匀或者非均匀掺杂多晶硅。在一些可选的实施例中，栅极电极层220b可以包括金属诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi、功函数与衬底材料兼容的其他导电材料，或它们的组合。在本实施例中，栅极电极层220b包括介于约30nm至约60nm范围内的厚度。可以使用合适的工艺诸如ALD、CVD、PVD、电镀或它们的组合形成栅极电极层220b。
仍参考图7A，半导体器件200还包括在衬底202上方并且沿着栅极堆叠件220的侧面形成的介电层224。在一些实施例中，介电层224可以包括氧化硅、氮化硅、氮氧化硅或其他合适的材料。介电层224可以包括单层或多层结构。可以通过CVD、PVD、ALD或其他合适的方法形成介电层224的覆盖层。然后，在介电层224上实施各向异性蚀刻以在栅极堆叠件220的两侧形成一对间隔件。介电层224包括介于约5nm至15nm范围内的厚度。
图8A是根据实施例的处于其中一个制造阶段的半导体器件200的透视图，并且图8B是沿着图8A的线b-b获得的半导体器件200的截面图。栅极堆叠件220和介电层224用作硬掩模，实施偏蚀刻工艺凹进鳍212的上部222的S/D部分222b(未保护的或暴露的)以形成位于主表面202s之下的S/D腔228。在一个实施例中，可以使用选自NF3、CF4和SF6的化学物质用作蚀刻气体来实施蚀刻工艺。在可选的实施例中，可以使用包含NH4OH和H2O2的溶液来实施蚀刻工艺。
参考图9A和图9B以及图1中步骤104，在S/D部分222b中形成S/D腔228之后，通过在S/D腔228中外延生长应变材料226来制造图9A和图9B中的结构，其中应变材料226的晶格常数不同于衬底202的晶格常数。图9A是根据实施例的处于制造的其中一个阶段的半导体器件200的透视图，并且图9B是沿着图9A的线b-b获得的半导体器件200的截面图。在所描述的实施例中，应变材料226的顶面226t高于顶面216t。在一些实施例中，应变材料226包括用于p型金属氧化物半导体场效应晶体管(pMOSFET)的SiGe或SiGeB。
在所描述的实施例中，可以实施预清洗工艺从而用HF或其他合适的溶液清洗S/D腔228。然后，通过LPCVD工艺选择性生长诸如硅锗(SiGe)的应变材料226以填充S/D腔228。在一个实施例中，在约660℃至700℃的温度以及约13托至50托的压力下，使用SiH2Cl2、HCl、GeH4、B2H6和H2用作反应气体来实施LPCVD工艺。
工艺步骤到目前为止已经提供了具有在S/D腔228中的应变材料226的衬底202。按照惯例，可以通过覆盖沉积金属材料(诸如镍、钛、钴和它们的组合)薄层形成位于应变材料226上方的硅化物区。然后加热衬底202，这引起硅与所接触的金属反应。反应后，在含硅材料和金属之间形成金属硅化物层。通过使用侵蚀金属材料但不侵蚀硅化物的蚀刻剂选择性地去除未反应的金属。然而，金属硅化物和应变材料226之间的费米能级钉扎效应导致固定的肖特基势垒高度(SBH)。这种固定的SBH引起半导体器件的S/D区的高接触电阻并且因此使器件性能退化。
因此，以下参考图10至图12论述的工艺可以形成包括含Ge介电层的接触结构以取代硅化物区。含Ge介电层可以充当低电阻中间层以取代高电阻金属硅化物。同样地，接触结构可以提供半导体器件的S/D区的低接触电阻，从而提高器件性能。
如图10以及图1中步骤106所描述，为了制造半导体器件200的接触结构(诸如图12中示出的接触结构230)，通过在应变材料226上方外延生长Ge层232来制造图10中的结构。图10是根据实施例的处于制造的其中一个阶段的沿着图9A的线b-b获得的半导体器件200的截面图。在一些实施例中，Ge层232具有介于约1nm至约10nm范围的厚度。在一些实施例中，制造接触结构230的步骤还包括在外延生长Ge层232之前修减应变材料226以避免相邻的Ge层232之间的融合。在一些实施例中，使用HCl用作蚀刻气体实施修剪应变材料226的步骤。
在一个实施例中，可以在约10毫托至100毫托的压力、约350℃至450℃的温度下使用GeH4、GeH3CH3和/或(GeH3)2CH2作为外延气体来实施Ge外延工艺。可选地，在外延工艺之后，在约550℃至750℃的温度下实施退火工艺以限制应变材料226和Ge外延层232的界面上的位错缺陷。
图11是根据实施例的处于制造的其中一个阶段的半导体器件200沿着图9A的线b-b获得的截面图。然后，通过处理240处理Ge层232以形成位于应变材料226上方的含Ge介电层234(图1中的步骤108)来制造图11中所描述的结构。在一些实施例中，含Ge介电层234包括GeNx，GeOx或GeOxNy。在一些实施例中，含Ge介电层234具有介于约1nm至约10nm范围内的第一厚度t1。
在一些实施例中，通过热氮化或热氧化(将Ge层232的表面暴露于包含N2、NH3、H2O、O2或O3的蒸汽)执行处理240步骤处理Ge层232以形成应变材料226上方的含Ge介电层234。在一些实施例中，通过等离子体掺杂或离子注入使用N2和/或O2作为掺杂气体来执行处理240步骤从而处理Ge层232以形成应变材料226上方的含Ge介电层234。掺杂浓度介于约1015至约1022原子/cm3。然后，通过退火处理衬底202以将掺杂Ge层232转变为含Ge介电层234来制造图11所描述的结构。在所描述的实施例中，含Ge介电层234可以降低固定的SBH并且充当低电阻层以取代高电阻金属硅化物，从而提高器件性能。
图12是根据实施例的处于制造的其中一个阶段的半导体器件200沿着图9A的线b-b获得的截面图。参考图12，在形成含Ge介电层234之后，在含Ge介电层234上方形成具有介于约5nm至约10nm范围内的第二厚度t2的第一金属层236(图1中的步骤110)。在一些实施例中，第一金属层236包括Co、Ni或TiN。可以通过CVD、ALD或溅射形成第一金属层236。在所描述的实施例中，第一金属层236、含Ge介电层234、应变材料226以及衬底202被合并且被称为半导体器件200的接触结构230。
然后，第二金属层238形成在第一金属层236上方。在所描述的实施例中，第二金属层238包括Al、Cu或W。在一些实施例中，可以通过CVD、PVD、ALD或其他合适的方法形成第二金属层238。在执行图1示出的步骤之后(如关于图2A至图12所示的实例所作出的进一步阐述)，通常实施后续的工艺(包括互连工艺)以完成半导体器件200的制造。
根据一个实施例，用于半导体器件的接触结构包括衬底，该衬底包括主表面和位于主表面之下的腔；位于腔中的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数；应变材料上方的含Ge介电层以及含Ge介电层上方的金属层。
根据另一实施例，p型金属氧化物半导体场效应晶体管(pMOSFET)包括衬底，该衬底包括主表面和位于主表面之下的腔；位于衬底的主表面上的栅极堆叠件；设置在栅极堆叠件一侧的浅沟槽隔离(STI)区，其中STI区位于衬底内；分布在栅极堆叠件和STI区之间的接触结构，其中接触结构包括位于腔中的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数；应变材料上方的含Ge介电层；以及含Ge介电层上方的金属层。
根据另一实施例，一种制造半导体器件的方法包括：提供衬底，该衬底包括主表面和位于主表面之下的腔；在腔中外延生长应变材料，其中应变材料的晶格常数不同于衬底的晶格常数；在应变材料上方外延生长Ge层；处理Ge层以在应变材料上方形成含Ge介电层；以及在含Ge介电层上方形成金属层。
虽然通过实例和根据优选的实施例描述了本发明，但是应理解本发明不限于公开的实施例。相反，本发明意图涵盖各种修改和相似的布置(对本领域的技术人员来说显而易见的)。因此，所附权利要求的范围应与最广泛的解释一致以涵盖所有这些改进和相似的布置。

Claims (20)

1.一种用于半导体器件的接触结构，包括：
衬底，包括主表面和位于所述主表面之下的腔；
所述腔中的应变材料，其中所述应变材料的晶格常数不同于所述衬底的晶格常数；
含Ge介电层，位于所述应变材料上方，所述含Ge介电层具有均匀厚度；以及
金属层，位于所述含Ge介电层上方。
2.根据权利要求1所述的用于半导体器件的接触结构，其中，所述应变材料包含SiGe或SiGeB。
3.根据权利要求1所述的用于半导体器件的接触结构，其中，所述含Ge介电层具有介于1nm至10nm范围内的厚度。
4.根据权利要求1所述的用于半导体器件的接触结构，其中，所述含Ge介电层包含GeNx。
5.根据权利要求1所述的用于半导体器件的接触结构，其中，所述含Ge介电层包含GeOx或GeOxNy。
6.根据权利要求1所述的用于半导体器件的接触结构，其中，所述金属层包含Co、Ni或TiN。
7.根据权利要求1所述的用于半导体器件的接触结构，其中，所述金属层具有介于5nm至10nm范围内的厚度。
8.一种p型金属氧化物半导体场效应晶体管(pMOSFET)，包括：
衬底，包括主表面和位于所述主表面之下的腔；
栅极堆叠件，位于所述衬底的主表面上；
浅沟槽隔离(STI)区，设置在所述栅极堆叠件的一侧上，其中所述浅沟槽隔离区位于所述衬底内；以及
接触结构，分布在所述栅极堆叠件和所述浅沟槽隔离区之间，其中所述接触结构包括：
所述腔中的应变材料，其中所述应变材料的晶格常数不同于所述衬底的晶格常数；
位于所述应变材料上方的含Ge介电层，所述含Ge介电层具有均匀厚度；以及
位于所述含Ge介电层上方的金属层。
9.根据权利要求8所述的p型金属氧化物半导体场效应晶体管，其中，所述应变材料包含SiGe或SiGeB。
10.根据权利要求8所述的p型金属氧化物半导体场效应晶体管，其中，所述含Ge介电层具有介于1nm至10nm范围内的厚度。
11.根据权利要求8所述的p型金属氧化物半导体场效应晶体管，其中，所述含Ge介电层包含GeNx。
12.根据权利要求8所述的p型金属氧化物半导体场效应晶体管，其中，所述含Ge介电层包含GeOx或GeOxNy。
13.根据权利要求8所述的p型金属氧化物半导体场效应晶体管，其中，所述金属层包含Co、Ni或TiN。
14.根据权利要求8所述的p型金属氧化物半导体场效应晶体管，其中，所述金属层具有介于5nm至10nm范围内的厚度。
15.一种制造半导体器件的方法，包括：
提供衬底，所述衬底包括主表面和位于所述主表面之下的腔；
在所述腔中外延生长应变材料，其中所述应变材料的晶格常数不同于所述衬底的晶格常数；
在所述应变材料上方外延生长Ge层；
处理所述Ge层以在所述应变材料上方形成含Ge介电层，所述含Ge介电层具有均匀厚度；以及
在所述含Ge介电层上方形成金属层。
16.根据权利要求15所述的制造半导体器件的方法，还包括：
在所述应变材料上方外延生长所述Ge层之前修剪所述应变材料。
17.根据权利要求16所述的制造半导体器件的方法，其中，使用HCl作为蚀刻气体执行修剪所述应变材料的步骤。
18.根据权利要求15所述的制造半导体器件的方法，其中，通过将所述Ge层暴露于包含N2、NH3、H2O、O2或O3的蒸汽来执行处理所述Ge层的步骤。
19.根据权利要求15所述的制造半导体器件的方法，其中，通过等离子体掺杂或离子注入执行处理所述Ge层的步骤。
20.根据权利要求15所述的制造半导体器件的方法，其中，通过CVD、ALD或溅射执行在所述介电层上方形成金属层的步骤。
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US20160005825A1 (en) 2016-01-07
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US20140042500A1 (en) 2014-02-13
US20160254383A1 (en) 2016-09-01
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