TWI520340B - 半導體裝置之接觸結構、ｐ型金氧半導體場效電晶體及半導體裝置之製造方法 - Google Patents

半導體裝置之接觸結構、ｐ型金氧半導體場效電晶體及半導體裝置之製造方法 Download PDF

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TWI520340B
TWI520340B TW102125494A TW102125494A TWI520340B TW I520340 B TWI520340 B TW I520340B TW 102125494 A TW102125494 A TW 102125494A TW 102125494 A TW102125494 A TW 102125494A TW I520340 B TWI520340 B TW I520340B
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germanium
layer
dielectric layer
semiconductor device
containing dielectric
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TW102125494A
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TW201407786A (zh
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萬幸仁
葉凌彥
施啓元
陳彥友
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台灣積體電路製造股份有限公司
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Description

半導體裝置之接觸結構、p型金氧半導體場效電晶體及半導體裝置之製造方法
本發明係關於積體電路製作，且特別是關於一種具有接觸結構之半導體裝置。
隨著半導體工業演進至奈米技術製程節點以追求更高元件密度、更佳表現與更低成本，製造與設計問題的挑戰便造成了如鰭型場效電晶體(FinFET)之三維設計(three-dimensional designs)的發展。典型之鰭型場效電晶體係藉由如蝕刻基板之一矽層之一部所形成之延伸自一基板處之極薄之一垂直”鰭部”(或鰭結構)所形成。此鰭型場效電晶體之通道係形成於此垂直之鰭部之內。閘極則形成於(如包覆)鰭部之上。具有位於通道區之兩側之一閘極則允許了於對於通道兩側的閘極控制情形。此外，此鰭型場效電晶體之源極/汲極區內之利用了選擇性成長矽鍺之應變材料則可增強載子遷移率(carrier mobility)。
然而，於互補型金氧半導體(CMOS)製作中應用上述構件與製程仍存在有許多挑戰。舉例來說，形成於應變材料之上之矽化物(silicide)造成了此鰭型場效電晶體之源極/汲極 區之高接觸電阻值(high contact resistance)，進而劣化了裝置表現。
依據一實施例，本發明提供了一種半導體裝置之接觸結構，包括：一基板，包括一主表面以及位於該主表面下方之一空室；一應變材料，位於該空室內，其中該應變材料之一晶格常數不同於該基板之一晶格常數；一含鍺介電層，位於該應變材料上；以及一金屬層，位於該含鍺介電層上。
依據另一實施例，本發明提供了一種p型金氧半導體場效電晶體，包括：一基板，包括一主表面以及位於該主表面下方之一空室；一閘堆疊物，位於該基板之該主表面上；一淺溝槽隔離物，設置於該閘堆疊物之一側上，其中該淺溝槽隔離物係位於該基板之內；以及一接觸結構，分佈於該閘堆疊物與該淺溝槽隔離物之間，其中該接觸結構包括：一應變材料，位於該空室內，其中該應變材料之一晶格常數不同於該基板之一晶格常數；一含鍺介電層，位於該應變材料上；以及一金屬層，位於該含鍺介電層上。
依據又一實施例，本發明提供了一種半導體裝置之製造方法，包括：提供包括一主表面以及位於該主表面下方之一空室之一基板；於該空室內磊晶成長一應變材料，其中該應變材料之一晶格常數不同於該基板之一晶格常數；磊晶成長一鍺層於該應變材料上；處理該鍺層以形成位於該應變材料上之一含鍺介電層；以及形成一金屬層於該含鍺介電層上。
為讓本發明之上述目的、特徵及優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
100‧‧‧半導體裝置之製造方法
102、104、106、108、110‧‧‧步驟
200‧‧‧半導體裝置
202‧‧‧基板
202s‧‧‧主表面
204a‧‧‧墊層
204b‧‧‧罩幕層
206‧‧‧感光層
208‧‧‧開口
210‧‧‧溝槽
212‧‧‧半導體鰭狀物
214‧‧‧介電材料
216‧‧‧絕緣層
216a‧‧‧剩餘絕緣層
216t‧‧‧頂面
218‧‧‧凹口
220a‧‧‧閘介電層
220b‧‧‧閘電極
220‧‧‧閘堆疊物
222‧‧‧鰭狀物之上部
222a‧‧‧通道部
222b‧‧‧源極/汲極區
224‧‧‧介電層
226‧‧‧應變材料
226t‧‧‧頂面
228‧‧‧源極/汲極空室
230‧‧‧接觸結構
232‧‧‧鍺層/鍺磊晶層
234‧‧‧含鍺介電層
236‧‧‧第一金屬層
238‧‧‧第二金屬層
240‧‧‧步驟
H1‧‧‧第一高度
H2‧‧‧第二高度
W‧‧‧寬度
S‧‧‧間距
t1‧‧‧第一厚度
t2‧‧‧第二厚度
第1圖顯示了依據本發明之一實施例之一種具有接觸結構之半導體裝置之製造方法之一流程圖。
第2A-9A、2B-9B、10-12圖為一系列之立體圖與剖面圖，顯示了於不同製造階段中之依據本發明之一實施例之一種具有接觸結構之半導體裝置。
可以理解的是，於下文中提供了用於施行本發明之不同特徵之多個不同實施例，或範例。基於簡化本發明之目的，以下描述了元件與設置情形之特定範例。然而，此些元件與設置情形僅作為範例之用而非用於限制本發明。此外，本發明於不同實施例中可能重複使用標號及/或文字。如此之重複情形係基於簡化與清楚之目的，而非用於限定不同實施例及/或討論形態內的相對關係。再者，於描述中關於於一第二元件之上或上之第一元件的形成可包括了第一元件與第二元件係為直接接觸之實施情形，且亦包括了於第一元件與第二元件之間包括了額外元件之實施情形，因而使得第一元件與第二元件之間並未直接接觸。此外，本發明於多個範例內可能使用重複之標號及/或文字。如此之重複情形係基於簡化與清楚之目的，而非用於顯示多個實施例及/或所討論圖式之間的關係。
請參照第1圖，顯示了依據本發明之一實施例之一 種具有接觸結構之半導體裝置之製造方法100之一流程圖。方法100起使於步驟102，提供包括一主表面以及位於主表面下方之一空室之一基板。方法100接著進行步驟104，於空室內磊晶成長一應變材料，其中此應變材料之晶格常數不同於基板之晶格常數。方法100接著進行步驟106，於應變材料上磊晶成長一鍺(Ge)層。方法100接著進行步驟108，處理此鍺層以於應變材料上形成一含鍺介電層(Ge-containing dielectric layer)。方法100繼續步驟110，形成一金屬層於含鍺介電層上。於下文中將藉由圖示實施例以解說可藉由第1圖所示方法所製造形成之半導體裝置。
第2A-12圖為一系列立體圖與剖面圖，顯示了依據本發明之一實施例之一種具有接觸結構230之半導體裝置200於不同製造階段中之情形。在此顯示之實施例中係關於一種鰭型場效電晶體(FinFET)。此鰭型場效電晶體可為任何形態之鰭基多重閘電晶體(fin-based multi-gate transistor)。於部份之其他實施例中，於下文中討論之此些實施例係關於一種平面型金氧半導體場效電晶體(planar MOSFET)。此半導體裝置200可位於一微處理器、記憶胞、及/或其他積體電路之內。
值得注意的是，於部份實施例中，於第1圖內所提及的操作表現並無法形成完整的一半導體裝置200。可更採用互補型金氧半導體技術製程(CMOS technology processing)以形成完整的半導體裝置200。如此，可以理解的是，可於如第1圖所示之方法100施行之前、之中或之後施行額外之製程，且部份之其他製程於此處簡單僅進行簡單描述。此外，第2A-12 圖係經過簡化以較為簡單瞭解本發明之概念。舉例來說，雖然所有圖式中繪示了半導體裝置200，可以理解的是於積體電路中可包括如電阻、電容、電感、熔絲等之數個其他裝置。
請參照第2A與2B圖以及第1圖內之步驟102，提供一基板202。第2A圖顯示了依據本發明之一實施例之製作中之多個步驟之一中之具有一基板202之一半導體裝置200之一立體圖，而第2B圖為沿著第2A圖內線段a-a之半導體裝置200之一剖面圖。於至少一實施例中，基板202包括一結晶矽基板(例如一晶圓)。基板202可依照設計需求(例如p型基板或n型基板)而包括多個摻雜區。於部份實施例中，此些摻雜區可摻雜有n型或p型摻質。舉例來說，此些摻雜區域可摻雜有如硼或BF2之p型摻質，或摻雜有如磷或砷之n型摻質，及/或其組合。此些摻雜區可用於形成一n型金氧半導體場效電晶體(nMOSFET)或形成一p型金氧半導體場效電晶體(pMOSFET)。
於其他實施例中，基板202可由如鑽石(diamond)或鍺(germanium)之其他適當元素半導體、如砷化鎵(gallium arsenide)、碳化矽(silicon carbide)、砷化銦(indium arsenide)、或磷化銦(indium phosphide)之一適當化合物半導體，或如碳化矽鍺(silicon germanium carbide)、磷砷化鎵(gallium arsenic phosphide)或磷銦化鎵(gallium indium phosphide)之一適當合金材料所製成。再者，基板202可包括一磊晶層(磊晶層)，其可經過應變以增加表現，及/或可包括一絕緣層上覆矽結構。
於一實施例中，於基板202之一主表面202s之上形成有一墊層(pad layer)204a與一罩幕層(mask layer)204b。墊層 204a可為包括採用如熱氧化製程所形成之氧化矽之一薄膜層。墊層204a可做為介於半導體基板202與罩幕層204b間之一黏著層(adhesion layer)。墊層204a亦可於蝕刻罩幕層204b時做為一蝕刻停止層。於一實施例中，罩幕層204b包括採用如低壓化學氣相沈積或電漿加強型化學氣相沈積所形成之氮化矽。罩幕層204b於後續微影製程中係做為一硬罩幕。感光層206則形成於罩幕層204b上，且接著經過圖案化以於感光層206內形成數個開口208。
請參照第3A與3B圖，於感光層206內形成數個開口208之後，如第3A與3B圖內結構經過製作以形成位於基板202內之數個鰭狀物212。第3A圖顯示了依據本發明之一實施例之製作中之多個步驟之一中之一半導體裝置200之一立體圖，而第3B圖為沿著第3A圖內線段a-a之半導體裝置200之一剖面圖。穿過此些開口208以蝕刻罩幕層204b與墊層204a，露出下方的半導體基板202。接著蝕刻露出之半導體基板202以形成低於半導體基板202之主表面202s之數個溝槽210。介於此些溝槽210間之半導體基板202的數個部份便形成了半導體鰭狀物(semiconductor fins)212。
於圖示實施例中，半導體鰭狀物212自半導體基板200之主要表面202s向下延伸至一第一高度H1。此些溝槽210可為相平行且緊密地相分隔之數個條狀物(自半導體基板200之上視觀之)。此些溝槽210分別具有一寬度W、第一高度H1且與其鄰近溝槽之間相距一間距S。舉例來說，介於此些溝槽210間之此些間距S可少於約30奈米。可接著移除感光層206。接 著，可施行一潔淨(cleaning)製程以移除半導體基板202上之原生氧化物(native oxides)。上述捷淨製程可採用稀釋氫氟酸(diluted HF acid)而施行。
於部份實施例中，溝槽210之第一高度H1可介於約2100-2500埃，而此些溝槽210之寬度W可介於約300-1500埃。於一示範實施例中，此些溝槽210之深寬比(aspect ratio)可大於約7.0。於其他實施例中，此深寬比可更大於約8.0。於其他實施例中，此深寬比可低於7.0或介於7.0-8.0之間。然而，本領域之通常知識者可以理解此些尺寸與數值僅作為範例之用，且其可改變以符合不同規格之積體電路之用。
於此些溝槽210內可選擇地形成襯氧化物(liner oxide，未顯示)。於一實施例中，襯氧化物可為具有介於約20-150埃之一厚度之一熱氧化物(thermal oxides)。於部份實施例中，襯氧化物可形成採用臨場蒸汽產生法(in-situ steam generation)及相似方法所形成。襯氧化物的形成圓滑了溝槽210的邊角，如此可降低電場且因此改善了最後得到之積體電路的表現。
第4A圖顯示了依據本發明之一實施例之製作中之多個步驟之一中之一半導體裝置200之一立體圖，而第4B圖為沿著第4A圖內線段a-a之半導體裝置200之一剖面圖。此些溝槽210為一介電材料214所填入。介電材料214可包括氧化矽，且因此於下文中可稱為氧化物214。於部份實施例中，可使用如氮化矽、氮氧化矽、氟摻雜矽玻璃(FSG)或低介電常數介電材料之其他介電材料。於一實施例中，氧化物214可藉由採用矽 甲烷與氧氣做為反應前驅物之高密度電漿加強型化學氣相沈積(HDP CVD)製程所形成。於其他實施例中，氧化物214可採用次大氣壓化學氣相沈積(SACVD)製程或高深寬比(HARP)製程所形成，其中製程氣體可包括四乙氧基矽烷(TEOS)與臭氧(O3)。於又一實施例中，氧化物214可形成採用一旋轉塗佈製程，例如為氫矽倍半氧烷(HSQ)與甲基倍半矽氧烷(MSQ)。
第4A與4B圖顯示了沈積介電材料214後之結構。可接著施行一化學機械研磨，並接著移除罩幕層204b與墊層204a。最終結構如第5A與5B圖所示。第5A圖顯示了依據本發明之一實施例之製作中之多個步驟之一中之一半導體裝置200之一立體圖，而第5B圖為沿著第5A圖內線段a-a之半導體裝置200之一剖面圖。位於此些溝槽210內之氧化物214的剩餘部份於下文中稱為絕緣層216。於一實施例中，罩幕層204b係由氮化矽所形成，而罩幕層204b可採用使用熱磷酸之一濕蝕刻製程所移除，而當墊層204a為氧化矽時，其可採用稀釋氫氟酸所移除。於部份之其他實施例中，罩幕層204b與墊層204a的移除可於凹陷(recessing)絕緣層216之後施行，而此凹陷步驟則於第6A與6B圖中顯示。
如第6A與6B圖所示，於移除罩幕層204b與墊層204a之後，藉由一蝕刻步驟以凹陷絕緣層216，並形成了數個凹口218以及包括一頂面216t之剩餘絕緣層216a。第6A圖顯示了依據本發明之一實施例之製作中之多個步驟之一中之一半導體裝置200之一立體圖，而第6B圖為沿著第6A圖內線段a-a之半導體裝置200之一剖面圖。於一實施例中，上述蝕刻步驟 可採用一濕蝕刻製程所施行，例如將基板202浸入於氫氟酸中。於其他實施例中，此蝕刻步驟可採用一乾蝕刻製程所施行，而此乾蝕刻製程可採用CHF3或BF3做為蝕刻氣體而施行。
於圖示之實施例中，此些鰭狀物212之上部222自半導體基板202之主表面202s朝下延伸至頂面216t至低於第一高度H1之一第二高度H2，進而延伸至絕緣層216之頂面216t處。於一實施例中，第二高度H2與第一高度H1間之一比例約為0.2-0.5。鰭狀物212之上部222的第二高度H2可介於15-50奈米，雖然其亦可為更大或更小。於圖示之實施例中，此些鰭狀物212之上部可包括通道部222a與源極/汲極區222b。通道區222a係用於形成半導體裝置200之通道區。
第7A圖顯示了依據本發明之一實施例之製作中之多個步驟之一中之一半導體裝置200之一立體圖，而第7B圖為沿著第7A圖內線段a-a之半導體裝置200之一剖面圖。閘堆疊物220係形成於鰭狀物212之上部222之通道區222a之上，且延伸至絕緣層216a的頂面216t處。於部份之實施例中，閘堆疊物220通常包括位於閘介電層220a上之一閘介電層220a與一閘電極220b。
於第7A與7B圖中，形成介電層220a以覆蓋鰭狀物212之上部222之通道部222a。於部份實施例中，閘介電層220a可包括氧化矽、氮化矽、氮氧化矽或高介電常數介電材料。高介電常數介電材料包括了金屬氧化物。做為高介電常數介電材料之金屬氧化物包括了Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、 Yb、Lu之氧化物及其混合物。於本實施例中，閘介電層220a為具有介於約10-30埃之一厚度之一高介電常數介電層。閘介電材料220a可採用如為原子層沈積、化學氣相沈積、物理氣相沈積、熱氧化法、深紫外光-臭氧法或其組合之一適當製程所形成。閘介電材料層220a可更包括一中間層(未顯示)，以降低閘介電層220a與鰭狀物212之上部之通道層222a之間的毀損情形。上述中間層可包括氧化矽。
接著形成閘電極層220b於閘介電層220a之上。於一實施例中，閘電極層220b覆蓋了一個以上之鰭狀物212之上部222，使得最終半導體裝置200包括了多於一個以上之鰭狀物。於其他之實施例中，此些半導體鰭狀物212之上部可分別用於形成個別之一半導體裝置200。於部分實施例中，閘電極層220b可包括單一膜層或多重膜層。於本實施例中，閘電極層220b可包括多晶矽。再者，閘電極層220b可為具有均勻摻雜或非均勻摻雜之摻雜多晶矽(doped polysilicon)。於部分之其他實施例中，閘電極層220b可包括如為Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi或其組合之一金屬、具有匹配於基底材料之功函數之其他導電材料、或其組合。於本實施例中，閘電極層220b包括介於30-60奈米之一厚度。閘電極層220b可採用如原子層沉積、化學氣相沉積、物理氣相沉積、電鍍或其組合之一適當製程所形成。
請繼續參照第7A圖，半導體裝置200更包括形成於基板202上且沿著閘堆疊物220的側邊形成之一介電層224。於部分實施例中，介電層224可包括氧化矽、氮化矽、氮氧化矽、 或其他適當材料。介電層224可包括單一膜層或多膜層結構。介電層224之坦覆膜層可藉由化學氣相沉積、物理氣相沉積、原子層沉積或其他適當技術所形成。接著，可針對介電層224施行非等向性蝕刻以形成一對間隔物於閘堆疊物220之兩側上。介電層224可具有介於5-15奈米之一厚度。
第8A圖顯示了依據本發明之一實施例之製作中之多個步驟之一中之一半導體裝置200之一立體圖，而第8B圖為沿著第8A圖內線段b-b之半導體裝置200之一剖面圖。採用閘堆疊物220與介電層224作為硬罩幕，施行一偏壓蝕刻(biased etching)製程以凹陷鰭狀物212之上部222之未為保護的或露出的源極/汲極區222b，以形成位於主表面202s下方之數個源極/汲極空室228。於一實施例中，可採用擇自由NF3、CF4與SF6作為蝕刻氣體之一化學品以施行此蝕刻製程。於其他實施例中，此蝕刻製程可採用包括NH4OH與H2O2之一溶液。
請參照第9A與9B圖以及第1圖內之步驟104，於源極/汲極部222b內形成源極/汲極空室228之後，藉由磊晶成長一應變材料226以於此些源極/汲極空室228內製作出如第9A與9B圖所示結構，其中應變材料226之晶格常數不同於基板202之晶格常數。第9A圖顯示了依據本發明之一實施例之製作中之多個步驟之一中之一半導體裝置200之一立體圖，而第9B圖為沿著第9A圖內線段b-b之半導體裝置200之一剖面圖。於圖示之實施例中，應變材料226之頂面226t係高於頂面216t。於部分實施例中，應變材料226包括用於一P型金氧半導體場效電晶體之矽鍺(SiGe)或矽鍺硼(SiGeB)。
於圖示之實施例中，可採用氫氟酸或其他適當溶液以施行一預先潔淨製程(pre-clean process)以潔淨源極/汲極空室228。接著，藉由低壓化學氣相沉積以選擇性成長如矽鍺之應變材料226以填滿源極/汲極空室228。於一實施例中，低壓化學氣相沉積製程係於約660-700℃之一溫度下以及約為13-50 Torr之一壓力下施行，其採用SiH2Cl2、HCl、GeH4、B2H6與氫氣作為反應氣體。
製程步驟至此，已形成了具有位於源極/汲極空室228內之應變材料226之基板202。傳統地，可藉由坦覆地沉積如鎳、鈦、鈷或其組合之一金屬材料之薄層以形成位於應變材料226上之矽化物區(silicide regions)。接著加熱此基板202，以使得矽與所接觸之金屬反應。於反應之後，於含矽材料與金屬之間形成有一層金屬矽化物。透過使用可攻擊金屬材料但不會攻擊矽化物之一蝕刻劑以選擇性地移除未反應之金屬。然而，介於金屬矽化物與應變材料226之間的費米能階鎖定效應(Fermi level pinning)造成了一固定的蕭基能位障(Schottky barrier height，SBH)。此固定之蕭基能位障造成了半導體裝置之源極汲極區之高接觸電阻值且因此劣化了裝置表現。
如此，於下文中參照第10-12圖所探討之製程可形成包括一含鍺介電層之一接觸結構以替代上述矽化物區。含鍺介電層可作為低電阻值之中間層以取代高電阻值之金屬矽化物(metal silicide)。如此，接觸結構可提供半導體裝置之源極/汲極區之低接觸電阻值，進而增加了裝置表現。
如第10圖及第1圖內步驟106所示，為了製造半導 體裝置200之一接觸結構(例如第12圖內所示之一接觸結構230)，藉由磊晶成長鍺層232於應變材料226之上而形成如第10圖所示結構。第10圖為依據本發明之一實施例之製作中之多個步驟之一中之沿著第9A圖內線段b-b之半導體裝置200之一剖面圖。於部分之實施例中，鍺層232具有介於約1-10奈米之一厚度。於部分之實施例中，接觸結構230的製造步驟更包括早於磊晶成長鍺層232之前縮減應變材料226以避免相鄰鍺層232的聚合。於部分之實施例中，縮減應變材料226之步驟的施行可採用氯化氫(HCl)作為一蝕刻氣體。
於一實施例中，可於壓力約為10-100 mTorr下、於溫度約為350-450℃下採用GeH4、GeH3CH3、及/或(GeH3)2CH2作為磊晶氣體以施行鍺磊晶製程。於磊晶製程之後可選擇性地於約為550-750℃之一溫度下施行一回火製程，以控制應變材料226與鍺磊晶層232間之介面處之差排缺陷(dislocation defects)。
第11圖為依據本發明之一實施例之製作中之多個步驟之一中之沿著第9A圖內線段b-b之半導體裝置200之一剖面圖。接著，如第11圖所示結構係藉由處理(treating)鍺層232以於應變材料226之上形成含鍺介電層(Ge-containing dielectric layer)234(如第1圖所示之步驟108)。於部分實施例中，含鍺膜層234包括氮化鍺(GeNx)、氧化鍺(GeOx)或氮氧化鍺(GeOxNy)。於部分之實施例中，含鍺介電層234具有介於1-10奈米之一第一厚度t1。
於部分之實施例中，處理鍺層232以於應變材料 226上形成含鍺介電層234之步驟240係藉由熱氮化法或熱氧化法所施行，將鍺層232之一表面曝露於包括氮氣(N2)、氨氣(NH3)、水(H2O)、氧氣(O2)或臭氧(O3)之一氣體中。於部分之實施例中，處理鍺層232以於應變材料226之上形成含鍺介電層234之步驟240係介由電漿佈植或離子佈植所施行，其採用氮氣(N2)及/或氧氣(O2)作為摻雜氣體。摻雜濃度約為1015-1022原子/立方公分。接著，如第11圖所示結構係藉由回火基板202以轉化摻雜鍺層232成為含鍺介電層234。於圖示實施例中，含鍺介電層234可降低固定之蕭基能位障且作為用以取代高電阻值之金屬矽化物之一低電阻值層，進而增強裝置表現。
第12圖為依據本發明之一實施例之製作中之多個步驟之一中之沿著第9A圖內線段b-b之半導體裝置200之一剖面圖。請參照第12圖，於含鍺介電層234形成之後，形成第一金屬層236於含鍺介電層234之上(第1圖內步驟110)至介於約5-10奈米之一第二厚度t2。於部分之實施例中，第一金屬層236包括鈷、鎳或氮化鈦。第一金屬層236可藉由化學氣相沉積、原子層沉積或濺鍍所形成。於圖示之實施例中，第一金屬層236、含鍺介電層234、應變材料236與基板202可結合並通稱為半導體裝置200之一接觸結構230。
接著，形成一第二金屬層238於第一金屬層236上。於圖示之實施例中，第二金屬層238包括鋁、銅或鎢。於部分之實施例中，第二金屬層238可包括化學氣相沉積法、物理氣相沉積法、原子層沉積或其他適當技術。於如第1圖所示步驟以及如第2A-12圖所顯示之範例之後，可通常施行包括內 連製程之後續製程以完成半導體裝置的製作。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧半導體裝置
202‧‧‧基板
212‧‧‧半導體鰭狀物
216a‧‧‧剩餘絕緣層
226‧‧‧應變材料
230‧‧‧接觸結構
234‧‧‧含鍺介電層
236‧‧‧第一金屬層
238‧‧‧第二金屬層
t1‧‧‧第一厚度
t2‧‧‧第二厚度

Claims (10)

  1. 一種半導體裝置之接觸結構，包括：一基板，包括一主表面以及位於該主表面下方之一空室；一應變材料，位於該空室內，其中該應變材料之一晶格常數不同於該基板之一晶格常數；一含鍺介電層，位於該應變材料上，其中該含鍺介電層具有大體均勻之一厚度；以及一金屬層，位於該含鍺介電層上，其中該金屬層具有大體均勻之一厚度。
  2. 如申請專利範圍第1項所述之半導體裝置之接觸結構，其中該應變材料包括矽鍺或矽鍺硼，該含鍺介電層包括氮化鍺(GeNx)，該含鍺介電層包括氧化鍺(GeOx)或氮氧化鍺(GeOxNy)。
  3. 如申請專利範圍第1項所述之半導體裝置之接觸結構，其中該含鍺介電層具有介於1-10奈米之一厚度，該金屬層具有介於約5-10奈米之一厚度。
  4. 一種p型金氧半導體場效電晶體，包括：一基板，包括一主表面以及位於該主表面下方之一空室；一閘堆疊物，位於該基板之該主表面上；一淺溝槽隔離物，設置於該閘堆疊物之一側上，其中該淺溝槽隔離物係位於該基板之內；以及一接觸結構，分佈於該閘堆疊物與該淺溝槽隔離物之間，其中該接觸結構包括：一應變材料，位於該空室內，其中該應變材料之一晶格常 數不同於該基板之一晶格常數；一含鍺介電層，位於該應變材料上，其中該含鍺介電層具有介於約1015-1022原子/立方公分之一摻雜濃度；以及一金屬層，位於該含鍺介電層上。
  5. 如申請專利範圍第4項所述之p型金氧半導體場效電晶體，其中該應變材料包括矽鍺或矽鍺硼，該含鍺介電層包括氮化鍺(GeNx)，該含鍺介電層包括氧化鍺(GeOx)或氮氧化鍺(GeOxNy)，該金屬層包括鈷、鎳、或氮化鈦。
  6. 如申請專利範圍第4項所述之p型金氧半導體場效電晶體，其中該含鍺介電層具有介於1-10奈米之一厚度，該金屬層具有介於約5-10奈米之一厚度。
  7. 一種半導體裝置之製造方法，包括：提供包括一主表面以及位於該主表面下方之一空室之一基板；於該空室內磊晶成長一應變材料，其中該應變材料之一晶格常數不同於該基板之一晶格常數；磊晶成長一鍺層於該應變材料上；處理該鍺層以形成位於該應變材料上之一含鍺介電層，其中該含鍺介電層具有大體均勻之一厚度；以及形成一金屬層於該含鍺介電層上，其中該金屬層具有大體均勻之一厚度。
  8. 如申請專利範圍第7項所述之半導體裝置之製造方法，更包括：於磊晶成長該鍺層於該應變材料上之前，縮減該應變材料。
  9. 如申請專利範圍第7項所述之半導體裝置之製造方法，其中處理該鍺層係藉由暴露該鍺層於包括氮氣、氨氣、水、氧氣或臭氧之一氣體中所施行，而處理該鍺層係藉由離子摻雜或離子佈值所施行。
  10. 如申請專利範圍第7項所述之半導體裝置之製造方法，其中形成該金屬層於該介電層上係藉由化學氣相沈積、原子層沈積或濺鍍所施行。
TW102125494A 2012-08-09 2013-07-17 半導體裝置之接觸結構、ｐ型金氧半導體場效電晶體及半導體裝置之製造方法 TWI520340B (zh)

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US10043908B2 (en) 2018-08-07
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