TWI550868B - 場效電晶體、半導體元件及場效電晶體之製作方法 - Google Patents

場效電晶體、半導體元件及場效電晶體之製作方法 Download PDF

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TWI550868B
TWI550868B TW102110435A TW102110435A TWI550868B TW I550868 B TWI550868 B TW I550868B TW 102110435 A TW102110435 A TW 102110435A TW 102110435 A TW102110435 A TW 102110435A TW I550868 B TWI550868 B TW I550868B
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field effect
source
effect transistor
channel
channel portion
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TW201344913A (zh
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李宗霖
葉致鍇
袁鋒
彭成毅
萬幸仁
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台灣積體電路製造股份有限公司
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Description

場效電晶體、半導體元件及場效電晶體之製作方法
本發明係有關於一種積體電路之製造，特別是有關於一種具有應變結構之半導體元件及其製造方法。
當一例如金氧半導體場效電晶體(MOSFET)之半導體元件微縮數個世代，金氧半導體場效電晶之閘極堆疊係使用高介電常數閘極介電層和金屬閘電極層，以使微縮元件的同時，可改進元件效能。此外，金氧半導體場效電晶體(MOSFET)係於源極/汲極之凹處中使用選擇性成長矽鍺，形成應變結構，以改善載子移動率。
然而，上述技術在用於互補金屬氧化物半導體(CMOS)時係遇到挑戰，舉例來說，由於應變材料無法傳遞特定量的應變至場效電晶體(FET)，要增加場效電晶體載子移動率係遇到困難，因此增加元件不穩定及/或失效的可能性。當閘極長度和元件間的間距縮小時，此問題會更為嚴重。
根據上述，本發明提供一種場效電晶體(field effect transistor，FET)，包括：一矽基底，包括一第一表面；一通道部分，位於第一表面上方，其中通道部分具有一第二表面，第二表面係位於第一表面上之第一高度，且該通道部分具 有平行該第一表面之一長度；及兩個源極/汲極區，位於第一表面上且沿著通道部分的長度包圍通道部分，其中上述源極/汲極區包括SiGe、Ge、Si、SiC、GeSn、SiGeSn、SiSn或III-V族材料。
本發明另一實施例係揭示一種半導體元件，包括：一矽基底，包括一第一表面；一第一通道部分和一第二通道部分，位於第一表面上方，其中各第一通道部分和第二通道部具有一第二表面，第二表面係位於第一表面上之第一高度，且通道部分之長度係平行第一表面；一第一場效電晶體，包括第一源極/汲極區，位於第一表面上，且沿著第一通道部分的長度包圍第一通道部分，其中第一源極/汲極區包括SiGe、Ge、GeSn、SiGeSn、SiSn或III-V族材料；及一第二場效電晶體，包括第二源極/汲極區，位於一第三表面上，且沿著二通道部分的長度包圍第二通道部分，其中第三表面係位於第一表面和第二表面間，且第二源極/汲極區包括SiGe、Si或SiC。
本發明又另一實施例係揭示一種場效電晶體(field effect transistor，FET)之製作方法，包括：提供一矽基底，包括一第一表面；形成一通道部分於第一表面上方；形成複數個凹處(cavities)，延伸穿過通道部分，且延伸入矽基底中；及於上述凹處中磊晶成長一應變材料。
20‧‧‧基底
20a‧‧‧第一區
20b‧‧‧第二區
20s‧‧‧第一表面
100‧‧‧方法
102‧‧‧步驟
104‧‧‧步驟
106‧‧‧步驟
108‧‧‧步驟
200‧‧‧半導體元件
202a‧‧‧第一鰭結構
202b‧‧‧第二鰭結構
204‧‧‧隔離區
204s‧‧‧STI表面
206a‧‧‧第一溝槽
206b‧‧‧第二溝槽
208a‧‧‧第一鍺通道
208b‧‧‧第二鍺通道
210a‧‧‧第一閘極堆疊
210b‧‧‧第二閘極堆疊
208s‧‧‧第二表面
212‧‧‧閘極介電層
214‧‧‧閘電極層
216a‧‧‧側壁間隙壁
216b‧‧‧側壁間隙壁
218a‧‧‧第一源極/汲極凹處
218b‧‧‧第二源極/汲極凹處
218c‧‧‧側壁
218d‧‧‧底部表面
218e‧‧‧側壁
218f‧‧‧底部表面
220‧‧‧感光層
222a‧‧‧源極/汲極區
222b‧‧‧源極/汲極區
228a‧‧‧第三凹處
230a‧‧‧應變結構
230b‧‧‧應變結構
300‧‧‧半導體元件
310‧‧‧圖案化虛設介電圖樣
318b‧‧‧第四源極/汲極凹處
318s‧‧‧第四表面
320‧‧‧虛設介電圖樣
322a‧‧‧S/D區
322b‧‧‧S/D區
328a‧‧‧第五S/D凹處
330‧‧‧應變結構
330a‧‧‧應變結構
330b‧‧‧應變結構
第1圖顯示本發明一實施例應變結構之製造方法的流程圖。
第2A-2G圖顯示包括本發明一實施例包括應變結構之半導體元件的製作方法各階段的剖面圖。
第3A-3D圖顯示包括本發明另一實施例包括應變結構之半導體元件的製作方法各階段的剖面圖。
以下詳細討論實施本發明之實施例。可以理解的是，實施例提供許多可應用的發明概念，其可以較廣的變化實施。所討論之特定實施例僅用來發明使用實施例的特定方法，而不用來限定發明的範疇。以下將針對特定實施例的構成與排列方式作簡要描述，當然，以下之描述僅是範例，但非用來限定本發明。此外，本發明在各範例中可能會出現重複的圖樣標號，但上述之重複僅是用來簡要和清楚的描述本發明，並不代表各實施範例和結構之間有必然關聯。
請參照第1圖，其顯示本發明一實施例應變結構之製造方法的流程圖。方法100以步驟102開始，提供一包括第一表面之矽基底。方法接著進行步驟104，形成一鍺通道於第一表面上方。方法接著進行步驟106，形成一凹處，延伸穿過鍺通道，且延伸入矽基底中。方法接著進行步驟108，於凹處中磊晶成長一應變材料。以下的討論係揭示根據第1圖之方法100之半導體元件製作的實施例。
第2A-2G圖顯示包括本發明一實施例包括應變結構230a之半導體元件200的製作方法。第3A-3D圖顯示包括本發明一實施例包括應變結構330a之半導體元件300的製作方法。在本揭示中，半導體元件200、300這個名詞係指鰭式場效電晶 體，鰭式場效電晶體為任何以鰭為主的多閘極電晶體。在另外的實施例中，半導體元件200、300這個名詞係指平面場效電晶體。半導體元件200、300可用於微處理器、記憶晶胞及/或其它積體電路。值得注意的是，第1圖之方法並沒有製作完整的半導體元件200、300。完整的半導體元件200、300可使用互補金屬氧化物半導體(CMOS)技術製程製作。因此，可了解的是，在第1圖之方法100之前、之中或之後可進行其它的製程，且其它的製程在此僅簡要的敘述。第2A圖至第3D圖係概要的描繪，以更容易了解本發明之概念。例如，雖然第2A圖至第3D圖僅描繪半導體元件200、300，可了解的是積體電路(IC)可包括其它的元件，包括電阻、電容、電感、熔絲等。
請參照第2A圖和第1圖之步驟102，提供一基底20。在一實施例中，基底20包括結晶矽基底(例如晶圓)。在另一實施例中，基底20可由其它的元素半導體材料(例如鑽石或鍺)；適合之化合物半導體(例如砷化鎵、碳化矽、砷化銦、磷化銦)；或適合之合金半導體(例如SiGeC、GaAsP或GaInP)。更甚者，基底20可包括一磊晶層，且其可施以應變以改善效能，及/或可包括絕緣層上有矽(SOI)結構。依設計的需求，基底20可包括各種的摻雜區，例如p型基底或n型基底。在一些實施例中，摻雜區可摻雜p型或n型摻雜物。例如，摻雜區可摻雜p型摻雜物，例如硼或BF2，摻雜區可摻雜n型摻雜物例如磷或砷，及/或上述之組合。摻雜區可用來形成n型場效電晶體，或p型場效電晶體。
在所揭示的實施例中，基底20包括一第一區20a和 一第二區20b。在半導體元件200實施例中，第一區20a係指核心區，其中可形成核心元件。第二區20b係指週邊區，其中可形成輸入/輸出(I/O)元件。在一些實施例中，核心元件和輸入/輸出(I/O)元件皆為p型場效電晶體。在一些實施例中，核心元件和輸入/輸出(I/O)元件皆為n型場效電晶體。在半導體元件300實施例中，第一區20a係指第一核心區，其中可形成第一核心元件。第二區20b係指第二核心區，其中可形成第二核心元件。在所揭示之實施例中，第一核心元件係為p型場效電晶體，第二核心元件係為n型場效電晶體。在半導體元件300之又另一實施例中，第一區20a係指第一核心區，其中可形成第一核心元件，第二區20b係指週邊區，其中可形成輸入/輸出(I/O)元件。在所揭示的實施例中，第一核心元件是p型場效電晶體，而輸入/輸出(I/O)元件是n型場效電晶體。
在形成鰭式場效電晶體之實施例中，基底20包括位於第一區20a之第一鰭結構202a和位於第二區20b之第二鰭結構202b。形成於基底20上之各第一鰭結構202a和第二鰭結構202b包括一或多個鰭。在所揭示之實施例中，為簡化，各第一鰭結構和第二鰭結構包括單一鰭。
第一鰭結構202a和第二鰭結構202b係使用任何適合的製程形成，包括各種的沉積、微影及/或蝕刻製程。一示範的微影製程可包括形成一光阻層於基底20(例如矽層)上；將光阻曝光成一圖案；進行一曝光後烘烤製程；且對光阻進行顯影以形成包括光阻之罩幕單元。後續可對矽層進行一蝕刻製程，例如反應離子蝕刻(reactive ion etching，RIE)製程及/或其 它適合的製程。在一範例中，第一鰭結構202a和第二鰭結構202b之矽鰭可以圖案化和蝕刻部分的矽基底20形成。在另一範例中，第一鰭結構202a和第二鰭結構202b之矽鰭可以圖案化和蝕刻沉積於一絕緣層上的矽層(例如絕緣層上有矽SOI基底之矽-絕緣層-矽之上矽層)形成。
在揭示的實施例中，隔離區係形成於基底20中，以定義和電性隔離第一鰭結構202a和第二鰭結構202b。在一範例中，隔離區包括淺溝槽隔離區204(shallow trench isolation，簡稱STI)。隔離區204可包括氧化矽、氮化矽、氮氧化矽、摻氟矽玻璃(FSG)、低介電常數材料及/或上述之組合。隔離區204(本實施例之STI區)可使用任何適合的製程形成。在一範例中，STI區之形成可包括以一介電材料填入第一和第二鰭結構202a、202b間的溝槽(例如使用化學氣相沉積法)。在一些實施例中，填入之溝槽可具有多層結構，例如熱氧化襯層上填入氮化矽或氧化矽。在所揭示的實施例中，STI區204包括STI表面204s。
請參照第2B圖和第1圖之步驟102，凹陷化第一鰭結構202a之上方部分，以於STI表面204s下形成第一溝槽206a，同時凹陷化第二鰭結構202b之上方部分，以於STI表面204s下形成第二溝槽206b。在本實施例中，各第一和第二鰭結構202a、202b暴露的表面定義一第一表面20s。在一示範的實施例中，第一和第二溝槽206a、206b的高度H可為20nm至70nm。然而，熟悉本技術領域的人士可了解，所有本說明書的尺寸和數值僅是範例，其可因應不同大小的積體電路而改變。
在所揭示的實施例中，使用STI區204作為硬式罩幕，進行一偏壓蝕刻製程，以凹陷第一鰭結構202a，形成第一溝槽206a，且凹陷第二鰭結構202b，形成第二溝槽206b。在一實施例中，蝕刻製程可以下述條件進行：壓力約為1 mTorr至1000 mTorr，功率約為50W至1000W，偏壓(bias voltage)約為20V至500V，溫度約為40℃至60℃，使用HBr及/或Cl2作為蝕刻氣體。在一些實施例中，可調整蝕刻製程施加之偏壓，以使蝕刻方向有較佳的控制，使溝槽206a、206b達成預定的輪廓。
方法100接著進行步驟104，藉由於第一表面20s上方形成一第一鍺通道208a和一第二鍺通道208b，以製作第2C圖之結構，其中各第一鍺通道208a和第二鍺通道208b在第一表面20s上之第一高度H1具有一第二表面208s，且其具有平行第一表面20s的長度L。
當選擇形成通道區之半導體材料時，考量點包括半導體材料之特性，例如接面正向電壓(junction forward voltage)、電子和電洞移動率、漏電流程度、半導體材料和其它材料(例如氧化物材料)界面品質。鍺之電子移動率較矽之電子移動率高。因此，在揭示的實施例中，半導體元件200之通道區使用鍺。在一些實施例中，形成通道區之半導體材料除了鍺以外，包括砷化鎵、碳化矽、砷化銦或磷化銦，或適合之合金半導體，例如SiGeC、GaAsP或GaInP。
在一實施例中，鍺磊晶製程可以下列條件進行：壓力約為10 mTorr至100 mTorr，溫度約為350℃至450℃，使用GeH4、GeH3CH3及/或(GeH3)2CH2作為磊晶氣體。在磊晶製程 後，可選擇性的進行一退火製程(溫度約為550℃至750℃，以使差排缺陷(dislocation defect)限制於矽和鍺磊晶層之界面。在形成平面場效電晶體(未繪示)之實施例中，因為僅需要表面通道，部分之STI 204係保留。在一形成鰭式場效電晶體之實施例中，部分之STI 204區係藉由HF溶液移除，以暴露鍺磊晶層(於第2D圖顯示)，其中磊晶層係作為半導體元件200、300之鍺通道。
請參照第2D圖，在形成第一和第二鍺通道208a、208b於第一表面20s上之後，形成第一閘極堆疊210a於第一鍺通道208a之第二表面208s上，同時形成第二閘極堆疊210b於第二鍺通道208b之第二表面208s上。在所揭示的實施例中，各第一和第二閘極堆疊210a、210b包括一閘極介電層212和一閘電極層214。第一和第二閘極堆疊210a、210b可以任何適合之製程(包括以上所述之製程)形成。
在一範例中，閘極介電層212和閘電極層214係依序形成基底20上方。在一些實施例中，閘極介電層212可包括氧化矽、氮化矽、氮氧化矽或高介電常數材料。高介電常數包括金屬氧化物，其包括以下金屬之氧化物：Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu或上述之混合。在此實施例中，閘極介電層212是高介電常數層，其厚度約為10埃~30埃。閘極介電層212可使用適合之製程形成，例如原子層沉積法(ALD)、化學氣相沉積法(CVD)、物理相沉積法(PVD)、熱氧化法、紫外線-臭氧氧化法(UV-ozone oxidation)或上述之結合。閘極介 電層212可更包括一中間層(未繪示)，以減少閘極介電層212和鰭結構202a、202b間的損壞。中間層可包括氧化矽。
在一些實施例中，閘電極層214可包括單一層或複數層。在此實施例中，閘電極層214可包括多晶矽。更甚著，閘電極層214可以是摻雜之多晶矽，其可具有均勻或非均勻之摻雜。在另一些實施例中，閘電極層214可包括之金屬例如為(Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlN、TaN、NiSi、CoSi)或其它功函數可與基底材料相容之導電材料，或上述之組合。在此實施例中，閘電極層214之厚度約為30nm至60nm。閘電極層214可使用適合之製程形成，例如原子層沉積法(ALD)、化學氣相沉積法(CVD)、物理相沉積法(PVD)、電鍍法或上述之組合。
後續，以適合之製程(例如旋轉塗佈法)形成一光阻層(未繪示)於閘電極層214上方，且以適合之微影圖案化方法將其圖案化以形成圖案化光阻圖樣。在至少一實施例中，圖案化光阻圖樣之寬度約為5至45nm。圖案化光阻圖樣之圖案可使用乾蝕刻製程轉印至其下之層(亦即閘電極層214和閘極介電層212)，以形成第一和第二閘極堆疊210a、210b。光阻層可在後續步驟移除。
在另一範例中，一硬式罩幕層(未繪示)係形成於閘電極層214上；一圖案化光阻層(未繪示)係形成於硬式罩幕層上；光阻層之圖案係轉印至硬式罩幕層，且後續轉印至閘電極層214和閘極介電層212，以形成第一和第二閘極堆疊210a、210b。硬式罩幕層包括氧化矽。在一些另外的實施例中，硬式 罩幕層可選擇性的包括氮化矽、氮氧化矽及/或其它適合之介電材料，且可使用例如化學氣相沉積法(CVD)或物理相沉積法(PVD)形成。硬式罩幕層之厚度可以為100埃至800埃。光阻層可在後續步驟移除。
請參照第2D圖，半導體元件200更包括一對側壁間隙壁216a，位於第一閘極堆疊210a之兩側，一對側壁間隙壁216b，位於第二閘極堆疊210b之兩側。在一些實施例中，側壁間隙壁216a係藉由首先形成一介電層於第一和第二閘極堆疊210a、210b上形成。介電層可包括氧化矽、氮化矽、氮氧化矽或其它適合之材料。介電層可包括單一層或多層結構。介電層可原子層沉積法(ALD)、化學氣相沉積法(CVD)、物理相沉積法(PVD)或其它適合之技術形成。介電層之厚度約為5至15nm。後續，於介電層上進行一非等向性蝕刻製程，以於第一閘極堆疊210a之兩側形成一對側壁間隙壁216a，於第二閘極堆疊210b之兩側形成一對側壁間隙壁216b。
請參照第2E圖，在形成第一和第二閘極堆疊210a、210b之後，凹陷化部分之第一和第二鍺通道208a、208b(除了第一和第二閘極堆疊210a、210b和側壁間隙壁216a、216b形成之部位以外)，以於第一鍺通道208a中形成第一源極/汲極凹處218a，並第二鍺通道208b中形成第二源極/汲極凹處218b。第一和第二源極/汲極凹處218a、218b均位於第一表面20s和第二表面208s間。在所揭示之實施例中，第一源極/汲極凹處218a係鄰接第一閘極堆疊210a，而第二源極/汲極凹處218b係鄰接第二閘極堆疊210b，其中由第一鍺通道208a形 成之各第一源極/汲極凹處218a包括一側壁218c和一底部表面218d，且其中由第二鍺通道208b形成之各第二源極/汲極凹處218b包括一側壁218e和一底部表面218f。在另一實施例中，鍺通道208a、208b並非如第2E圖所示全部都凹陷。
在所揭示之實施例中，係進行一偏壓蝕刻製程(使用上述側壁間隙壁216a、216b作為硬式罩幕層)，以凹陷至少未被保護或暴露之部分第一和第二鍺208a、208b之第二表面208s，以形成第一和第二源極/汲極凹處218a、218b。在一實施例中，可使用NF3、CF4或SF6之化學物品為蝕刻氣體，進行上述蝕刻製程。在另一實施例中，蝕刻製程可使用包括NH4OH和H2O2之溶液。
進行至此之製程步驟係於第一表面20s和第二表面208s間提供第一和第二源極/汲極凹處218a、218b。在一些構造中，係使用金屬有機化學氣相沉積法(MOCVD)，於第一鍺通道208a之第一凹處218a中沿著側壁208c和底部表面208d選擇性成長例如GaAs之應變材料。然而，使用金屬有機化學氣相沉積法(MOCVD)，應變材料之成長製程並未獲得良好的控制。
因此，使用金屬有機化學氣相沉積法(MOCVD)會於凹處218a中產生不均勻分佈之應變材料。由於應變材料之晶格常數不同於第一鍺通道208a之晶格常數，半導體元件之通道區會產生應變或應力，而增進元件之載子的移動率。然而，應變材料於凹處218a中不均勻的分佈會導致施加於半導體元件之通道區非均勻的應變。因此，應變材料可能無法傳遞半導體元件之通道區一特定量的應變，導致半導體元件之開啟電流 (on-current)不足。
因此，以下參照第2F-2G圖和第3A-3D圖討論之製程可形成穿過鍺通道，延伸入矽基底之凹處。凹處中係填入包括SiGe層之應變結構。應變結構可減少應變材料的不均勻分佈，藉以傳遞半導體元件之通道區一特定量的應變，而可避免半導體元件之開啟電流(on-current)不足之相關問題，藉以增進元件效能。
為了製作第2G圖所示之半導體元件200之應變結構230的實施例，第2F圖之實施例係以深凹處圖案化製程製作(deep-cavity patterning process)(第1圖之步驟106)。深凹處圖案化製程可包括以下製程：於基底20上方形成一感光層220；後續圖案化感光層220，以暴露出對第一鍺通道208a之第一源極/汲極凹處218a，而覆蓋第二鍺通道208b之第二源極/汲極凹處218b。
在所揭示的實施例中，使用圖案化感光層220、第一閘極堆疊210a和STI 204區作為罩幕，進一步蝕刻第一鍺通道208a露出之第一源極/汲極凹處218a，形成延伸穿過第一鍺通道208a且延伸至矽基底20之第三凹處228a。在一實施例中，蝕刻製程可使用包括NF3、CF4或SF6之化學物品的蝕刻氣體。在另一實施例中，蝕刻製程可使用包括NH4OH和H2O2之化學物品的溶液。在對第二鍺通道208b之第二源極/汲極凹處218b進行曝光之後，可移除圖案化感光層220。
請參照第2G圖和第1圖之步驟108，在形成延伸穿過第一鍺通道208a且延伸至矽基底20之第三凹處228a之後，於 第二源極/汲極凹處218b中磊晶成長一應變材料，形成源極/汲極區222b，且於第三源極/汲極凹處228a中磊晶成長一應變材料，形成源極/汲極區222a，製作第2G圖之結構。應變材料可包括SiGe、Ge、Si、SiC、GeSn、SiGeSn、SiSn、III-V族材料。
在所揭示之實施例中，可進行一預清洗製程，以HF或其它適合之溶液清洗第二和第三源極/汲極凹處218b、228a。後續，以低壓化學氣相沉積法(LPCVD)製程選擇性成長例如SiGe之應變材料，填入第二和第三源極/汲極凹處218b、228a。在揭示的實施例中，LPVCD之製程條件如下：溫度約為為660℃至700℃，壓力大體上為13 Torr至50 Torr，且使用SiH2Cl2、HCl、GeH4、B2H6和H2作為反應氣體。SiH2Cl2質量流率(mass flow rate)與HCl質量流率的比值大體上為0.8至1.5。SiH2Cl2質量流率與GeH4質量流率的比值大體上為10至50。
在第一區20a(或稱為核心區)中，兩源極/汲極區222a係形成於第一表面20s(虛線)上，且包夾第一鍺通道208a之上方部分和長度為La之通道208a。在一些實施例中，從第二表面208s向下延伸之兩源極/汲極區222a係與第一表面20s(虛線)共平面。在一些實施例中，從第二表面208s向下延伸之兩源極/汲極區222a係低於第一表面20s。如此，部分從第二表面208s向下延伸之兩源極/汲極區222a具有一第二高度H2，其等於或大於第一高度H1。在一些實施例中，第二高度與第一高度之比值為1~1.2。上述兩個源極/汲極區222a係結合且稱為一應變結構230a。與使用金屬有機化學氣相沉積法(MOCVD)之應變 結構230a相比較，應變結構230a具有較佳的均勻度，藉以傳遞半導體元件200之通道區一特定量的應變，以增進元件效能。
在第二區20b(或稱為週邊區)中，兩源極/汲極區222b係形成於第二鍺通道208b上，且包夾第二鍺通道208b(通道之長度為Lb)之上方部分。上述兩個源極/汲極區222b係結合且稱為一應變結構230b。在一些實施例中，核心元件(或輸入/輸出元件)包括N型金氧半導體場效電晶體(NMOS)和P型金氧半導體場效電晶體(PMOS)。在一些實施例中，若應變材料包括SiGe、Ge、GeSn、SiGeSn、SiSn或III-V族材料，核心元件和輸入/輸出元件兩者皆為P型金氧半導體場效電晶體(PMOS)。在一些實施例中，若應變材料包括SiGe、Si、或SiC，核心元件和輸入/輸出元件兩者皆為N型金氧半導體場效電晶體(NMOS)。
在另一些實施例中，為製作另一實施例之半導體元件300的應變結構330(第3D圖所示)，第3A圖的結構顯示第二鍺通道208b凹陷，於第二鍺通道208b中形成第四源極/汲極凹處318b後之半導體元件300(第2D圖之200)。在此實施例中，第3A至3D圖之半導體元件300係在係在形成第2D圖之半導體元件200後製作。因此，為清楚和簡潔，第2D圖與第3A至3D圖類似的圖樣使用相同的標號。在所揭示的實施例中，第四源極/汲極凹處318b係鄰接第二閘極堆疊210b，其中第二鍺通道208b中之各第四源極/汲極凹處318b具有一第四表面318s。第四表面318s係位於第一表面20s和第二表面208s之間。
在所揭示的實施例中，一包括例如氧化矽材料之 虛設介電圖樣310係藉由化學氣相沉積法製程形成於基底20上方，且其係藉由適當的微影和蝕刻製程圖案化，形成虛設介電圖樣310。圖案化之虛設介電圖樣覆蓋第一鍺通道208a，且暴露部分的第二鍺通道208b(第二閘極堆疊210b和該對側壁間隙壁216b形成於上方之部分除外)。後續，使用圖案化虛設介電圖樣310和該對側壁間隙壁216b作為硬式罩幕，進行一偏壓蝕刻製程，使未被保護的或暴露的第二鍺通道208b之第二表面208s凹陷，以於第一表面20s和第二表面208s間形成第四源極/汲極凹處318b。在一實施例中，蝕刻製程可使用NF3、CF4或SF6之化學物品作為蝕刻氣體。在另一實施例中，蝕刻製程可使用包括NH4OH和H2O2之溶液進行蝕刻。在一些實施例中，可略過第2E圖揭示之凹陷第二鍺通道208b之步驟。在另一實施例中，可略過第2E圖之凹陷鍺通道208a、208b之步驟。
請參照第3B圖，在形成第一表面20s和第二表面208s間之第四S/D凹處318b之後，兩個S/D區322b係磊晶成長於第四表面318s上，且包夾第二鍺通道208b之上方部分具有長度Ld之第二鍺通道208b。在一實施例中，從第二表面208s向下延伸之部分的兩個S/D區322b具有一第三高度H3，第三高度H3小於第一高度H1。在另一實施例中，第三高度與第一高度之比值為0.5至0.9。在所揭示的實施例中，兩個S/D區322b係結合，且稱為一應變結構330b。在一些實施例中，兩個S/D區322b包括SiGe、Si或SiC。藉此，第二區20b中的兩個S/D區322b係指n型場效電晶體之核心區或n型I/O場效電晶體之週邊區。
在揭示的實施例中，可進行一預清洗製程，以HF 或其它適合之溶液清洗第四S/D凹處318b。後續，以低壓化學氣相沉積法(LPCVD)製程，選擇性成長例如SiC之應變材料，填入第四S/D凹處318b。在揭示的實施例中，低壓化學氣相沉積法(LPCVD)製程以下列條件進行：溫度大體上為400℃至800℃，壓力大體上為1 Torr至15 Torr，且使用SiH4、CH4和H2作為反應氣體。後續使用HF溶液移除圖案化虛設介電圖樣310。
請參照第3C圖和第1圖所揭示之步驟106，在於第四表面318s上形成兩個S/D區322b之後，藉由凹陷第一鍺通道208a製作第3C圖的結構，形成第五S/D凹處328a，延伸穿過第一鍺通道208a且延伸入矽基底20中。在揭示的實施例中，第五S/D凹處328a之分佈係鄰接第一閘極堆疊210a。
在揭示的實施例中，例如氧化矽之虛設閘極介電層係藉由化學氣相沉積製程形成於基底20上方，且以適合之微影和蝕刻製程將其圖案化，形成虛設介電圖樣320。圖案化虛設介電圖樣320覆蓋第二鍺通道208b，且暴露部分的第一鍺通道208a(第一閘極堆疊210a和該對側壁間隙壁216a形成於上方之部分除外)。後續，使用圖案化虛設介電圖樣320和該對側壁間隙壁216a作為硬式罩幕，進行一偏壓蝕刻製程，使未被保護的或暴露的第一鍺通道208a之第二表面208s凹陷，以形成第五源極/汲極凹處328a。在至少一實施例中，蝕刻製程可使用包括NF3、CF4或SF6之化學物的蝕刻氣體。在另一實施例中，蝕刻製程可使用包括NH4OH和H2O2之化學物的蝕刻氣體。
請參照第3D圖和第1圖之步驟108，在形成延伸穿過第一鍺通道208a和延伸入矽基底20之第五源極/汲極凹處 328a後，於第五S/D凹處328a中磊晶成長應變材料，製作第3D圖之結構，形成S/D區322a。應變材料可包括SiGe、Ge、GeSn、SiGeSn、SiSn或III-V族材料。
在揭示之實施例中，可進行一預清洗製程，以HF或其它適合之溶液清洗第五源極/汲極凹處328a。後續，以低壓化學氣相沉積法(LPCVD)製程選擇性成長例如SiGe之應變材料，填入第五源極/汲極凹處328a。在一實施例中，低壓化學氣相沉積法(LPCVD)之製程條件如下：溫度約為為660℃至700℃，壓力大體上為13 Torr至50 Torr，且使用SiH2Cl2、HCl、GeH4、B2H6和H2作為反應氣體。SiH2Cl2質量流率(mass flow rate)與HCl質量流率的比值大體上為0.8至1.5。SiH2Cl2質量流率與GeH4質量流率的比值大體上為10至50。
在第一區20a(或稱為核心區)中，兩源極/汲極區322a係形成於第一表面20s(虛線)上，且包夾第一鍺通道208a之上方部分長度為Lc之通道208a。在一些實施例中，從第二表面208s向下延伸之兩源極/汲極區322a係與第一表面20s(虛線)共平面。在一些實施例中，從第二表面208s向下延伸之兩源極/汲極區322a係低於第一表面20s。如此，部分從第二表面208s向下延伸之兩源極/汲極區322a具有一第四高度H4，其等於或大於第一高度H1。在一些實施例中，第四高度H4與第一高度H1之比值為1~1.2。上述兩個源極/汲極區322a係結合且稱為一應變結構330a。與使用金屬有機化學氣相沉積法(MOCVD)之應變結構330a相比較，應變結構330a具有較佳的均勻度，藉以傳遞半導體元件300之通道區一特定量的應變，以增進元件效能。
在進行第1圖所示之步驟之後，如第2A-2G圖、2A-2D圖和第3A-3D圖所更進一步的說明，一般會進行後續的製程(包括矽化製程和內連線製程)，以完成半導體元件200、300之製作。
本發明一實施例係揭示一種場效電晶體(field effect transistor，FET)，包括：一矽基底，包括一第一表面；一通道部分，位於第一表面上方，其中通道部分具有一第二表面，第二表面係位於第一表面上之第一高度，且該通道部分具有平行第一表面之一長度；及兩個源極/汲極區，位於第一表面上且沿著通道部分的長度包圍通道部分，其中上述源極/汲極區包括SiGe、Ge、Si、SiC、GeSn、SiGeSn、SiSn或III-V族材料。
本發明另一實施例係揭示一種半導體元件，包括：一矽基底，包括一第一表面；一第一通道部分和一第二通道部分，位於第一表面上方，其中各第一通道部分和第二通道部具有一第二表面，第二表面係位於第一表面上之第一高度，且通道部分之長度係平行第一表面；一第一場效電晶體，包括第一源極/汲極區，位於第一表面上，且沿著第一通道部分的長度包圍第一通道部分；及一第二場效電晶體，包括第二源極/汲極區，位於一第三表面上，且沿著二通道部分的長度包圍第二通道部分，其中第三表面係位於第一表面和第二表面間。
本發明又另一實施例係揭示一種場效電晶體(field effect transistor，FET)之製作方法，包括：提供一矽基底，包括一第一表面；形成一通道部分於第一表面上方；形成複數個 凹處(cavities)，延伸穿過通道部分，且延伸入矽基底中；及於 上述凹處中磊晶成長一應變材料。
雖然本發明之較佳實施例說明如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧基底
20a‧‧‧第一區
20b‧‧‧第二區
20s‧‧‧第一表面
200‧‧‧半導體元件
202a‧‧‧第一鰭結構
202b‧‧‧第二鰭結構
204‧‧‧隔離區
208a‧‧‧第一鍺通道
208b‧‧‧第二鍺通道
210a‧‧‧第一閘極堆疊
210b‧‧‧第二閘極堆疊
208s‧‧‧第二表面
212‧‧‧閘極介電層
214‧‧‧閘電極層
216a‧‧‧側壁間隙壁
216b‧‧‧側壁間隙壁
222a‧‧‧源極/汲極區
222b‧‧‧源極/汲極區
230a‧‧‧應變結構
230b‧‧‧應變結構

Claims (5)

  1. 一種半導體元件，包括：一矽基底，包括一第一表面；一第一通道部分和一第二通道部分，位於該第一表面上方，其中各該第一通道部分和第二通道部分具有一第二表面，該第二表面係位於該第一表面上之第一高度，且該通道部分之長度係平行該第一表面；一第一場效電晶體，包括第一源極/汲極區，位於該第一表面上，且沿著該第一通道部分之長度包圍該第一通道部分，其中該第一源極/汲極區包括SiGe、Ge、GeSn、SiGeSn、SiSn或III-V族材料；及一第二場效電晶體，包括第二源極/汲極區，位於一第三表面上，且沿著該第二通道部分的長度包圍該第二通道部分，其中該第三表面係位於該第一表面和該第二表面間，且該第二源極/汲極區包括SiGe、Si或SiC。
  2. 如申請專利範圍第1項所述之半導體元件，其中該第一源極/汲極區從該第二表面向下延伸之部分具有一第二高度，該第二高度等同或大於該第一高度。
  3. 如申請專利範圍第1項所述之半導體元件，其中該第二源極/汲極區從該第二表面向下延伸之部分具有一第三高度，該第三高度小於該第一高度。
  4. 如申請專利範圍第1項所述之半導體元件，其中該第一場效電晶體是p型場效電晶體，該第二場效電晶體是n型場效電晶體。
  5. 如申請專利範圍第1項所述之半導體元件，其中該第一場效電晶體是一核心元件(core device)，該第二場效電晶體是一輸入/輸出(I/O)元件。
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US10535735B2 (en) * 2012-06-29 2020-01-14 Intel Corporation Contact resistance reduced P-MOS transistors employing Ge-rich contact layer
US9123633B2 (en) * 2013-02-01 2015-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming semiconductor regions in trenches
KR20140106270A (ko) * 2013-02-26 2014-09-03 삼성전자주식회사 집적 회로 장치 및 그 제조 방법
US8900934B2 (en) 2013-04-18 2014-12-02 International Business Machines Corporation FinFET devices containing merged epitaxial Fin-containing contact regions
US9349730B2 (en) * 2013-07-18 2016-05-24 Globalfoundries Inc. Fin transformation process and isolation structures facilitating different Fin isolation schemes
US9553012B2 (en) 2013-09-13 2017-01-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and the manufacturing method thereof
EP3050088A4 (en) * 2013-09-25 2017-05-03 Intel Corporation Isolation well doping with solid-state diffusion sources for finfet architectures
FR3016235B1 (fr) 2014-01-08 2016-01-22 Commissariat Energie Atomique Procede de fabrication d'un dispositif microelectronique
US9236483B2 (en) 2014-02-12 2016-01-12 Qualcomm Incorporated FinFET with backgate, without punchthrough, and with reduced fin height variation
CN103811352A (zh) * 2014-02-25 2014-05-21 清华大学 具有GeSn源漏的MOSFET及其形成方法
CN103840005A (zh) * 2014-02-25 2014-06-04 清华大学 具有SiGeSn源漏的鳍式场效应晶体管及其形成方法
CN103839832A (zh) * 2014-02-25 2014-06-04 清华大学 具有GeSn源漏的鳍式场效应晶体管及其形成方法
CN103839980B (zh) * 2014-02-25 2017-01-18 清华大学 具有SiGeSn源漏的MOSFET及其形成方法
CN103840004A (zh) * 2014-02-25 2014-06-04 清华大学 具有SiGeSn源漏的鳍式场效应晶体管及其形成方法
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
US9502565B2 (en) 2014-06-27 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Channel strain control for nonplanar compound semiconductor devices
CN105304494B (zh) * 2014-07-25 2019-06-28 Imec 非营利协会 一种形成nmos晶体管装置的锗通道层、nmos晶体管装置和cmos装置的方法
KR102263045B1 (ko) 2014-07-25 2021-06-10 삼성전자주식회사 공통 스트레인-완화 버퍼를 구비하는 cmos 장치 및 그 제조 방법
US10854735B2 (en) 2014-09-03 2020-12-01 Taiwan Semiconductor Manufacturing Company Limited Method of forming transistor
US9818744B2 (en) 2014-09-04 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Leakage current suppression methods and related structures
KR102255174B1 (ko) 2014-10-10 2021-05-24 삼성전자주식회사 활성 영역을 갖는 반도체 소자 및 그 형성 방법
US10164108B2 (en) 2014-10-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9391201B2 (en) 2014-11-25 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structure and manufacturing the same
US9455195B2 (en) * 2014-12-05 2016-09-27 International Business Machines Corporation Method of forming performance optimized gate structures by silicidizing lowered source and drain regions
US9349652B1 (en) 2014-12-12 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device with different threshold voltages
US9780214B2 (en) 2014-12-22 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin- FET and manufacturing method thereof
US10141310B2 (en) 2014-12-23 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Short channel effect suppression
US9768301B2 (en) 2014-12-23 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Short channel effect suppression
US10134871B2 (en) 2014-12-23 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of high-K dielectric oxide by wet chemical treatment
US9515071B2 (en) 2014-12-24 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Asymmetric source/drain depths
US9425250B2 (en) 2014-12-30 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor with wurtzite channel
US9647090B2 (en) 2014-12-30 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Surface passivation for germanium-based semiconductor structure
US9601626B2 (en) 2015-01-23 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structure with two channel layers and manufacturing method thereof
US9443729B1 (en) 2015-03-31 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming FinFET devices
KR102339777B1 (ko) * 2015-04-14 2021-12-15 삼성전자주식회사 반도체 소자
US9590102B2 (en) 2015-04-15 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9680014B2 (en) 2015-04-17 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin structures and manufacturing method thereof
US9570557B2 (en) 2015-04-29 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Tilt implantation for STI formation in FinFET structures
US9461110B1 (en) 2015-04-30 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. FETs and methods of forming FETs
US9773786B2 (en) 2015-04-30 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. FETs and methods of forming FETs
EP3093881B1 (en) * 2015-05-13 2020-11-11 IMEC vzw Method for manufacturing a cmos device
US10269968B2 (en) 2015-06-03 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9647071B2 (en) 2015-06-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. FINFET structures and methods of forming the same
US9449975B1 (en) 2015-06-15 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices and methods of forming
US9425313B1 (en) 2015-07-07 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9953881B2 (en) 2015-07-20 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a FinFET device
US9472620B1 (en) 2015-09-04 2016-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9680017B2 (en) 2015-09-16 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin FET and manufacturing method thereof
US11222947B2 (en) 2015-09-25 2022-01-11 Intel Corporation Methods of doping fin structures of non-planar transistor devices
US10121858B2 (en) 2015-10-30 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated semiconductor structure planarization
US9960273B2 (en) 2015-11-16 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US9887269B2 (en) 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9564317B1 (en) 2015-12-02 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a nanowire
US9716146B2 (en) 2015-12-15 2017-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method with solid phase diffusion
EP3182461B1 (en) * 2015-12-16 2022-08-03 IMEC vzw Method for fabricating finfet technology with locally higher fin-to-fin pitch
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US9660033B1 (en) 2016-01-13 2017-05-23 Taiwan Semiconductor Manufactuing Company, Ltd. Multi-gate device and method of fabrication thereof
US9876098B2 (en) 2016-01-15 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a gate spacer
US10038095B2 (en) 2016-01-28 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. V-shape recess profile for embedded source/drain epitaxy
US10453925B2 (en) 2016-01-29 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth methods and structures thereof
US10644153B2 (en) * 2016-02-25 2020-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method for fabricating the same
WO2017151055A1 (en) * 2016-02-29 2017-09-08 Nanyang Technological University Optical structure and method of forming the same
TWI699885B (zh) 2016-03-22 2020-07-21 聯華電子股份有限公司 半導體結構與其製作方法
US10340383B2 (en) 2016-03-25 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having stressor layer
US10164061B2 (en) 2016-05-19 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating non-volatile memory device array
US10734522B2 (en) 2016-06-15 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure with gate stacks
US10008414B2 (en) 2016-06-28 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for widening Fin widths for small pitch FinFET devices
US9620628B1 (en) 2016-07-07 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming contact feature
US10269938B2 (en) 2016-07-15 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure having a doped passivation layer
US10217741B2 (en) 2016-08-03 2019-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure and method of forming same through two-step etching processes
US9853150B1 (en) 2016-08-15 2017-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating epitaxial gate dielectrics and semiconductor device of the same
US9865589B1 (en) 2016-10-31 2018-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. System and method of fabricating ESD FinFET with improved metal landing in the drain
US10840350B2 (en) 2016-10-31 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Nanolaminate structure, semiconductor device and method of forming nanolaminate structure
US11152362B2 (en) 2016-11-10 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure
US9847334B1 (en) 2016-11-18 2017-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with channel layer
US10879240B2 (en) 2016-11-18 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure
US10134870B2 (en) 2016-11-28 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method of manufacturing the same
US10164066B2 (en) 2016-11-29 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices and methods of forming
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10062782B2 (en) 2016-11-29 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device with multilayered channel structure
US9953875B1 (en) 2016-11-30 2018-04-24 Taiwan Semiconductor Manufacturing Company Contact resistance control in epitaxial structures of finFET
US11011634B2 (en) 2016-11-30 2021-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Elongated source/drain region structure in finFET device
US10707328B2 (en) 2016-11-30 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming epitaxial fin structures of finFET
US9865595B1 (en) 2016-12-14 2018-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same
US10002796B1 (en) 2016-12-15 2018-06-19 Taiwan Semiconductor Manufacturing Co., Ltd. Dual epitaxial growth process for semiconductor device
US9899273B1 (en) 2016-12-15 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with dopants diffuse protection and method for forming the same
US10347581B2 (en) 2017-03-22 2019-07-09 International Business Machines Corporation Contact formation in semiconductor devices
US10319722B2 (en) 2017-03-22 2019-06-11 International Business Machines Corporation Contact formation in semiconductor devices
US10163731B2 (en) 2017-04-12 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET semiconductor structure having hybrid substrate and method of fabricating the same
US10522643B2 (en) 2017-04-26 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate
US10522417B2 (en) 2017-04-27 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with different liners for PFET and NFET and method of fabricating thereof
US10050149B1 (en) 2017-05-18 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure for semiconductor device
US10636910B2 (en) 2017-05-30 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method of forming the same
US10163628B1 (en) 2017-05-31 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Lattice-mismatched semiconductor substrates with defect reduction
US9991262B1 (en) 2017-06-15 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device on hybrid substrate and method of manufacturing the same
US10141430B1 (en) 2017-07-27 2018-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures with uniform threshold voltage distribution and method of making the same
US10515952B2 (en) 2017-08-04 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure and method for forming the same
US10833152B2 (en) 2017-08-15 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10504898B2 (en) 2017-08-28 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field-effect transistor structure and method for forming the same
US10276445B2 (en) 2017-08-31 2019-04-30 Taiwan Semiconductor Manfacturing Co., Ltd. Leakage reduction methods and structures thereof
US10522680B2 (en) 2017-08-31 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Finfet semiconductor device structure with capped source drain structures
US10497577B2 (en) 2017-08-31 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method
US10453753B2 (en) 2017-08-31 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET
US10276718B2 (en) 2017-08-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having a relaxation prevention anchor
US10468275B2 (en) 2017-09-27 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor fabrication with electrochemical apparatus
US10516032B2 (en) 2017-09-28 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device
US10763114B2 (en) 2017-09-28 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating gate oxide of semiconductor device
US10403545B2 (en) 2017-09-28 2019-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Power reduction in finFET structures
US10283639B2 (en) 2017-09-28 2019-05-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method for forming the same
US10535736B2 (en) 2017-09-28 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Fully strained channel
US10804367B2 (en) 2017-09-29 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Gate stacks for stack-fin channel I/O devices and nanowire channel core devices
US10276697B1 (en) 2017-10-27 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance FET with improved reliability performance
US10535737B2 (en) 2017-10-27 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10325912B2 (en) 2017-10-30 2019-06-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure cutting process and structures formed thereby
US11444173B2 (en) 2017-10-30 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with salicide layer and method for forming the same
US10522418B2 (en) 2017-10-30 2019-12-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
US10522557B2 (en) 2017-10-30 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Surface topography by forming spacer-like components
US10276693B1 (en) 2017-10-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10629497B2 (en) 2017-11-02 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device structure and method for enlarging gap-fill window
US10707318B2 (en) 2017-11-15 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US10355102B2 (en) 2017-11-15 2019-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacturing the same
US10269576B1 (en) 2017-11-15 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Etching and structures formed thereby
US10483168B2 (en) 2017-11-15 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Low-k gate spacer and formation thereof
US10515948B2 (en) 2017-11-15 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including vertical routing structure and method for manufacturing the same
US10366915B2 (en) 2017-11-15 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices with embedded air gaps and the fabrication thereof
US10680106B2 (en) 2017-11-15 2020-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming source/drain epitaxial stacks
US10867859B2 (en) 2017-11-17 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of fabricating semiconductor devices having isolation structures with liners
US10269648B1 (en) 2017-11-17 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating a semiconductor device structure
US10867809B2 (en) 2017-11-22 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Laser anneal process
US10276449B1 (en) 2017-11-24 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming fin field effect transistor (FinFET) device structure
US10340190B2 (en) 2017-11-24 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US10361279B2 (en) 2017-11-24 2019-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing FinFET structure with doped region
US10510883B2 (en) 2017-11-28 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Asymmetric source and drain structures in semiconductor devices
US11183423B2 (en) 2017-11-28 2021-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Liner structure in interlayer dielectric structure for semiconductor devices
US10510889B2 (en) 2017-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. P-type strained channel in a fin field effect transistor (FinFET) device
US11114549B2 (en) 2017-11-29 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure cutting process and structures formed thereby
US10629749B2 (en) * 2017-11-30 2020-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of treating interfacial layer on silicon germanium
US10504899B2 (en) 2017-11-30 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Transistors with various threshold voltages and method for manufacturing the same
US10748774B2 (en) 2017-11-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10510894B2 (en) 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structure having different distances to adjacent FinFET devices
US10658225B2 (en) 2018-01-19 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices and methods of forming the same
US10468409B2 (en) 2018-03-14 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with oxidation-resist STI liner structure
US10749007B2 (en) 2018-03-14 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure with desired profile for semiconductor devices
US11056392B2 (en) 2018-03-29 2021-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices having gate stacks with protruding parts and method of forming the same
US10854615B2 (en) 2018-03-30 2020-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having non-merging epitaxially grown source/drains
US10763363B2 (en) 2018-04-10 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gradient doped region of recessed fin forming a FinFET device
US10854715B2 (en) 2018-04-13 2020-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Supportive layer in source/drains of FinFET devices
KR102546305B1 (ko) * 2018-04-20 2023-06-21 삼성전자주식회사 집적회로 소자
US11398476B2 (en) 2018-05-16 2022-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with hybrid fins
US10529414B2 (en) 2018-05-31 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. SRAM cell having SiGe PMOS fin lines
CN110571259B (zh) * 2018-06-05 2023-04-07 中芯国际集成电路制造(上海)有限公司 Finfet器件及其制备方法
US10665697B2 (en) 2018-06-15 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10522662B1 (en) 2018-06-22 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with T-shaped fin and method for forming the same
US10535570B1 (en) 2018-06-22 2020-01-14 International Business Machines Corporation Cointegration of III-V channels and germanium channels for vertical field effect transistors
US11302535B2 (en) 2018-06-27 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Performing annealing process to improve fin quality of a FinFET semiconductor
US10790352B2 (en) 2018-06-28 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. High density capacitor implemented using FinFET
US10388771B1 (en) 2018-06-28 2019-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method and device for forming cut-metal-gate feature
US11355339B2 (en) 2018-06-29 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Forming nitrogen-containing layers as oxidation blocking layers
US11011623B2 (en) 2018-06-29 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for increasing germanium concentration of FIN and resulting semiconductor device
US11437497B2 (en) 2018-06-29 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10998310B2 (en) 2018-07-09 2021-05-04 Taiwan Semiconductor Manufacturing Company Ltd. Fins with wide base in a FINFET
US11205700B2 (en) 2018-07-16 2021-12-21 Taiwan Semiconductor Manufacturing Co., Ltd. Air gap spacer and related methods
US11276695B2 (en) 2018-07-16 2022-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
US11271111B2 (en) 2018-07-26 2022-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain structure with barrier in FinFET device and method for forming the same
US10672879B2 (en) 2018-07-30 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming FinFET and gate-all-around FET with selective high-K oxide deposition
US10535667B1 (en) 2018-07-30 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array and semiconductor chip
US11158644B2 (en) 2018-07-31 2021-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with field effect transistors of differing gate dielectric thickness on the same substrate and method of manufacturing the same
US11158727B2 (en) 2018-07-31 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for gate-all-around device with extended channel
US11069692B2 (en) 2018-07-31 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET SRAM cells with dielectric fins
US11227918B2 (en) 2018-07-31 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Melt anneal source and drain regions
US11114303B2 (en) 2018-07-31 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Gate all around device, method for manufacturing FinFET device, and method for manufacturing gate all around device
US10679995B2 (en) 2018-07-31 2020-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11211293B2 (en) 2018-07-31 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and methods of forming the same
US10886226B2 (en) 2018-07-31 2021-01-05 Taiwan Semiconductor Manufacturing Co, Ltd. Conductive contact having staircase barrier layers
US11049775B2 (en) 2018-07-31 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having FinFET with work function layers and method of manufacturing the same
US10741558B2 (en) 2018-08-14 2020-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Nanosheet CMOS device and method of forming
US11211479B2 (en) 2018-08-14 2021-12-28 Taiwan Semiconductor Manufaciuring Co., Ltd. Method of fabricating trimmed fin and fin structure
US11037837B2 (en) 2018-08-15 2021-06-15 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial source/drain and methods of forming same
US10867862B2 (en) 2018-08-31 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor method and device
US10714395B2 (en) 2018-09-18 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Fin isolation structure for FinFET and method of forming the same
US10998241B2 (en) 2018-09-19 2021-05-04 Taiwan Semiconductor Manufacturing Co., Ltd. Selective dual silicide formation using a maskless fabrication process flow
US11018012B2 (en) 2018-09-21 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structures with deposited silicide layers
US11437385B2 (en) 2018-09-24 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET SRAM cells with reduced fin pitch
US11217585B2 (en) 2018-09-25 2022-01-04 Taiwan Semiconductor Manufacturing Co., Ltd. Forming dielectric dummy fins with different heights in different regions of a semiconductor device
US11094826B2 (en) 2018-09-27 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
US10840152B2 (en) 2018-09-27 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10804162B2 (en) 2018-09-27 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Dual channel gate all around transistor device and fabrication methods thereof
US11349008B2 (en) 2018-09-27 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance transistor having a multilayer ferroelectric structure or a ferroelectric layer with a gradient doping profile
US11450571B2 (en) 2018-09-27 2022-09-20 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
US11094597B2 (en) 2018-09-28 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with fin structures
US11289583B2 (en) 2018-09-28 2022-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. High aspect ratio gate structure formation
US11222958B2 (en) 2018-09-28 2022-01-11 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance transistor with external ferroelectric structure
US11264237B2 (en) 2018-09-28 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of epitaxy and semiconductor device
DE102019117897B4 (de) 2018-09-28 2024-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung zur logik- und speicher-co-optimierung sowie schaltung
US11069812B2 (en) 2018-09-28 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method of forming the same
US11088262B2 (en) 2018-09-28 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Radical etching in gate formation
US10790184B2 (en) 2018-09-28 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation with multi-step structure for FinFET device and method of forming the same
US10763863B2 (en) 2018-09-28 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device for logic and memory co-optimization
US11121036B2 (en) 2018-10-16 2021-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
US10971605B2 (en) 2018-10-22 2021-04-06 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy dielectric fin design for parasitic capacitance reduction
US11107904B2 (en) 2018-10-23 2021-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Inner spacer formation in multi-gate transistors
US10872906B2 (en) 2018-10-25 2020-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11133222B2 (en) 2018-10-26 2021-09-28 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
US10847426B2 (en) 2018-10-28 2020-11-24 Taiwan Semicondutor Manufacturing Company, Ltd. FinFET devices and methods of forming the same
US10916550B2 (en) 2018-10-30 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Memory devices with gate all around transistors
US10868114B2 (en) 2018-10-30 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structures of semiconductor devices
US10811255B2 (en) 2018-10-30 2020-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming semiconductor devices
US11087987B2 (en) 2018-10-31 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11257928B2 (en) 2018-11-27 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for epitaxial growth and device
US11031291B2 (en) 2018-11-28 2021-06-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of forming the same
US11685015B2 (en) 2019-01-28 2023-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method and system for performing chemical mechanical polishing
US11217526B2 (en) 2019-02-28 2022-01-04 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with source resistor and manufacturing method thereof
US10978354B2 (en) 2019-03-15 2021-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Selective dual silicide formation
US11239339B2 (en) 2019-04-29 2022-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and method
US11088255B2 (en) 2019-05-17 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices
US11088034B2 (en) 2019-05-22 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structures for semiconductor devices
US11183574B2 (en) 2019-05-24 2021-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Work function layers for transistor gate electrodes
US11107923B2 (en) 2019-06-14 2021-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain regions of FinFET devices and methods of forming same
US10971402B2 (en) 2019-06-17 2021-04-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including interface layer and method of fabricating thereof
US11682665B2 (en) 2019-06-19 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor layout with different row heights
US11373870B2 (en) 2019-06-27 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor device including performing thermal treatment on germanium layer
US11728344B2 (en) 2019-06-28 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid SRAM design with nano-structures
US11411112B2 (en) 2019-07-31 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure, method of forming the same, and semiconductor device having the same
US11245029B2 (en) 2019-08-22 2022-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with metal gate stack
US10978344B2 (en) 2019-08-23 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Melting laser anneal of epitaxy regions
US11515199B2 (en) 2019-08-26 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structures including standard cells and tap cells
US11133386B2 (en) 2019-08-27 2021-09-28 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-layer fin structure
US11315925B2 (en) 2019-08-28 2022-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Uniform gate width for nanostructure devices
US11282942B2 (en) 2019-08-30 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with uniform threshold voltage distribution and method of forming the same
US11545573B2 (en) 2019-09-10 2023-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid nanostructure and fin structure device
US11114547B2 (en) 2019-09-17 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistor with negative capacitance dieletric structures
US11342231B2 (en) 2019-09-17 2022-05-24 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device with low threshold voltage
US11177344B2 (en) 2019-09-25 2021-11-16 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device with air gap spacer and fabrication methods thereof
US11621224B2 (en) 2019-09-26 2023-04-04 Taiwan Semiconductor Manufacturing Co. Ltd. Contact features and methods of fabricating the same in semiconductor devices
US11469238B2 (en) 2019-09-26 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Non-interleaving N-well and P-well pickup region design for IC devices
US11322409B2 (en) 2019-09-26 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate devices and method of fabricating the same
US11482610B2 (en) 2019-09-26 2022-10-25 Taiwan Semiconductor Manufacturing Co. Method of forming a gate structure
US11282748B2 (en) 2019-09-26 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same
US11443980B2 (en) 2019-09-27 2022-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device with metal pad extending into top metal layer
US11031292B2 (en) 2019-09-29 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
US11374104B2 (en) 2019-09-30 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of reducing capacitance in field-effect transistors
US10937704B1 (en) 2019-10-01 2021-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Mixed workfunction metal for nanosheet device
US11296227B2 (en) 2019-10-16 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
US11145650B2 (en) 2019-10-18 2021-10-12 Taiwan Semiconductor Manufacturing Co., Ltd. Gate cut dielectric feature and method of forming the same
US11322495B2 (en) 2019-10-28 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Complementary metal-oxide-semiconductor device and method of manufacturing the same
US11183591B2 (en) * 2019-10-30 2021-11-23 Avago Technologies International Sales Pte. Ltd. Lateral double-diffused metal-oxide-semiconductor (LDMOS) fin field effect transistor with enhanced capabilities
US11374090B2 (en) 2019-10-31 2022-06-28 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structures for semiconductor devices
DE102020110789B4 (de) 2019-10-31 2024-10-31 Taiwan Semiconductor Manufacturing Co. Ltd. Gate-strukturen für halbleitervorrichtungen und verfahren zum herstellen einer halbleitervorrichtung
US10964792B1 (en) 2019-11-22 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Dual metal capped via contact structures for semiconductor devices
US11233134B2 (en) 2019-12-19 2022-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistors with dual silicide contact structures
US11075195B2 (en) 2019-12-26 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated hybrid standard cell structure with gate-all-around device
US11380548B2 (en) 2019-12-30 2022-07-05 Taiwan Semiconductor Manufacturing Company Ltd. Method of manufacturing semiconductor structure through multi-implantation to fin structures
US11302692B2 (en) 2020-01-16 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same
US11309419B2 (en) 2020-01-17 2022-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11244899B2 (en) 2020-01-17 2022-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Butted contacts and methods of fabricating the same in semiconductor devices
US11521969B2 (en) 2020-01-29 2022-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structures for semiconductor devices
DE102020120099B4 (de) 2020-01-29 2024-07-25 Taiwan Semiconductor Manufacturing Co. Ltd. Verfahren zur herstellung von isolationsstrukturen für halbleitervorrichtungen
US11417764B2 (en) 2020-01-29 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Interface profile control in epitaxial structures for semiconductor devices
US11245028B2 (en) 2020-01-30 2022-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structures of semiconductor devices
US11563110B2 (en) 2020-01-30 2023-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method for forming the same
US11610822B2 (en) 2020-01-31 2023-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Structures for tuning threshold voltage
US11705372B2 (en) 2020-02-11 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Fin loss prevention
US11177180B2 (en) * 2020-02-11 2021-11-16 Taiwan Semiconductor Manufacturing Co., Ltd. Profile control of a gap fill structure
US11328963B2 (en) 2020-02-27 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
CN113130483A (zh) 2020-02-27 2021-07-16 台湾积体电路制造股份有限公司 半导体结构
US11799019B2 (en) 2020-02-27 2023-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Gate isolation feature and manufacturing method thereof
US11233119B2 (en) 2020-03-02 2022-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Core-shell nanostructures for semiconductor devices
US11695055B2 (en) 2020-03-03 2023-07-04 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation layers for semiconductor devices
US11233149B2 (en) 2020-03-03 2022-01-25 Taiwan Semiconductor Manufacturing Co., . Ltd. Spacer structures for semiconductor devices
US11677013B2 (en) 2020-03-30 2023-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain epitaxial layers for transistors
US12022643B2 (en) 2020-03-31 2024-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-layer high-k gate dielectric structure
DE102020126060A1 (de) 2020-03-31 2021-09-30 Taiwan Semiconductor Manufacturing Co., Ltd. Mehrschichtige high-k-gatedielektrikumstruktur
US11107736B1 (en) 2020-03-31 2021-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structures for semiconductor devices
US11189697B2 (en) 2020-04-01 2021-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. Ultra-thin fin structure and method of fabricating the same
US11257911B2 (en) 2020-04-01 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Sacrificial layer for semiconductor process
US11139432B1 (en) 2020-04-01 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming a FinFET device
US11527527B2 (en) 2020-05-21 2022-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Tap cell, integrated circuit structure and forming method thereof
US11295989B2 (en) 2020-05-26 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structures for semiconductor devices
US11444198B2 (en) 2020-05-29 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Work function control in gate structures
US11302580B2 (en) 2020-05-29 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Nanosheet thickness
US11424347B2 (en) 2020-06-11 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11417571B2 (en) 2020-06-12 2022-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Dopant profile control in gate structures for semiconductor devices
US11296095B2 (en) 2020-06-12 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and method for forming the same
US11637099B2 (en) 2020-06-15 2023-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Forming ESD devices using multi-gate compatible processes
US11264513B2 (en) 2020-06-30 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structures for transistors
US11315924B2 (en) 2020-06-30 2022-04-26 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structure for preventing unintentional merging of epitaxially grown source/drain
US11848238B2 (en) 2020-06-30 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for manufacturing semiconductor devices with tunable low-k inner air spacers
US11437371B2 (en) 2020-07-10 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Field effect transistors with negative capacitance layers
US12125891B2 (en) 2020-07-22 2024-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having gate spacers extending below a fin top surface
US11296082B2 (en) 2020-07-30 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
US11791401B2 (en) 2020-07-30 2023-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
US11532718B2 (en) 2020-07-30 2022-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins
US11245023B1 (en) 2020-07-31 2022-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11348921B2 (en) 2020-07-31 2022-05-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of manufacturing the same
US11489057B2 (en) 2020-08-07 2022-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structures in semiconductor devices
US12046479B2 (en) 2020-08-13 2024-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-containing STI liner for SiGe channel
US11610979B2 (en) 2020-08-13 2023-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Profile control in forming epitaxy regions for transistors
US11335606B2 (en) 2020-08-19 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Power rails for stacked semiconductor device
US11569234B2 (en) 2020-09-21 2023-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and methods of forming the same
US11349002B2 (en) 2020-09-25 2022-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure for for isolating epitaxially grown source/drain regions and method of fabrication thereof
US11721593B2 (en) 2020-09-30 2023-08-08 Tiawan Semiconductor Manufacturing Co., Ltd. Source/drain epitaxial structures for semiconductor devices
US11450743B2 (en) 2020-10-21 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a semiconductor device with implantation of impurities at high temperature
US11495463B2 (en) 2020-10-27 2022-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11276604B1 (en) 2020-10-27 2022-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Radical-activated etching of metal oxides
US11521971B2 (en) 2020-11-13 2022-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Gate dielectric having a non-uniform thickness profile
US11854831B2 (en) 2020-11-24 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Cleaning process for source/drain epitaxial structures
US11777014B2 (en) 2021-01-04 2023-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Controlled doping in a gate dielectric layer
US11784218B2 (en) 2021-01-08 2023-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Gate air spacer protection during source/drain via hole etching
US11948939B2 (en) 2021-01-13 2024-04-02 Taiwan Semiconductor Manufacturing Company, Ltd Profile control of gate structures in semiconductor devices
US11996317B2 (en) 2021-01-15 2024-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for forming isolation regions by depositing and oxidizing a silicon liner
US11600703B2 (en) 2021-01-29 2023-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Germanium tin gate-all-around device
US20220271162A1 (en) * 2021-02-19 2022-08-25 Qualcomm Incorporated P-type field effect transistor (pfet) on a silicon germanium (ge) buffer layer to increase ge in the pfet source and drain to increase compression of the pfet channel and method of fabrication
US11626495B2 (en) 2021-02-26 2023-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Protective liner for source/drain contact to prevent electrical bridging while minimizing resistance
US11848209B2 (en) 2021-02-26 2023-12-19 Taiwan Semiconductor Manufacturing Co., Ltd. Patterning semiconductor devices and structures resulting therefrom
US12040383B2 (en) 2021-03-05 2024-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and related methods
US11387109B1 (en) 2021-03-05 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. CMP process and methods thereof
US11942358B2 (en) 2021-03-12 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Low thermal budget dielectric for semiconductor devices
US11575026B2 (en) 2021-03-19 2023-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain structure for semiconductor device
US12062658B2 (en) 2021-03-31 2024-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming an integrated circuit having transistor gates over an interconnection structure
US11961884B2 (en) 2021-03-31 2024-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fill structures with air gaps
US11996468B2 (en) 2021-04-16 2024-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device fabrication and structures thereof
US12087845B2 (en) 2021-04-21 2024-09-10 Taiwan Semiconductor Manufacturing Co., Ltd. System and methods of manufacturing semiconductor devices
US11929287B2 (en) 2021-04-23 2024-03-12 Taiwan Semiconductor Manufacturing Co., Ltd. Dielectric liner for field effect transistors
US11869892B2 (en) 2021-04-29 2024-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and methods of forming the same
US11476342B1 (en) 2021-05-05 2022-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with improved source and drain contact area and methods of fabrication thereof
US11575047B2 (en) 2021-05-12 2023-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device active region profile and method of forming the same
US12027583B2 (en) 2021-05-13 2024-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structures for semiconductor devices
US11901415B2 (en) 2021-05-28 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor isolation structures
US11869954B2 (en) 2021-05-28 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Nanostructured channel regions for semiconductor devices
US12009208B2 (en) 2021-06-07 2024-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Deposition equipment with adjustable temperature source
US11916151B2 (en) 2021-06-25 2024-02-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having fin with all around gate
US12057506B2 (en) 2021-07-08 2024-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US12021125B2 (en) 2021-07-16 2024-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. High selectivity etching with germanium-containing gases
US12062576B2 (en) 2021-07-16 2024-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with a rare earth metal oxide layer
US11670590B2 (en) 2021-08-12 2023-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Chip structure with etch stop layer and method for forming the same
US11908921B2 (en) 2021-08-26 2024-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor isolation structures
US12002867B2 (en) 2021-08-27 2024-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structure for semiconductor device
US11990511B2 (en) 2021-08-27 2024-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain device and method of forming thereof
US12040384B2 (en) 2021-08-27 2024-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain structure for semiconductor device
US11920254B2 (en) 2021-08-30 2024-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. Detection of contact formation between a substrate and contact pins in an electroplating system
US11901412B2 (en) 2021-08-30 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Facet-free epitaxial structures for semiconductor devices
US11688625B2 (en) 2021-08-30 2023-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing semiconductor device
US11894276B2 (en) 2021-08-30 2024-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same
US12002863B2 (en) 2021-08-31 2024-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with air-gap spacers
US11942533B2 (en) 2021-08-31 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Channel structures for semiconductor devices
US11948840B2 (en) 2021-08-31 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Protective layer over FinFET and method of forming same
US11749570B2 (en) 2021-08-31 2023-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Etch monitoring and performing
CN115411091B (zh) * 2022-08-25 2024-06-28 长鑫存储技术有限公司 半导体结构及其制作方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060208320A1 (en) * 2005-03-15 2006-09-21 Kabushiki Kaisha Toshiba MIS-type semiconductor device
US20070026591A1 (en) * 2002-08-12 2007-02-01 Grupp Daniel E Insulated gate field effect transistor having passivated schottky barriers to the channel
TW200746428A (en) * 2006-04-04 2007-12-16 Micron Technology Inc Tunneling transistor with sublithographic channel
US20100006983A1 (en) * 2005-02-24 2010-01-14 Infineon Technologies Ag Process for producing sublithographic structures
TW201021209A (en) * 2008-08-28 2010-06-01 Memc Electronic Materials Bulk silicon wafer product useful in the manufacture of three dimensional multigate MOSFETs
US20100252862A1 (en) * 2009-04-01 2010-10-07 Chih-Hsin Ko Source/Drain Engineering of Devices with High-Mobility Channels
US20110248348A1 (en) * 2010-04-08 2011-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Gate Process For Fabricating Finfet Device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
JP4847152B2 (ja) * 2006-02-22 2011-12-28 富士通セミコンダクター株式会社 半導体装置とその製造方法
US7678631B2 (en) * 2006-06-06 2010-03-16 Intel Corporation Formation of strain-inducing films
US7674669B2 (en) * 2007-09-07 2010-03-09 Micron Technology, Inc. FIN field effect transistor
US7964910B2 (en) * 2007-10-17 2011-06-21 International Business Machines Corporation Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure
US8299453B2 (en) * 2009-03-03 2012-10-30 International Business Machines Corporation CMOS transistors with silicon germanium channel and dual embedded stressors
US8264021B2 (en) * 2009-10-01 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods for forming the same
US9245805B2 (en) * 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
DE102010029531B4 (de) * 2010-05-31 2017-09-07 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Verringerung der Defektraten in PFET-Transistoren mit einem Si/Ge-Halbleitermaterial, das durch epitaktisches Wachsen hergestellt ist
US8659054B2 (en) * 2010-10-15 2014-02-25 International Business Machines Corporation Method and structure for pFET junction profile with SiGe channel

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070026591A1 (en) * 2002-08-12 2007-02-01 Grupp Daniel E Insulated gate field effect transistor having passivated schottky barriers to the channel
US20100006983A1 (en) * 2005-02-24 2010-01-14 Infineon Technologies Ag Process for producing sublithographic structures
US20060208320A1 (en) * 2005-03-15 2006-09-21 Kabushiki Kaisha Toshiba MIS-type semiconductor device
TW200746428A (en) * 2006-04-04 2007-12-16 Micron Technology Inc Tunneling transistor with sublithographic channel
TW201021209A (en) * 2008-08-28 2010-06-01 Memc Electronic Materials Bulk silicon wafer product useful in the manufacture of three dimensional multigate MOSFETs
US20100252862A1 (en) * 2009-04-01 2010-10-07 Chih-Hsin Ko Source/Drain Engineering of Devices with High-Mobility Channels
US20110248348A1 (en) * 2010-04-08 2011-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid Gate Process For Fabricating Finfet Device

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