CN106133892B - 使用罩盖装配电构件的方法和适合在该方法中使用的罩盖 - Google Patents
使用罩盖装配电构件的方法和适合在该方法中使用的罩盖 Download PDFInfo
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- CN106133892B CN106133892B CN201580018036.5A CN201580018036A CN106133892B CN 106133892 B CN106133892 B CN 106133892B CN 201580018036 A CN201580018036 A CN 201580018036A CN 106133892 B CN106133892 B CN 106133892B
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 238000005304 joining Methods 0.000 claims abstract description 83
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000009792 diffusion process Methods 0.000 claims abstract description 16
- 238000003466 welding Methods 0.000 claims abstract 2
- 229910000679 solder Inorganic materials 0.000 claims description 36
- 238000005245 sintering Methods 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910010293 ceramic material Inorganic materials 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 21
- 239000000945 filler Substances 0.000 description 11
- 238000005219 brazing Methods 0.000 description 10
- 238000002844 melting Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 238000001816 cooling Methods 0.000 description 5
- 230000008018 melting Effects 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 229910008433 SnCU Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910017770 Cu—Ag Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910020888 Sn-Cu Inorganic materials 0.000 description 1
- 229910020882 Sn-Cu-Ni Inorganic materials 0.000 description 1
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 229910006414 SnNi Inorganic materials 0.000 description 1
- 229910019204 Sn—Cu Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- XEOCKQIQXJNTER-UHFFFAOYSA-N gold palladium platinum Chemical compound [Pd].[Pd].[Pd].[Pd].[Pd].[Pt].[Pt].[Pt].[Pt].[Pt].[Pt].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au].[Au] XEOCKQIQXJNTER-UHFFFAOYSA-N 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 210000002966 serum Anatomy 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4875—Connection or disconnection of other leads to or from bases or plates
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- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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Abstract
本发明涉及一种用于将电构件(12)装配在基底(13)上的方法。根据本发明,接合通过罩盖(11)得以简化,其中,在该罩盖中设有触点接通结构(16)并且该触点接通结构当罩盖(11)安放在各接合水平面(28、29)上时用焊接填充料(35)接合。另外,通过该罩盖可构建所需的接合压力,正如例如在电触点的扩散连接或烧结连接中需要接合压力那样。另外,本发明涉及一种适合在该方法中使用的罩盖。
Description
本发明涉及一种用于在基底上装配电构件的方法,其中该构件具有朝向基底的下侧和与下侧对置的上侧。在该方法中,该构件的下侧与通过基底提供的组件机械连接。该构件上侧则与触点接通结构机械连接。在此,在接合时形成的接合连接部处于至少两个不同的接合水平面。
本发明还涉及一种用于电组件的罩盖,其中,该组件具有基底和至少一个装配在基底上的构件。罩盖具有支承面,罩盖可以支承面安放在基底上。罩盖另外具有空腔,在该空腔中可容纳构件。构件不仅在其上侧而且在其下侧(构件以其下侧装配在基底上)具有触点。这些触点因此处于不同的接合水平面。
所述接合水平面这样限定,即,电子构件的触点当装配在基底上时和当触点接通时处于不同的平面,其中,用词“平面”在这里是指技术意义而非数学意义。平面或相关的接合水平面限定了待触点接通的构件的特定的接合连接部所处于的区域。
通过叠置构件,接合水平面优选地同样叠置,尤其沿彼此平行的取向叠置。
用于将电子构件装配到基底上的方法是已知的。这些装配方法也得以应用于功率电子应用的电子组件的装配。例如,在DE100 62 108 A1中描述了可构建功率模块,其中电子的功率构件可以通过烧结层与基底连接。基底可以是通常应用于功率电子中的DCB-陶瓷基底(DCB表示覆铜陶瓷(Direct Copper Bond))。功率构件的上侧可以用烧结层例如连接在提供冷却体的附加热容上。基底可完全一样地用其下侧经由烧结层与另外的冷却体连接。
根据DE 10 2007 047 698 A1已知,电子组件的烧结连接可借助特殊工具制造。这些工具具有与要烧结的构件接触的压力面,从而在烧结处理期间可施加压力于所述压力面上。通过工具中的公差补偿可以确保,当待烧结的组件具有取决于公差的制造误差时,所施加的压力也可以是均匀的。在烧结处理时,除了形成压力以外,在限定的时间间隔内达到特定的烧结温度也是必要的。还可以设置钎焊连接替代烧结连接。
根据US 2013/0201631 A1要注意的是,这样选择对于烧结过程所需的温度,使得该组件中已经装配的接合连接部不会由于刚刚发生的热处理而再次熔融。这如下实现:在相关的连接工艺之前已经实现的构件连接具有这样的连接材料,这些连接材料的工艺温度(软化温度、烧结温度、熔融温度)以足够的安全距离处于刚刚发生的连接工艺的相关工艺温度之上。以该方式,已经形成的接合连接部关于它们的完整性不会因刚刚进行的连接过程而受损。
在完成这些构件在基底上的装配之后通常还必须进行通过适合的触点接通结构使这些构件与基底的触点接通。在此,处于构件上侧的触点与在基底上的相应触点相连接。为此除了根据US 2012/0106109 A1通常已知的焊线以外还可应用金属导电结构,这些金属导电结构例如可为引线框架的一部分。以适合方式弯曲的导电结构优选地借助烧结或钎焊与相关的接触面连接。另一可能性在于,这些触点接通结构通过柔性膜(Flexfolien)提供,在所述柔性膜上印制例如导电结构。根据DE 10 2009 016 112 A1,这些柔性膜也可借助烧结连接在构件上侧和基底装配侧的相关接触面处连接。
通过在形成功率电子时经转换的电功率,功率电子组件以热和电的方式被强烈负载,因此这些电连接部和其它接合连接部必须具有高的可靠性。恰好的烧结连接特别地适合于该目的,因为其热稳定性以及接合连接部的无缺陷形成能够得以确保。然而,相较于例如钎焊而言,通过烧结连接来装配功率电子组件目前意味着在制造中一定的额外耗费。
发明内容
本发明要解决的技术问题在于,提供一种用于将电构件装配在基底上的方法,其中该方法被简化并且还允许功率电子构件的装配。另外,技术问题在于提供前述类型的罩盖,该罩盖可在该改善的方法中使用。
根据本发明,该技术问题是用前述方法通过将触点接通结构以导电路径(Leitpfaden)的形式设计在罩盖内侧上解决的。在装配时,将罩盖安放在基底的装配侧上,其中在由基底的装配侧提供的第一接合水平面内形成了触点接通结构与基底的电接触。罩盖跨越构件,并且在罩盖内侧上,在构件上侧的高度上的第二接合水平面内形成触点接通结构与构件的电接触。这意味着,触点接通结构的接触面分别设置在基底装配侧的高度上的第一接合水平面上和在构件上侧的高度上的第二接合水平面上。由此,触点接通结构桥接了两个不同的接合水平面,这两个接合水平面有利地在没有例如焊线或自支撑式引线框架的辅助措施的前提下可以在装配步骤中通过装上罩盖来可靠地接合。在此,在接触面于不同的接合水平面中触点接通的情况下,制造公差也可以减少,因为在需要相对简单且准确地制造的构件、即罩盖中,所述不同的接合水平面能够在其制造时就已经被集成。于是,单独支承的触点接通结构的后续装配不是必需的。触点接通结构的定位有利地与罩盖在基底上的定位一起进行。
根据本发明的设计方式规定,首先将基底、构件和具有触点接通结构的罩盖在要形成的构造中彼此放置在一起。在此之后才应当在同一工序中通过升高温度或升高温度和压力来完成在至少两个接合水平面内在构件处接合连接部、尤其是电连接部。换言之,根据本发明规定,用于将电子组件装配在基底上的方法应以两个限定的工艺段进行。在第一工艺段中,由基底提供的组件的所有待装配构件彼此放置在一起。在此,这也导致接合连接的形成,然而这些接合连接仍未完成。在第二制造阶段中,完成这些接合连接。为此,需要使用适合的接合方法,其中,根据待形成的机械连接的类型,需要升高温度(例如在钎焊时)或升高温度和压力(例如在扩散钎焊或在烧结时)。有利地设成,这些接合连接可在一个工序中形成。为此需要针对在该单个工序中使用的工艺参数来设计所有待形成的接合连接。由此达到特定的温度水平。另外,至少可以额外地施加压力于这些连接部的一部分上。分别选择的连接类型以及可能必要的焊接填充料不一定需要在所有接合连接部中均完全相同。关键的仅仅是,工艺参数对于所有的连接类型和材料都彼此匹配并且以该方式能够在一个工序中同时形成所有的接合连接。
通过同时形成所有的接合连接,有利地尤其也可以装配这样的触点接通结构,它们的特别是电连接部处于不同的接合水平面上。在此可将这些接合水平面桥接,而无需额外的用于形成接合连接部的工序。有利地是如下实现:构件下侧位于由基底装配侧提供的第一接合水平面内,并且,构件上侧位于第二接合水平面内。第一接合水平面由常规地通过基底提供的平面限定。接合连接部的组合位于该平面上(该平面对于不平的基底如壳体而言无须强制性地在数学意义上是平的),电构件的下侧分别以这些接合连接部在基底上触点接通。只要构件具有电接触面,构件上侧就限定出第二接合水平面,第二接合水平面通过这些电构件的空间高度伸展与第一接合水平面隔开。由于这些电构件的高度不同,可能的是,第二接合水平面不处于一个平面上,其中,所有接触面的总和均在这些构件的各个上侧上限定出该接合水平面。
如果多个电构件彼此堆叠,则相应地在堆叠体的每个“楼层”中均形成进一步的接合水平面,这些接合水平面对于电连接而言可能必须通过相应的触点结构进行桥接。这些电构件以这样的布置、即它们的触点可分别对应于不同的接合水平面这样的布置,有利地简化了电组件的装配,在该电组件中这些构件和这些触点结构可以一层一层地预先装配(即,可以彼此放置在一起),以便随后在一个工序中在所有接合水平面中均形成优选的电连接部。
根据本发明的另一设计方式规定,基底以其背离装配侧的背侧提供接触面,以所述接触面可获得第三接合水平面。在该接合水平面内放置构件。随后以根据本发明的方式在这样的工序中通过升高温度或升高温度和压力来完成该构件与基底之间的连接,恰恰在该工序中还完成了在第一接合水平面和第二接合水平面(以及可能的其它接合水平面)中在电构件上的接合连接。由此有利地实现了对装配工艺的进一步简化。在完成这些连接时在一个工序中考虑到越多不同的接合水平面,装配工艺的简化程度就越大,这最终也对其经济性有好处。
装配在基底背侧上的构件也可以例如为冷却体或散热器,该冷却体在功率电子组件中用于排出热损失。该冷却体也可设计成基体,其中,该冷却体可用于多个电子组件的共同装配。另一可能性在于,基底在两侧上配备有电构件。在此情况下例如可通过基底上的冷却通道进行冷却。
根据本发明的一个特别设计方式规定,所有接合连接均在同一接合工艺中完成。如已所述,同样可能的是,针对各个接合连接选择不同的接合工艺。然而必须满足以下条件:所选的各个接合工艺能够在预设的工艺条件(温度、压力)下实现。尤其地,在整个待装配的电组件上温度必须相同。压力可以变化,方式是例如使用多个接合工具或设置这样的一个接合工具,其中例如通过具有不同的弹簧刚度的弹簧机构将不同的制造压力施加在待接合的结构的不同部件上。即使对于以同一接合工艺完成所有电连接的这种情形,这些条件也适用。特别优选地,对于所选的接合工艺(尤其是扩散钎焊或烧结)也可选择同样的焊接填充料,以使针对整个组件的接合工艺而言的制造条件一致。然而也可选择不同的焊接填充料,只要这些焊接填充料能够以上述方式在预设的接合条件下完成就可。
根据本发明的另一设计方式规定,除了接合连接外,用所选的接合工艺还完成了在构件(例如冷却体)与基底(在背侧上)之间的连接。由此,所阐述的优点也能够扩展到构件与基底之间的连接部的接合上,这些连接部能够在一个工序中与基底装配侧上的接合连接部一起完成。当然,当装配在那里的构件是电构件时,基底背侧上的连接部也可以是电连接部。
本发明的另一设计方式规定,使用扩散钎焊或烧结作为接合工艺。这些工艺当需要装配功率电子元器件时是特别适合的,因为所形成的连接部具有低的缺陷密度且拥有高的热稳定性。扩散钎焊具有一个与烧结关联的工艺流程。向待接合的构件之间的区域中引入焊接填充料,其中,该焊接填充料在温度和必要时升高的压力的作用下有助于低熔点和高熔点的合金组分的扩散。通过该局部的浓度变化,在接合区中和在接合区与相邻构件的交界面上导致高熔点的金属间相的生成,这些金属间相具有高的温度稳定性。所形成的连接具有很高的导电性和导热性以及高的机械强度。
另外可有利地规定,在放置于待形成的构造中之前,将焊接填充料引入到基底和/或构件和/或在罩盖中的触点接通结构和/或构件上。如前所述,这些焊接填充料可有利于接合,例如烧结或扩散钎焊。然而,对烧结过程或扩散过程负责的连接组成部分也可以包含在用于待形成的连接的接触面中。对于典型的钎焊,始终需要焊料作为焊接填充料。
本发明的另一设计方式规定,罩盖在外部具有平行于基底延伸的平面。这大大有利于装配工艺的进程,该进程由此被简化。平面能够实现接合工具的简单安放,使用该接合工具可向待装配的组件上施加压力。另外,当加热该工具时,经由该工具还能够引入所需的工艺热。当提供的是尤其在罩盖的整个表面尺寸上延伸的平面时,工艺热在待接合的构件、特别是罩盖上的传递同样得以改善。另一优点在于,接合工具无需在几何结构上与罩盖匹配。接合工具在标准情况下配置有用于施加压力的平面,其中,原则上能够以同一接合工具装配不同应用情形的罩盖,确切地说具有不同尺寸或具有不同的内侧结构的罩盖。
本发明的另一设计方式在如下情况下获得,即,在内侧上设置至少一个接合面,该接合面在装配时在基底上与构件形成接合。由此能够有利地实现,通过安放罩盖也将构件至少沿空间方向明确地在基底对面取向且固定。例如,接合面可作为水平面设置在罩盖内侧上。这样的接合面能够实现沿垂直于基底表面的方向定位构件。通过接合面特别是也可构建必需的压力,该压力是例如借助烧结处理或形成扩散钎焊连接来接合电触点所必需的。接合压力的形成在此通过接合面相对于罩盖在基底上的安放高度的过盈来实现,这导致罩盖的变形。换言之,在构件下方的由罩盖在基底上形成的空腔中的净高度小于构件在装配好的状态下在基底上的结构高度。由此形成了接合力P,该接合力P例如经由接合工具传递。
本发明的另一设计方式规定,在将罩盖安放在基底上之前,触点接通结构在接触面上设有焊接填充料。焊接填充料应当确保接合连接的可靠形成。当要实现的是扩散钎焊时,该接合连接例如可由扩散钎焊构成。当要制备的烧结连接时,还可以使用烧结材料。其它可能性在于使用钎焊材料、尤其是高温钎焊材料。当该组件应配备有功率电子构件时,使用烧结材料、扩散钎焊材料或高温钎焊材料则是特别有利的。它们在运行期间相对较强地升温,因此所形成的电触点还必须承受热负荷。触点接通结构可设有焊接填充料,这还具有的优点是,构件本身无需设有焊接填充料。所需的焊接填充料可施加在基底和触点接通结构上。有利地,在此仅两个构件设有焊接填充料就已足够,即基底和罩盖。这在操作中比反而多个构件必须设有焊接填充料时更简单。
该技术问题另外通过前述罩盖解决,其中,在罩盖内侧上设置从支承面通向空腔中的触点接通结构。如前文已经详细阐述地,这样的罩盖适合于根据所介绍的方法来装配在基底上。根据本发明,在此规定,组件的接触面在不同的接合水平面上的桥接能够实现,方法是:使集成到罩盖内侧中的触点接通结构从处于基底高度(第一接合水平面)上的支承面向其接触面所处位置较高(第二接合水平面)的那些构件的上侧延伸。由此,根据本发明的罩盖的使用有利地简化了电构件在基底上的装配工艺。
有利地,罩盖可设为LTCC构件或设为MID构件。LTCC构件是在所谓的LTCC技术中制备的那些构件。该缩写表示“低温共烧陶瓷(Low Temperature Co-Fired Ceramics)”,即,在低温下制备的且在其中烧制上能够形成触点结构的电路亦或导电路径的陶瓷。这些构件的制备本身是已知的,例如通过Boleslav Psota等人,,,Usage of LTCC Technology inElectronic Packaging"36th Int.Spring Seminar on Electronics Technology,IEEE2013,自第206页起。
如果罩盖被表示为MID-构件,则这意味着使用的是所谓的MID-技术。该缩写表示其中制备所谓的“模塑互连器件(Molded Interconnect Devices)”的工艺。在此,触点接通结构例如浇铸在一个构件中。该技术同样是普遍已知的,例如从N.Bachnak,,,3D-MIDTechnology MEMS Connectivity at System Level"IEEE 2012,自第572页起。
特别优选的情形是,在罩盖中将焊接填充料施加在触点接通结构的接触面上。在此,如前所述地可涉及高温钎焊材料、扩散钎焊材料或烧结材料。在罩盖装配在组件上后,这些焊接填充料则可用于形成接合连接。接合可以上文已述的方式实现。
有利的情形还有,通过罩盖边缘形成支承面。随后将罩盖以其边缘安放在基底上。只要边缘是环绕的,在将罩盖安放在基底上时就会出现封闭的空腔,该空腔有利地确保了防止组件免受污染和其它环境影响。在罩盖边缘上也可另外规定接触面或备有焊接填充料的接触面,因为由此可实现触点接通结构与基底的触点接通。
另外特别优选的情形是,罩盖外侧是平的。这带来了经简化的装配的已述优点,因为接合工具可具有平的和进而简单的几何结构并且还可得以应用于不同的罩盖几何结构(具有平的外侧)。不言而喻地,当罩盖外侧平行于支承面地设计时是有利的,因为基底(如果基底以水平定位来装配)也可通过水平施加接合工具来装配。
作为用于电构件的材料可考虑硅、碳化硅、砷化镓或氮化镓。这些材料优选地用于功率电子构件。基底可例如由陶瓷制成。所述陶瓷可涂覆有铜、银或金,其中,用于形成电接触面和导电路径的涂层可被结构化。作为焊接填充料,可根据接合工艺使用高温焊料如含锑的合金,或常规的含铅量高的焊料,材料体系Sn-Cu、Sn-Cu-Ni、Sn-Cu-Ag的扩散焊料,和优选地含银的银膏或烧结膜。接下来示例性地描述用于焊接填充料的以下实例。
烧结连接部:
银-烧结膏(例如Heraeus mAgic Paste,Microbond ASP Serie),温度范围200-280℃
扩散焊料连接部:
材料体系SnCu、SnAg、SnNi和能够形成高熔点的金属间相的其它材料体系。在此可使用不同的配制物,例如,
-单膏体系,其具有分散在由低熔点合金(如SnCu)制成的基体中的高熔点颗粒(如Cu),
-使用依次施涂方法的双膏体系(高熔点Cu,随后是SnCu-合金),或
-将低熔点的焊接填充料(例如SnCu-合金)施涂在高熔点界面(例如Cu)之间的方法,其中,在工艺条件下通过扩散性浓度变化产生高熔点接合区。
附图说明
接下来借助附图来说明本发明的其它细节。相同或相对应的标记元素分别设有相同的附图标记并且在各图之间存在差异时才多次阐述。其中:
图1示出根据本发明的罩盖的实施例的横截面示意图,其中,在此也涉及根据本发明的方法的实施例的第一步骤,和
图2和3示出了根据本发明的方法的该实施例的其它工艺步骤,作为侧视图,局部剖视图。
具体实施方式
图1中示出了罩盖11,其根据图3可安放在配有电构件12的基底13上。罩盖11由塑料材料构成,用该塑料材料制造MID构件。在罩盖中设有内侧18,在内侧18中借助MID技术浇铸或以其它方式形成触点接通结构16。触点接通结构16因此与罩盖的材料整合为一体,其中,触点接通结构16的整个上侧独立地处于罩盖11的内侧18处。在提供用于触点接通的接触面的触点接通结构的端部处,设有以扩散焊料形式的焊接填充料17。罩盖除内侧18外还具有外侧19,其中外侧19设成平的,从而能够将带有平的压力面的接合工具20a安放在罩盖的外侧19上(比对图3)。在此使用接合面15,该接合面15如图3所示的那样安放在待装配的构件12的上侧27上。
另外,在罩盖的内侧18上形成支承面21,支承面21在图1所示的剖面图中由焊接填充料17在罩盖的外边缘处提供。在未设有焊接填充料之处,该支承面21还可通过罩盖11的材料形成(未示出)。支承面的作用是,使得能够在另一工艺步骤中直接被安放在基底上。由此,罩盖的内部可以对周围密封,以便在罩盖的内部形成空腔22(比对图3)。
图2中可见基底13,其具有装配侧23和背侧24。在此涉及未详细示出的DCB-陶瓷基底,其中,铜层未详细示出。在装配侧23上且在背侧24上设置另外的具有焊接填充料17的区域,不同的接合配对件应当在随后被装配在这些区域中(比对图3)。装配侧23上未示出的铜层以适合方式结构化,由此可使待装配的构件12以适合方式触点接通。
图3中示出了如何形成待装配的电组件的方式。由此可见,在基底13的装配侧23上在焊接填充料的区域中(比对图2),构件12以其下侧26被安放在基底13的装配侧23上。该构件12具有在其上侧27上未详细示出的电触点。将罩盖11根据图1安放在这样形成的由基底13和构件12构成的组件上,其中,触点接通结构16以它们的端部和焊接填充料(比对图1)实现了平放在构件12的上侧27和基底13的装配侧23上。在此要考虑到,触点接通结构16的端部分别处于不同的高度或水平上,所述不同的高度在图3中标出作为通过基底13的装配侧23而设的第一接合水平面28和作为通过构件12的上侧27而设的第二接合水平面29。第三接合水平面30通过基底13的下侧24提供。这用于固定基板31,基板31设计为冷却体或散热器,并作为构件经由所述焊接填充料(比对图2)与基底13的下侧24热传导地连接。出于冷却的目的,在基板23中例如可设有冷却通道32。这时,根据图3的组件是预装配的。也就是说,各个构件部件(基板31、基底13、构件12、触点接通结构16)在待形成的构造中彼此放置在一起。焊接填充料17的作用在于,使得该构造为了有利于在其它制造工艺中的操作已然具有足够的稳定性。出于该目的,还可以具有未详细示出的接合辅助件。这些接合辅助件例如可以由外部工具如夹子组成。还可将接合辅助件如卡夹连接集成到各个构件中(未示出)。借助这些接合辅助件对该组件的单个构件的固定仅仅是暂时的,直到该组件的最终装配。
最终装配同样在图3中表示。该组件被插入到适合的工具中。该工具由从下方且从上方引到完成的组件25上的接合工具20a、20b组成。这些接合工具拥有支承面34,以这些支承面34能够将按压力P施加在待接合的构件上。这些支承面34有利地设计为平的,这是通过基板31和罩盖11均以适合方式提供用于接合工具20a、20b的平的支承面实现的。因此,未详细示出的用于使接合工具处于温度T的加热器可以将热量在整个支承面34上传递到组件25上。接合工具中的热量例如可以通过未示出的电阻式加热器实现。与必要的按压力P一起,将焊接填充料(比对图1)转换成根据图3的接合连接部35,从而以该方式永久性地装配该组件。
Claims (4)
1.一种用于将电构件(12)装配在基底(13)上的方法,其中,在所述方法期间,
·所述电构件具有朝向基底的下侧和与下侧对置的上侧(27),
·电构件(12)的下侧与通过基底(13)提供的组件通过形成接合连接部(35)机械连接,
·电构件(12)的上侧(27)和基底(13)的装配侧(23)经由触点接通结构(16)通过形成接合连接部(35)机械连接,
其中,在接合时形成的接合连接部位于至少两个不同的接合水平面,
并且其中在所述方法期间触点接通结构(16)以在罩盖(11)内侧上延伸的导电路径的形式设计,其中,
·在装配时罩盖(11)跨越电构件(12),
·在装配时罩盖(11)被安放在基底(13)的装配侧(23)上,其中,在由基底(13)的装配侧(23)提供的第一接合水平面(28)内形成触点接通结构(16)与基底(13)的机械接触,
·在装配时在罩盖(11)内侧上,在电构件的上侧(27)的高度上的第二接合水平面(29)内形成触点接通结构(16)与电构件(12)的电接触,
其中,罩盖(11)在外部具有平行于基底延伸的平面,其中,在罩盖(11)的内侧上设置至少一个接合面(15),所述接合面在装配在基底(13)上时与电构件(12)形成接合,其中,接合面(15)与电构件(12)的上侧(27)处于接合状态,其中,这样形成的接触面位于所述电接触之外,
·基底(13)由陶瓷材料制成,所述陶瓷材料覆有铜、银或金,
其中,
·先将基底(13)、电构件(12)和罩盖(11)组装在一起,
·随后在同一工序中通过升高温度或升高温度和压力来完成在第一接合水平面(28)和第二接合水平面(29)中在电构件(12)处的接合连接部(35)。
2.根据权利要求1所述的方法,其特征在于,
·基底(13)以其背离装配侧(23)的、提供第三接合水平面(30)的背侧(24)与构件(31)组装在一起,
·随后,在完成在第一接合水平面(28)和第二接合水平面(29)中在电构件(12)处的接合连接部(35)的工序中,还完成构件(31)与基底(13)之间的连接。
3.根据权利要求1所述的方法,其特征在于,接合连接部的完成通过扩散焊接或烧结实现。
4.根据前述权利要求之一所述的方法,其特征在于,触点接通结构(16)在接触面上设有焊接填充料(17),然后将罩盖(11)安放在基底(13)上。
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CN201580018036.5A Active CN106133892B (zh) | 2014-04-04 | 2015-03-30 | 使用罩盖装配电构件的方法和适合在该方法中使用的罩盖 |
Country Status (6)
Country | Link |
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US (1) | US11424170B2 (zh) |
EP (1) | EP3103138B1 (zh) |
JP (1) | JP6629290B2 (zh) |
CN (1) | CN106133892B (zh) |
DE (1) | DE102014206601A1 (zh) |
WO (1) | WO2015150335A1 (zh) |
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-
2014
- 2014-04-04 DE DE102014206601.8A patent/DE102014206601A1/de not_active Withdrawn
-
2015
- 2015-03-30 CN CN201580018036.5A patent/CN106133892B/zh active Active
- 2015-03-30 JP JP2017503064A patent/JP6629290B2/ja active Active
- 2015-03-30 WO PCT/EP2015/056912 patent/WO2015150335A1/de active Application Filing
- 2015-03-30 US US15/301,772 patent/US11424170B2/en active Active
- 2015-03-30 EP EP15714453.6A patent/EP3103138B1/de active Active
Also Published As
Publication number | Publication date |
---|---|
US11424170B2 (en) | 2022-08-23 |
DE102014206601A1 (de) | 2015-10-08 |
JP2017515317A (ja) | 2017-06-08 |
US20170033024A1 (en) | 2017-02-02 |
EP3103138C0 (de) | 2024-07-03 |
CN106133892A (zh) | 2016-11-16 |
EP3103138A1 (de) | 2016-12-14 |
WO2015150335A1 (de) | 2015-10-08 |
EP3103138B1 (de) | 2024-07-03 |
JP6629290B2 (ja) | 2020-01-15 |
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