CN105514045A - 闪存存储器栅极结构及其制作方法 - Google Patents
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Abstract
本发明公开一种闪存存储器栅极结构及其制作方法,其制作方法包含:首先提供一基底,再依序形成一第一绝缘层、一第一导电层和一第二绝缘层覆盖基底,然后在第一导电层和第二绝缘层内形成至少一第一沟槽,之后形成一第二导电层和一掩模层覆盖第二绝缘层,其中第二导电层填满第一沟槽,接续形成多个图案化掩模层,接着于各个图案化掩模层的两侧各形成一间隙壁,最后以图案化掩模层与间隙壁为掩模蚀刻第一导电层,直至第一绝缘层曝露出来,以形成一第一栅极结构和一第二栅极结构。
Description
技术领域
本发明涉及一种闪存存储器栅极结构及其制作方法,尤其是涉及一种使得选择栅极结构与浮置栅极结构之间的间隙缩小的栅极结构及其制作方法。
背景技术
闪存存储器(flashmemory)是一种非挥发性(non-volatile)存储器,其在缺乏外部电源供应时,也能够保存存储在存储器中的信号内容。近几年来,由于闪存存储器具有可重复写入以及可被电抹除等优点,因此,已被广泛地应用在移动电话(mobilephone)、数字相机(digitalcamera)、游戏机(videoplayer)、个人数字助理(personaldigitalassistant,PDA)等电子产品或正在发展中的系统单芯片(systemonachip,SOC)中。
然而,现有的分离栅(splitgate)闪存存储器在制作过程中容易遇到选择栅极与控制栅极对准偏差(overlayshift)的问题,并且制作步骤繁复,因此需要改善。
发明内容
有鉴于此,本发明的目的在于提供一种新颖的闪存存储器栅极结构及其制作方法,以解决上述问题。
根据本发明的一优选实施例,本发明提供一种闪存存储器栅极结构的制作方法,包含:首先提供一基底,基底包含一阵列区,再依序形成一第一绝缘层、一第一导电层和一第二绝缘层,覆盖基底的阵列区,然后在第一导电层和第二绝缘层内形成至少一第一沟槽,之后形成一第二导电层和一掩模层于阵列区并且覆盖第二绝缘层,其中第二导电层填满第一沟槽,接续形成多个图案化掩模层,接着于各个图案化掩模层的两侧各形成一间隙壁,最后以图案化掩模层与间隙壁为掩模蚀刻第一导电层,直至第一绝缘层曝露出来,以形成一第一栅极结构和一第二栅极结构,其中第一栅极结构包含第一沟槽,并且该第一栅极结构与第二栅极结构之间具有一间隙。
根据本发明的另一优选实施例,一种闪存存储器结构,包含:一第一栅极结构、一第二栅极结构以及一源极与一漏极分别设置于闪存存储器结构的两侧,第一栅极结构与第二栅极结构相邻地形成于一基底上,并且两者之间具有一间隙,第一栅极结构与第二栅极结构分别包含:一第一绝缘层、一第一导电层、一第二绝缘层、一第二导电层、一掩模层、以及一间隙壁覆盖于掩模层的侧壁,其中第一栅极结构的第二绝缘层与第一导电层具有一沟槽,并且第二导电层延伸至沟槽与该第一导电层相连接;其中第一栅极结构作为一选择栅极,第二栅极结构作为一控制栅极以及一浮置栅极。
根据本发明的另一优选实施例,一种闪存存储器结构的读取方法,闪存存储器结构包含一第一栅极结构以及一第二栅极结构形成于一基底上,第一栅极结构包含一选择栅极,第二栅极结构包含一控制栅极,其中第一栅极结构与第二栅极结构之间具有一间隙,并且闪存存储器结构两侧的基底中分别有一源极以及一漏极,读取方法包含:在选择栅极施加Vcc电压,在基底施加0伏特电压,在源极施加0伏特电压,在漏极施加1伏特电压,以及于控制栅极施加Vcc电压。
根据本发明的另一优选实施例,一种闪存存储器结构的写入方法,闪存存储器结构包含一第一栅极结构以及一第二栅极结构形成于一基底上,第一栅极结构包含一选择栅极,第二栅极结构包含一控制栅极,其中第一栅极结构与第二栅极结构之间具有一间隙,并且闪存存储器结构两侧的基底中分别有一源极以及一漏极,写入方法包含:在选择栅极施加1~4伏特电压,在基底施加0伏特电压,在源极施加3~5.5伏特电压,在漏极施加0伏特电压或是1~2微安培,以及于该控制栅极施加8.5~13电压。
根据本发明的另一优选实施例,一种闪存存储器结构的抹除方法,闪存存储器结构包含一第一栅极结构以及一第二栅极结构形成于一基底上,第一栅极结构包含一选择栅极,第二栅极结构包含一控制栅极,其中第一栅极结构与第二栅极结构之间具有一间隙,并且闪存存储器结构两侧的基底中分别有一源极以及一漏极,抹除方法包含:在选择栅极施加0伏特电压,在基底施加7~11伏特电压,源极维持浮置或是0伏特,在漏极施加0伏特电压或者维持浮置,以及于控制栅极施加-7~-11伏特电压。
一种闪存存储器结构的抹除方法,闪存存储器结构包含一第一栅极结构以及一第二栅极结构形成于一基底上,第一栅极结构包含一选择栅极,第二栅极结构包含一控制栅极,其中第一栅极结构与第二栅极结构之间具有一间隙,并且闪存存储器结构两侧的基底中分别有一源极以及一漏极,抹除方法包含:在选择栅极施加0伏特电压,在基底施加0伏特电压,源极施加5~9伏特电压,在漏极施加0伏特电压或者维持浮置,以及于控制栅极施加-7~-11伏特电压。
附图说明
图1至图7为本发明的优选实施例所绘示的闪存存储器栅极的制作方法示意图;
图8A为本发明的一优选实施例所绘示的闪存存储器栅极的制作方法的变化型的示意图;
图8B为本发明的一优选实施例所绘示的闪存存储器栅极的制作方法的变化型的示意图;
图8C为本发明的一优选实施例所绘示的闪存存储器栅极的制作方法的变化型的示意图;
图9A为本发明的一优选实施例所绘示的闪存存储器栅极结构的变化型的示意图;
图9B为本发明的一优选实施例所绘示的闪存存储器栅极结构的变化型的示意图;
图9C为本发明的一优选实施例所绘示的闪存存储器栅极结构的变化型的示意图;
图10为本发明闪存存储器结构在不同模式下的操作电压的示意图。
符号说明
10基底12第一绝缘层
12’图案化第一绝缘层14第一导电层
14’图案化第一导电层16第二绝缘层
16’图案化第二绝缘层18图案化掩模层
20沟槽22第二导电层
22’图案化第二导电层24掩模层
24’图案化掩模层26图案化光致抗蚀剂层
28间隙壁材料层30间隙壁
32第一栅极结构34第二栅极结构
100闪存存储器栅极结构102源极
104漏极
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明,下文特列举本发明的优选实施例,并配合所附的附图,详细说明本发明的构成内容及所欲达成的功效。
图1至图7为根据本发明的优选实施例绘示的闪存存储器栅极的制作方法示意图。
首先提供一基底10,基底10包含一阵列区A,接着依序形成一第一绝缘层12、一第一导电层14和一第二绝缘层16。第一绝缘层12和第二绝缘层16可以各自地为单层或多层的绝缘材料所构成,包括硅氧化物、氮氧化物或高介电常数介电层。根据本发明的优选实施例,第一绝缘层12为氧化硅,第二绝缘层16为氧化硅和氮化硅所组成的多材料层,例如:氧化硅-氮化硅-氧化硅或者氧化硅-氮化硅-氧化硅-氮化硅等。第一导电层14可以为多晶硅、金属硅化物或具有特定功函数的金属材料,根据本发明的优选实施例,第一导电层14可以为多晶硅。
之后如图2所示,形成一图案化掩模层18,并且图案化掩模层18曝露部分阵列区A的第二绝缘层16,然后以图案化掩模层18为掩模,蚀刻第二绝缘层16和第一导电层14,以在第一导电层14和第二绝缘层16中形成多个沟槽20,接着移除图案化掩模层18。
如图3所示,依序形成一第二导电层22和一掩模层24覆盖阵列区A的第二绝缘层16并且第二导电层22填满在阵列区A的沟槽20。第二导电层22可以为多晶硅、金属硅化物或具有特定功函数的金属材料,掩模层24可以为氮化硅或是其它合适的材料。
如图4所示,利用光刻及显影制作工艺,形成一图案化光致抗蚀剂层26,并且曝露部分阵列区A的掩模层24,详细来说,图案化光致抗蚀剂层26定义出后续选择栅极结构、控制栅极结构和浮置栅极结构的位置。接着如图5所示,以图案化光致抗蚀剂26为掩模,蚀刻掩模层24并且以第二导电层22作为蚀刻停止层,以在阵列区A内形成多个图案化掩模层24’,接着,移除图案化光致抗蚀剂26。如图6所示,在各个图案化掩模层24’上顺应地形成一间隙壁材料层28,如图7所示,干蚀刻阵列区A的间隙壁材料层28,在各个图案化掩模层24’的两侧各形成一间隙壁30,再以间隙壁30和图案化掩模层24’为掩模以自我对准的方式,依序蚀刻第二导电层22、第二绝缘层16、第一导电层14和第一绝缘层12,直至基底10曝露出来,以形成图案化第一绝缘层12’、图案化第一导电层14’、图案化第二绝缘层16’和图案化第二导电层22’并且形成一第一栅极结构32和一第二栅极结构34,其中第一栅极结构32包含了图案化第一绝缘层12’、图案化第一导电层14’、图案化第二绝缘层16’、图案化第二导电层22’和沟槽20,此外,第一栅极结构32之后会作为一选择栅极结构,第二栅极结构34中的图案化第二导电层22’和图案化第二绝缘层16’之后会作为一控制栅极结构,而图案化第一导电层14’和第一绝缘层12’之后会作为一浮置栅极结构。至此,本发明的闪存存储器结构100业已完成,之后并于闪存栅极结构100左右两侧的基底中形成一源极102以及一漏极104。
请继续参阅图7,第一栅极结构32以及第二栅极结构34之间具有一微小间隙D,根据本发明的优选实施例,间隙D介于50埃至400埃之间。此外,根据本发明的另一实施例,第一栅极结构32与第二栅极结构34顶面的图案化掩模层24’以及间隙壁30可以被移除。
在前述图4,以图案化光致抗蚀剂26为掩模,蚀刻掩模层24时,以第二导电层22作为蚀刻停止层,根据本发明的其它优选实施例,蚀刻掩模层24时,也可以分别以第二绝缘层16、第一导电层14作为蚀刻停止层,请同时参阅图5至图7以及图8A、图8B和图8C,如图8A所示,在蚀刻掩模层24之后,以图案化光致抗蚀剂26为掩模继续蚀刻第二导电层22,以第二绝缘层16作为蚀刻停止层,然后形成多个图案化第二导电层22’,并且图7中所形成的间隙壁30就会由各个图案化掩模层24’向下延伸至并覆盖各个图案化第二导电层22’的侧壁;如图8B所示,在蚀刻该掩模层24之后,以图案化光致抗蚀剂26为掩模继续蚀刻第二导电层22和第二绝缘层16,以第一导电层14作为蚀刻停止层,然后形成多个图案化第二导电层22’和多个图案化第二绝缘层16’,并且图7中所形成的间隙壁30会由各个图案化掩模层24’向下延伸至并覆盖各个图案化第二导电层22’的侧壁以及图案化第二绝缘层16’的侧壁;如图8C所示,在蚀刻掩模层24之后,以图案化光致抗蚀剂26为掩模继续蚀刻第二导电层22、第二绝缘层16和第一导电层14,直到在第一导电层14内形成多个沟槽42,并且可以选择性地曝露出第一绝缘层12。因此形成图案化第二导电层22’、图案化第二绝缘层16’、图案化的第一导电层14’和多个沟槽42,并且图7中所形成的间隙壁30会由各个图案化掩模层24’向下延伸至并覆盖各个图案化第二导电层22’、图案化第二绝缘层16’、图案化第一导电层14’和沟槽42。
前述的图8A、图8B和图8C,在后续步骤中以图案化掩模层24’以及间隙壁30为掩模进行蚀刻至基底10表面,最后形成如图9A、图9B和图9C中所示的闪存存储器结构100,图9A为接续图8A;图9B为接续图8B;图9C为接续为图8C。
请同时参阅图7和图10,图10表示本发明闪存存储器结构在不同模式下的操作电压,本发明的闪存存储器结构100包含的第一栅极结构32与第二栅极结构34之间具有一微小间隙D,因此在进行抹除(erase)时可利用福勒-诺德汉隧穿(Fowler-Nordheimtunneling)效应或者是能带对能带隧穿(Band-To-BandTunneling)效应。根据本发明的优选实施例,闪存存储器结构100在进行写入时,在选择栅极施加1~4伏特电压,基底10施加0伏特电压,源极102施加3~5.5伏特电压,漏极104施加0伏特电压或1~2微安培,控制栅极施加8.5~13伏特电压。闪存存储器结构100在进行读取时,在选择栅极施加供电电压(Vcc)电压,基底10施加0伏特电压,源极102施加0伏特电压,漏极104施加1伏特电压,控制栅极施加Vcc电压。闪存存储器结构100利用福勒-诺德汉隧穿效应进行抹除时,在选择栅极施加0伏特电压,基底10施加7~11伏特电压,源极102维持浮置(floating)或是0伏特,漏极104施加0伏特电压或者维持浮置,控制栅极施加-7~-11伏特电压。闪存存储器结构100利用能带对能带隧穿效应进行抹除时,在选择栅极施加0伏特电压,基底10施加0伏特电压,源极102施加5~9伏特电压,漏极104施加0伏特电压或者维持浮置,控制栅极施加-7~-11伏特电压。
本发明利用间隙壁以自我对准的方式定义出第一栅极结构和第二栅极结构之间的间隙,因此第一栅极结构和第二栅极结构之间的间隙可以比一般使用光掩模定义的间隙更小,也可以避免光掩模定义时所发生的位移问题。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (15)
1.一种闪存存储器栅极结构的制作方法,包含:
提供一基底,该基底包含一阵列区;
依序形成一第一绝缘层、一第一导电层和一第二绝缘层,覆盖该基底的该阵列区;
在该第一导电层和该第二绝缘层内形成至少一第一沟槽;
在该阵列区依序形成一第二导电层和一掩模层并且覆盖该第二绝缘层,其中该第二导电层填满该第一沟槽;
形成多个图案化掩模层;
在各该图案化掩模层的两侧各形成一间隙壁;以及
以图案化掩模层与该多个间隙壁为掩模蚀刻该第一导电层,直至该第一绝缘层曝露出来,以形成一第一栅极结构和一第二栅极结构,其中该第一栅极结构包含该第一沟槽,并且该第一栅极结构与第二栅极结构之间具有一间隙。
2.如权利要求1所述的闪存存储器栅极结构的制作方法,其中该第一栅极结构包含一选择栅极结构,该第二栅极结构包含一控制栅极结构和一浮置栅极结构。
3.如权利要求1所述的闪存存储器栅极结构的制作方法,还包含:
形成一图案化光致抗蚀剂覆盖该掩模层;
以该图案化光致抗蚀剂为掩模,蚀刻该掩模层以及该第二导电层,以在该阵列区内形成该多个图案化掩模层以及多个图案化第二导电层,并且该多个间隙壁由该多个图案化掩模层延伸至该多个图案化第二导电层。
4.如权利要求3所述的闪存存储器栅极结构的制作方法,还包含:
以该图案化光致抗蚀剂为掩模蚀刻该掩模层以及该第二导电层之后,继续蚀刻该第二绝缘层,以形成多个图案化第二绝缘层,并且该多个间隙壁由该多个图案化第二导电层延伸至该多个图案化第二绝缘层。
5.如权利要求3所述的闪存存储器栅极结构的制作方法,还包含:
以该图案化光致抗蚀剂为掩模蚀刻该掩模层、该第二导电层、以及该第二绝缘层之后,继续蚀刻该第一导电层,以在该第一导电层中形成至少一第二沟槽,并且该多个间隙壁由该多个图案化第二绝缘层延伸至该第二沟槽。
6.如权利要求1所述的闪存存储器栅极结构的制作方法,其中该第一栅极结构和该第二栅极结构之间的该间隙为50至400埃。
7.一种闪存存储器结构,包含:
第一栅极结构;
第二栅极结构;以及
源极与一漏极分别设置于该第一栅极结构和该第二栅极结构;
该第一栅极结构与该第二栅极结构相邻地形成于一基底上,并且两者之间具有一间隙,该第一栅极结构与该第二栅极结构分别包含:一第一绝缘层、一第一导电层、一第二绝缘层、一第二导电层、一掩模层、以及一间隙壁覆盖于该掩模层的侧壁,其中该第一栅极结构的该第二绝缘层与该第一导电层具有一沟槽,并且该第二导电层延伸至该沟槽与该第一导电层相连接;其中该第一栅极结构作为一选择栅极,该第二栅极结构作为一控制栅极以及一浮置栅极。
8.如权利要求7所述的闪存存储器结构,其中该间隙壁向下延伸覆盖该第二导电层的侧壁。
9.如权利要求7所述的闪存存储器结构,其中该间隙壁向下延伸覆盖该第二导电层以及该第二绝缘层的侧壁。
10.如权利要求7所述的闪存存储器结构,其中该间隙壁向下延伸覆盖该第二导电层、该第二绝缘层、以及该第一导电层的侧壁。
11.如权利要求7所述的闪存存储器结构,其中该第一栅极结构与该第二栅极结构之间的该间隙为50至400埃。
12.如权利要求7所述的闪存存储器结构,其中该闪存存储器的读取方法包含:在该选择栅极施加Vcc电压,在该基底施加0伏特电压,在该源极施加0伏特电压,在该漏极施加1伏特电压,以及于该控制栅极施加Vcc电压。
13.如权利要求7所述的闪存存储器结构,其中该闪存存储器的写入方法包含:在该选择栅极施加1~4伏特电压,在该基底施加0伏特电压,在该源极施加3~5.5伏特电压,在该漏极施加0伏特电压或者1~2微安培(μA),以及于该控制栅极施加8.5~13伏特电压。
14.如权利要求7所述的闪存存储器结构,其中该闪存存储器的抹除方法包含:在该选择栅极施加0伏特电压,在该基底施加7~11伏特电压,该源极施加0伏特电压或者维持浮置,在该漏极施加0伏特电压或者维持浮置,以及于该控制栅极施加-7~-11伏特电压。
15.如权利要求7所述的闪存存储器结构,其中该闪存存储器的抹除方法包含:在该选择栅极施加0伏特电压,在该基底施加0伏特电压,该源极施加5~9伏特电压,在该漏极施加0伏特电压或者维持浮置,以及于该控制栅极施加-7~-11伏特电压。
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TWI555213B (zh) | 2016-10-21 |
TW201611303A (zh) | 2016-03-16 |
US9437600B2 (en) | 2016-09-06 |
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