CN105308732B - 包括通过平面化减少焊接垫拓扑差异的制造电子结构的方法和对应的电子结构 - Google Patents

包括通过平面化减少焊接垫拓扑差异的制造电子结构的方法和对应的电子结构 Download PDF

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Publication number
CN105308732B
CN105308732B CN201480036296.0A CN201480036296A CN105308732B CN 105308732 B CN105308732 B CN 105308732B CN 201480036296 A CN201480036296 A CN 201480036296A CN 105308732 B CN105308732 B CN 105308732B
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metal layer
welded gasket
solder
layer part
chip
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CN105308732A (zh
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J.雷
S.希亚菲诺
A.H.尼克尔
M.G.吴
S.阿克拉姆
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Lumileds Holding BV
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Lumileds Holding BV
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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Abstract

公开了一种用于使芯片（40）上的焊料凸块的顶表面处于相同平面中以确保芯片（40）与衬底（62）之间的更可靠的键合的技术。芯片（40）提供有可以具有不同高度的焊接垫（42,44）。电介质层（50）形成在焊接垫（42,44）之间。相对厚的金属层（52）电镀在焊接垫（42,44）之上。对金属层（52）平面化以使焊接垫（42,44）之上的金属层（52）部分的顶表面处于相同平面中并且处于电介质层（50）上方。基本上均匀薄的焊料层（58）沉积在平面化的金属层部分（52）之上使得焊料凸块的顶表面基本上处于相同平面中，该平面可以基本上平行于芯片（40）的顶表面或者在相对于芯片（40）的顶表面的角度处。芯片（40）然后定位在具有对应金属垫（64）的衬底（62）之上，并且使焊料（58）回流或超声键合到衬底垫（64）。

Description

包括通过平面化减少焊接垫拓扑差异的制造电子结构的方法 和对应的电子结构
对相关申请的交叉引用
本申请是要求享有2013年6月24日提交的美国临时申请序列号61/838,457的优先权的于2014年6月5日提交且题为“Reducing Solder Pad Topology Differences byPlanarization”的国际申请号PCT/IB2014/061968的§371申请。将PCT/IB2014/61968和U.S.61/838,457二者并入本文中。
技术领域
本发明涉及将芯片焊接键合到衬底，并且具体地涉及用于改进芯片上的垫与衬底上的垫之间的焊料连接的可靠性的技术。
背景技术
常见的是提供诸如半导体芯片或陶瓷基座之类的芯片上的金属垫，然后将焊料凸块沉积在垫上。垫由于芯片的变化的厚度或者由于垫具有变化的厚度而可能具有不同的高度。然后将芯片定位在包含对应金属垫的较大衬底之上，并且使焊料凸块回流以将相对的垫键合在一起以形成芯片与衬底之间的电气连接。
焊料凸块可以具有数十微米至数百微米之间的高度。这些尺寸典型地是芯片上的垫的高度中的差异的许多倍大，因此在回流期间，存在每一个垫上的充足体积的焊料以跨任何间隙桥接到衬底上的相对垫。此外，焊料凸块本身的大小多少会变化，并且相对大体积的焊料足以跨任何间隙桥接到衬底上的相对垫。
然而，对于非常小的芯片垫或者对于非常接近在一起的垫，必须使用较少的焊料。存在其中每一个垫上的小体积焊料由于芯片上的垫的高度中的差异过大而不足以在回流期间桥接焊料凸块与相对垫之间的间隙的点。因此，垫和/或其间距的大小受到限制。
图1A-1C以及图2A和2B图示了就与具有高度中的差异的垫一同使用的非充足大小的焊料凸块而言的问题。
在图1A中，示出芯片10，其可以是半导体芯片、陶瓷基座或者可以受益于小焊料凸块的其它芯片。芯片10具有小金属焊接垫12和在高度上比焊接垫12低的小焊接区域14。芯片10可以具有这样的垫12或区域14的阵列。区域14表示具有比垫12低的高度的任何焊接附连区域（其也可以是另一金属垫）。小焊料凸块16和18沉积在垫12和区域14之上并且多少在表面之上扩展开。假设焊料凸块16和18的体积相同。如果垫12或区域14较大，则焊料凸块16和18可能由于焊料的表面张力而类似于球形。
在所有实施例中，焊料凸块可以是常规的，诸如锡、铅、银、金、镍、其它金属及其合金。
在图1B中，芯片10定位在衬底20之上。注意如何抵靠衬底20上的相对金属垫22按压焊料凸块16，但是焊料凸块18与衬底20上的相对垫24略微分离。
在图1C中，图1B的结构被加热以使焊料回流。焊料凸块16形成垫16与22之间的良好键合，但是焊料凸块18分离成两个部分18A和18B并且形成垫24与区域14之间的非可靠连接。因此，需要更多的焊料并且焊接垫/区域需要更大或者更加分离。因而，垫/区域高度差异限制焊接垫/区域的大小和/或密度。
在图2A中，芯片26具有垫28和较低高度的焊接区域30，在垫28与区域30之间具有电介质部分32。相同体积焊料的凹入焊料凸块34和36形成在垫28和区域30上。
在图2B中，芯片26定位在衬底20之上。注意如何抵靠衬底20上的相对金属垫22按压焊料凸块34，但是焊料凸块36与衬底20上的相对垫24略微分离。
在回流或超声键合过程期间，焊料凸块36将不做出到相对垫24的良好连接。
所需要的是改进使用焊料凸块做出的连接的可靠性的技术，其中芯片上的焊接垫或焊接区域的高度不同。
发明内容
在一个实施例中，形成芯片以具有至少两个垫，至少两个垫具有不同的高度。出于本公开的目的，垫可以包括其中沉积焊料凸块的芯片的任何区域。垫典型地将是图案化的金属层。电介质区形成在垫之间并且具有比垫更大的高度。
对垫进行电镀以形成相对厚的金属层。在垫之上的金属层部分由于金属多少与电介质区重叠并且由于电镀过程中的非均匀性而不是平面的。也可以使用其它金属沉积技术；然而，除其它优点之外，电镀可以导致更加精细的分辨率。
然后执行化学-机械平面化（CMP）过程（或其它平面化过程）以将金属层部分平面化到多少在电介质区以上的高度。金属层部分现在形成焊接垫，其全部在相同平面中。
然后在平面化的金属层之上形成均匀焊料层，诸如通过电镀、丝网印刷或其它手段。金属层部分之上的所得焊料层因此应当基本上在相同平面中。
如果使用层状（blanket）种子层和种子层之上的图案化的抗蚀剂层执行电镀，则抗蚀剂层以及在抗蚀剂层下面的种子层然后被蚀刻掉以使金属垫电气隔离。
所得焊料部分然后可以被键合到衬底的对应垫。因此的连接在仅非常小量的焊料的情况下具有高可靠性。垫可以制作得非常小和/或非常接近在一起而没有焊料使垫短接。
时常地，焊料凸块由诸如金之类的贵金属形成。本过程大幅减少用于得到可靠互连所要求的焊料量，从而节省相当大的成本。
过程可以在单个化之后的各个芯片上或者在单个化之前在晶片级上执行。
公开了各种其它实施例。
平面化半导体晶片表面以用于晶片的后续处理是公知的并且在美国专利6,746,317中描述。本发明的过程仅平面化焊接垫，其在芯片表面以上的高度处。
还已知的是平面化焊料凸块本身，诸如在美国专利5,901,437和6,660,944中所描述的那样。然而，由于焊料凸块具有到垫的微弱键合，所以这样的平面化可能使焊料凸块移走。另外，这样的平面化可能使相对柔软的焊料凸块在横向上扩展并且产生可靠性问题。
本过程避免与现有技术相关联的这样的缺点。
附图说明
图1A是具有不同高度的焊接垫或焊接区域的现有技术芯片的横截面简化视图，其导致具有不同高度的焊料凸块。
图1B图示了定位在衬底之上的图1A的芯片。
图1C图示了在回流之后图1B的结构，其由于焊料凸块的不同高度而导致低可靠性电气连接。
图2A是具有不同高度的焊接垫或焊接区域的现有技术芯片的横截面简化视图，其导致具有不同高度的凹入焊料凸块。
图2B图示了定位在衬底上的图2A的芯片，其由于焊料凸块的不同高度而导致低可靠性电气连接。
图3图示了其中焊接垫或焊接区域具有不同高度并且其中在焊接垫/区域之间形成电介质部分的芯片的简化拓扑。
图4图示了在不进行电镀的部分之上形成的图案化的抗蚀剂层和层状沉积的金属种子层。
图5图示了在电镀过程之后的芯片。
图6图示了具有作为虚线的平面化目标的芯片。
图7图示了平面化之后的芯片，平面化使金属垫平面化，因此其顶表面处于相同平面中。
图8图示了沉积在金属垫之上的均匀焊料层。
图9图示了抗蚀剂移除和种子层回蚀刻。
图10图示了定位在衬底之上的所得芯片，其中所有垫之上的焊料触碰衬底上的对应垫或者通过不大的距离分离，使得回流过程使焊料形成相对垫之间的可靠键合。
图11图示了可以如何形成比抗蚀剂层低的经电镀的金属层，因此金属层和抗蚀剂层二者随后被平面化。
图12是标识了可以使用在本发明的一个实施例中的各种步骤的流程图。
相同或类似的元件利用相同标号标记。
具体实施方式
一般地，本发明使得能够使用较少的焊料来确保在芯片与衬底之间做出可靠连接。本发明在其中期望焊接垫是小的和/或紧密间隔的情况下尤其有用。
图3图示了芯片40，其可以是任何电子器件，诸如倒装芯片发光二极管（LED）、集成电路、陶瓷基座、插入件等。
焊接垫42形成在芯片40上。垫42可以是与半导体区接触的金属层或者垫42可以本身是半导体层。还示出区域44，其可以是其中要求金属连接的另一金属垫或半导体区。垫42和区域44是示例性实施例，其包括其中要制作焊料互连的两个不同起始高度的区域。垫42和区域44二者可以是具有不同高度的金属层。高度中的差异可以是仅几个微米。
垫42和区域44可以电气连接到半导体区或芯片40中或芯片40上的其它电路。
图案化的电介质层46形成在垫42与区域44之间以及要保护的其它区域之上。
在图4中，金属种子层48沉积在芯片40的表面之上，诸如通过溅射。种子层48可以是将电镀在种子层之上的相同金属，诸如铜或其它适当材料，或者可以是不同的传导材料。
如果电镀过程要求将电势应用到所有经电镀的区域，则种子层48提供期望电势处的传导表面。
图案化的抗蚀剂层50形成在不进行电镀的种子层48的部分之上。
在图5中，电势耦合到种子层48，诸如在芯片的边缘处，并且芯片浸入在电镀溶液中。铜电极（或者要沉积的其它金属）也浸入在电镀溶液中并且铜原子迁移到种子层48以形成相对厚的电镀层52。层52可以大于10微米厚。也可以使用无电式电镀。所使用的电镀技术可以是常规的并且不需要详细描述。可以沉积各种各样的金属。不再示出种子层，因为假设其与电镀层52合并。
电镀层52多少在电介质层46之上延伸，因为种子层48在电介质层46的边缘周围暴露。电镀层52可以是非规则或蘑菇形状。电镀层52可以具有相对于芯片40的表面更高和更低的点。在可替换方案中，电镀层52可以是相对平滑的，但是仍将具有相对于芯片40的最低点。
图6图示了多少在电镀层52的最低点以下的目标平面化线56。平面化线56可以与电介质层46齐平或者在其上方。
在图7中，执行CMP过程或者其它平面化过程以将电镀层52平面化到平面化线56（图6）。注意，电镀层52仍在抗蚀剂层50上方延伸使得平面化仅对仅一种材料进行平面化。所有电镀层部分的顶表面现在处于相同平面中。
在图8中，在平面化的电镀层52之上沉积相对薄且均匀的焊料层58使得每一个垫12和区域14之上的焊料层58的顶表面基本上是平面的。焊料层58可以通过丝网印刷、电镀、溅射或其它适当方法来沉积。焊料层58可以是任何常规金属或者金属组合，诸如金、锡、银、镍或其它金属及其合金。焊料层58可以由于电镀层52的平面表面而制作得非常薄。这导致大量的成本节约，如果焊料是贵金属的话。一个或多个界面层可以沉积在电镀层52与焊料层58之间，诸如用于得到对电镀层52的改进的润湿或键合。
在图9中，抗蚀剂层50和所暴露的种子层48被蚀刻掉以使每一个电镀层52部分之上的焊料层58电气隔离。典型地，蚀刻是化学蚀刻。
图10图示了定位在衬底62之上的所得芯片40，其中焊料层58触碰衬底62上的对应金属垫64或者通过不大的距离分离，使得回流过程使焊料层58形成相对垫之间的可靠键合。衬底62可以是印刷电路板、基座、另一芯片、插入件或任何其它类型的衬底。
如果使用超声键合过程，则键合过程的压力抵靠垫64推动焊料层58而同时使焊料层58软化并将其熔合到垫64。因此，将存在所有焊料层58部分与垫64之间的可靠连接。
图11图示了可以如何形成比芯片67上的抗蚀剂层66低的经电镀的金属层65，因此金属层65和抗蚀剂层66二者随后在相同的平面化过程期间平面化。示出目标平面化线68。
图12是标识了可以使用在本发明的一个实施例中的各种步骤的流程图。
在步骤70中，为芯片提供可以具有不同高度的焊接垫。
在步骤72中，将相对厚的金属层沉积在焊接垫之上，诸如通过电镀。
在步骤74中，对金属层平面化使得每一个垫之上的金属层的顶表面处于相同平面中。
在步骤76中，将基本上均匀薄的焊料层沉积在平面化的金属层之上，因此每一个垫之上的焊料的顶表面处于相同平面中。
在步骤78中，芯片定位在具有对应金属垫的衬底之上，并且使焊料回流或者超声键合到衬底垫。
本发明可以在芯片被单个化之前在晶片级上执行或者在芯片被单个化之后执行。
本发明适用于改进具有焊接垫的任何两个相对表面之间的焊料连接并且不限于芯片。
虽然已经示出和描述了本发明的特定实施例，但是对本领域技术人员而言将显而易见的是，可以做出改变和修改而不脱离以其较宽方面的本发明，并且因此随附权利要求要在其范围内涵盖如落入本发明的真实精神和范围内的所有这样的改变和修改。

Claims (10)

1.一种用于将电子器件键合到衬底的方法，包括：
提供电子器件（40），所述电子器件（40）具有第一焊接垫、第二焊接垫，以及由第一焊接垫与第二焊接垫之间的绝缘材料形成的电介质层，第一焊接垫和第二焊接垫具有相对于电子器件的平面第一表面的不同高度，在所述平面第一表面上形成第一焊接垫和第二焊接垫；
将第一金属层部分（52）电镀在第一焊接垫之上，所述第一金属层部分在电介质层的高度以上；
将第二金属层部分（52）电镀在第二焊接垫之上，所述第二金属层部分在电介质层的高度以上；
平面化第一金属层部分和第二金属层部分以便将第一金属层部分和第二金属层部分的相应顶表面带到相同平面中，其中平面化包括仅移除第一金属层部分和第二金属层部分的部分，所述部分在存在于第一金属层部分与第二金属层部分之间的全部绝缘材料上方延伸；
将第一焊料层（58）沉积在第一金属层部分之上；以及
将第二焊料层（58）沉积在第二金属层部分之上，使得第一焊料层的顶表面与第二焊料层的顶表面处于相同平面中。
2.权利要求1的方法，其中第一金属层部分和第二金属层部分与电介质层部分重叠。
3.权利要求1的方法，其中电子器件包括半导体芯片。
4.权利要求3的方法，还包括：
在具有第三焊接垫（64）和第四焊接垫（64）的衬底（62）上定位电子器件；
将第一焊料层键合到第三焊接垫；以及
将第二焊料层键合到第四焊接垫。
5.权利要求4的方法，其中：
通过焊料回流将第一焊料层键合到第三焊接垫，并且通过焊料回流将第二焊料层键合到第四焊接垫。
6.权利要求4的方法，其中：
通过超声键合将第一焊料层键合到第三焊接垫，并且
通过超声键合将第二焊料层键合到第四焊接垫。
7.权利要求1的方法，其中在执行平面化的步骤之后，第一金属层部分和第二金属层部分高于电介质层。
8.权利要求1的方法，其中电子器件包括发光二极管。
9.权利要求1的方法，其中电子器件包括集成电路。
10.权利要求1的方法，其中第一金属层部分和第二金属层部分的相应表面驻留在平面中，所述平面平行于电子器件的平面第一表面，在所述平面第一表面上形成第一焊接垫和第二焊接垫。
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