TWI230427B - Semiconductor device with electrical connection structure and method for fabricating the same - Google Patents

Abstract

A semiconductor device with electrical connection structure and a method for fabricating the same are proposed, wherein a pad of a semiconductor device is formed with a cavity and an insulating layer formed with openings corresponding to the pads is formed on the semiconductor device. A conductive material is formed in the opening of the insulating layer and in the cavity of the pad. By the arrangement, it can gain a bigger contact area between the conductive material and the pad, and a bigger coupling force is provided therefore, so as to improve the reliability of electrical connection of the semiconductor device.

Description

1230427 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for electrically connecting semiconductor devices, especially a circuit for carrying semiconducting semiconductors, chips, and terawatts. A structure for forming a pre-solder bump on an electrical surface of a board and a manufacturing method thereof. Connection pads [Previous technology] With the demand for light, thin, short, and high-speed products of electrical products, semiconductor packages, which are the core components of electrical products, are also becoming smaller and faster. In response to this demand, the Fup-chlp technology introduced by the packaging industry. Its technical feature is that the metal bumps are formed on the ^^ face of the semiconductor wafer 7, and then the metal bumps and the pre-soldering bumps of the circuit board are used for electrical connection. Compared with the wire bond technology, which uses gold wire to electrically connect the semiconductor chip spear circuit board, the advantage of this flip-chip technology is that it does not require the use of longer metal wires, so it can improve power consumption. The performance is the same as 4 because there is no external metal wire connection structure, so it can save packaging space. Due to various application advantages of flip chip technology, it is widely used in the packaging industry. In the current flip-chip technology, electrical electrode pads (Electrode pds) are arranged on the electrical surface of a semiconductor integrated circuit (丨 c) wafer, and a corresponding electrode pad is also formed on the organic circuit board. Contact the solder pads so that solder bumps or other conductive adhesive materials can be appropriately placed between the semiconductor wafer + and the circuit board, and 俾 provide the wafer with the electrical contact surface facing down on the offending board. The solder bump or conductive adhesive material is used to provide electrical input / output (1/0) and mechanical connection of the chip and the circuit board. Please read Figure 1A to illustrate a conventional flip chip device. As shown in the figure

17809 全懋 .ptd Page 5 1230427 V. Description of the invention (2)

The Si number of the bump U is formed on the electrode pad 12 of the wafer 13. ^ ^ ^ ^ Tsi I ^ 14 # ^ ic ^ t ^ ^ ^ 16 degree, by f The reflow temperature 11 at which the block 14 is melted, that is, ^ ft fresh tin bump 14 is re-soldered to the corresponding metal bump joint) and ^, tin is connected to 1 ?. Regarding the solder bump connection (Solder bumP ^ r " further swells the difference between the chip and the gap between the circuit board and reduces the stress of the solder joint. ...... The aforementioned conventional circuit board 16 for flip-chip packages has a plurality of contact pads 15 formed on the circuit board 16 and is formed of a metal material (such as copper). Thereafter, the circuit board 16 An organic insulating protective layer, such as a green paint, is formed on the surface of the substrate, so as to ensure the circuit layer on the surface of the circuit board and provide insulation characteristics. Among them, a plurality of openings are formed in the edge protective layer 1 60.俾 The contact pad 15 of the circuit board is exposed. Finally, a pre-soldering & block 14 is formed on the contact pad 5 for subsequent formation of a flip-chip solder joint. In addition, another contact First, a metal barrier layer i 4 〇 is formed on the fresh pimple 15. The metal barrier layer i 4 〇 = an adhesive layer and a protective layer of gold. However, the barrier layer 1 40 can also be made of Bar, silver, tin, nickel / handle, chromium / titanium, palladium / gold or nickel / palladium / gold, etc., ^ by the% bond (electroplating), without electric clock ( (electroless plat ing), chemical or physical deposition, to avoid contamination of the material (copper metal) of the contact pad 15 with subsequent pre-weld kick bumps 14 stacked on it. " The uranium industry mainly uses templates Printing technology (S tenci 1

17809 Quan 懋 · ρΐ (1

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5. Description of the invention (3) printing technology) ^ f tin bumps are formed by depositing solder material on the contact pads of the circuit board. Further, the steel plate is generally used in the industry as the plate material of the template, so the stencil printing technology can be referred to as the steel plate e brush technology. However, in actual operation, due to the current large-scale growth of various portable products such as communication, network, and brain ()? 01 '' ^ 1:) 16), the product can be greatly reduced, and the product can be reduced by 1 ^ with high density and multi-portion. Pin-shaped ball grid array (BG A ^ crystal (FI IP chip), chip size package (CSP, chip Siz / package), and multi-chip module (MCM, Multi chip m〇dule), etc. Has gradually become the mainstream in the packaging market, and often with the microprocessor,

It can be matched with high-performance chips such as graphics chips to achieve higher-speed operation. However, these structures are bound to reduce the width of the circuit and the size of the pads. When soldering = the force gap continues to shrink, because of the insulating protective layer on the circuit board Existing, 2 The area of the contact pad that shields the part, resulting in a smaller size of the pad exposed outside the insulating protective layer, resulting in the subsequent problem of the alignment of the solder bumps. At the same time, it is also occupied by the insulating protective layer. The space and the words that formed it are so loud that the stencil opening size in the stencil printing technology will inevitably shrink: the manufacturing cost of the stencil is increased only because the die ^ is not easy to open, and = The fine pitch of the openings makes it difficult for the solder material to penetrate & the bottleneck in the process technology.乂 成

. In addition to the accuracy of the leaf material, the stencil printing technique is required to be the correct size, and the number of stencil printing must be confirmed. The tin material has viscosity (Visc〇sity), and when printing ^ Bottom: The more the solder material in the hole wall of the brush m template, the more the number of solder materials used, the shape and design specifications are not 11;

1230427 V. Description of the invention (4) Therefore, in actual operation, the template must be wiped and cleaned after using a certain number of prints, otherwise problems such as the shape and size of the solder material are extremely easy to cause, resulting in inconvenience and reliability of the manufacturing process. Degree of reduction. In addition, pre-solder may be formed in the opening area of the insulating protection layer by electroplating. The contact area of the pre-solder material formed on the pad is limited, and the strength of the pre-soldering bond formed is not good enough to pass the pre-solder. Reliability test. That is, since the solder material is only formed in the opening of the insulating protection layer, and the contact between the solder material and the pad is only the size of the opening, the solder bump will not be able to provide the wafer and the wafer in subsequent processes. The effective push-pull bonding force between the circuit boards may even cause problems such as detachment or incomplete electrical connection between the chip and the circuit board. Therefore, in view of the above problems, how to avoid the problems of poor alignment of the electrical conductive material, poor bonding strength, and too low process yield, and effectively forming an electrical connection structure on a semiconductor device. Has become a problem that is urgently needed to be solved. [Summary of the Invention] In view of the shortcomings of the conventional technology described above, the main object of the present invention is to provide an electrical connection structure of a semiconductor device and a manufacturing method thereof, by increasing the contact area between the electrical connection pad of the semiconductor device and the conductive material, It is conducive to improving the strength of its binding force. Another object of the present invention is to provide an electrical connection structure of a semiconductor device and a method for manufacturing the same, which can effectively clamp a conductive material formed on the electrical connection pad of the semiconductor device and increase the push-pull force of the conductive material. Another object of the present invention is to provide an electrical connection of a semiconductor device.

17809 Quan 懋 .ptd Page 8 (5) 1230427 V. Description of the invention Structure and electrical connection The structure of the hair and its existence, resulting in the subsequent sinking of the hair and the structure and the size of the mold opening and the narrow space between the bottlenecks. The electrical structure and the electrical connection edge layer of the solder structure of the hair structure and the wall are in addition to the electrical hole; the inner side is selected for the opening method of the edge layer. Exposing the build-up solder material again—manufacturing method, ^ It ’s not easy to reduce the distance with the micro but difficult to understand _ manufacturing method, to avoid the inconvenience of the material, and the semiconducting pad of the insulation layer that can be formed as a lift-up and connection structure. An electroplated conductive material is formed in the electroactive treatment port. The purpose is to avoid the problem of the alignment of the insulating protective layer. When the purpose is to provide a free-form template, the template template is manufactured so that the solder material method is used to print a circuit on the surface of the semiconductor device. The size of the insulating protective layer existing connection pads that pass through the surface of the electrical connection board of the semiconductor device is reduced, resulting in production. In the electrical connection technology of semiconductor devices, when the hole of the electrical connection pad must be reduced accordingly, the improvement is caused, and the technical purpose of the process caused by the opening of the template is to avoid the need to learn the next time and reduce the reliability of other purposes. In the manufacturing method, the body device is formed with partial regional connections; the intermediate gold is used to provide a semiconductor substrate, and the electrical connection plate printing technology, the amount and size of the solder material remaining in the template hole, resulting in low temple problems. The semiconductor device provided by the present invention mainly includes: providing a plurality of openings formed on the surface of the semiconductor device with an absolute connection pad; The surface of the cavity and the opening of the insulation layer are the cavity of the electrical connection pad and the insulation layer (Intermedium metal);

1230427 V. Description of the invention (6) A conductive layer is formed on the intermediate metal layer and the insulating layer; a resistive layer is formed on the conductive layer on the surface of the insulating layer, and the resistive layer is formed with an opening corresponding to the position of the electrical connection pad , So as to expose the opening of the insulating layer; and deposit a conductive material in the cavity of the opening of the resistive layer, the opening of the insulating layer, and the electrical connection pad by a plating process, so as to form an electrical connection structure on the semiconductor device. Thereafter, the resist layer and the conductive layer covering the resist layer can be removed. The intermediate metal layer is mainly a barrier metal layer, so as to provide a conductive material to be effectively attached to the electrical connection pad. In another embodiment of the method for manufacturing the electrical connection structure of the semiconductor device of the present invention, a cavity is formed in the electrical connection pad as described above, and the surface of the cavity of the electrical connection pad and the insulation can be selectively selected. After the inside of the opening of the layer is activated, a conductive layer is formed on the surface of the electrical connection pad and the surface of the insulating layer, and a resist layer is formed on the conductive layer on the surface of the insulating layer, and the resist layer is formed. There is an opening corresponding to the position of the electrical connection pad to expose the opening of the insulating layer, and then an intermediate metal layer is formed in the recess of the electrical connection pad and the opening of the insulating layer, and then the opening of the resistive layer and the insulating layer are opened. By depositing a conductive material in the cavity of the electrical connection pad, an electrical connection structure can be formed on the semiconductor device. In addition, if the process reliability permits, non-electroplating methods such as printing can be selectively used to directly deposit conductive materials in the openings of the resist layer, the openings of the insulating layer, and the recesses of the electrical connection pads, thereby forming semiconductor devices. There is an electrical connection structure. Through the foregoing processes, the present invention also discloses an electrical connection structure of a semiconductor device, which mainly includes: an electrical connection formed on a surface of the semiconductor device

17809 All pt.ptd Page 10 Pad 'in the reading semi-conductor ~ ~ ^ ^ ^ ---: the insulation layer' and; the break is covered with an electrical distance from the Electrical Materials Department, filling: the sexual connection pad has Ϊ́ 成 成 有成 成 electrical: ί layer surface. 11 ί The openings of the hole and the insulation layer are layers; and the four holes and the insulation; the door structure includes -shaped ::: 彳 ". #, Formed on the intermediate metal layer or is a 夂 'system, first Fengyue After the electrical properties of the semiconductor device have been checked, the electrical tf, ,, and σ structures in the four β V body device are formed, and the acupoints in the manufacturing method are removed. Partial areas of the η and the ancient connection are removed, and there is no problem. The previously held and charged conductive material makes the conductive; the middle part of the material: area 'to improve its bonding strength, and then; the electrical connection pad edge protection layer C insulation layer is clamped (that is, the previous VH conductive The material can be provided when the material is used). Then the conductive material is filled with a large push and pull force in the 7th paper and is effectively electrically connected to ♦ 1. It is more difficult to fall off by external force. The method of the invention is "may", the invention of the semiconductor device: Γ 生;: ;; the letter of the formation of the pre :: the circuit board carrying the semiconductor wafer table and its manufacturing process, 4Ϊ: block structure, to take this one step further Avoid the habit = pads around the pads: an insulating protective layer is formed on the surface of the board to cover: at a distance of 3 electrical limits; Printing technology to solve this problem: the problem of alignment, the upper part of the mountain, solder material is deposited: ^ the openings of the board I and the size and spacing of the electrical connection pads are reduced :: lead to It is not easy to open the mold due to the reduction, the cost of manufacturing the accompanying mold clothes &

17809 Quan 懋 .ptd Page 11 1230427 V. Description of the Invention (8) Problems such as process reduction caused by problems such as wiping and stencil cleaning, and the restricted area of the pre-solder material formation, the reliability of the pre-soldering bonding force formed by the pre-solder Missing tests etc. σ A specific example illustrates an embodiment of the present invention, and the effect is easily obtained from the content disclosed in this specification. The present invention can also be used for other different applications, and the details in this specification can also be subjected to various over-depositions without departing from the spirit of the present invention. The contact with the reliability has not been passed by a specific person. Advantages and implementation or application, transfer materials are not easy to wear, technical inconvenience, the strength of the electrical connection pad is not good, and the implementation method] The following is to familiarize with this technology to explain the specific implementation examples of the present invention and repair based on different perspectives i and change. Please refer to Figure 2A to Figure 2H for the first embodiment. It is a detailed description of the manufacturing method of the electrical connection structure of the carving device of the present invention. The schematic cross-section of the first embodiment is shown in Figure 2A. Most of the electrical connection pads 2 are body devices 20. The surface of the semiconductor device 20 is covered with an insulation layer 22, and the insulation layer 22 is formed with an opening 22 corresponding to the electrical connection pad 21, and the / opening 22 0 of the The size is smaller than the size of the electrical connection pad 21. = The conductor device 20 can be a single layer or multiple carrying semiconductor wafers; bands .. or even integrated circuit (κ) components such as wafers / day-day-day-chips, etc., and the material of the J-plate '21 can be copper metal . Electricity | Wang Liandeng

As shown in FIG. 2B, a portion 21 of the electrical connection pad 21 is formed in the electrical connection pad by removing the electrical connection pad 21. The electrical connection 210 of the ° / ′ can be connected to H Μ by etching or laser etc.

Page 12

L 17809 Full 懋 .ptd 1230427

V. Description of the invention (9) The form of the cavity 2 10 is determined. For example, the size of the cavity can be controlled according to the method used in the process and the type of etching solution, and the residual profit can be controlled by the parameters in the selective residual etching process. In order to obtain different 'night concentrations, etc.', the electrical connection pad 21 is etched and the recess 2 1 0 is located at the electrical connection type, and the bottom end of the recess 2 1 0 can be erected. It is true that any one of F2 21 or the end of the electrical connection pad 2 1 is reached, but it is not necessary to limit it to the figure. Thereafter, the surface of the cavity 2 1 0 of the electrical connection pad 21 and the inside of the opening 2 2 0 of the insulating layer 22 may be selectively activated, or even extend to a part of the surface of the insulating layer 22 to enhance the subsequent The adhesion ability of a metal material is deposited thereon, wherein the activation treatment can use an electroless plating process to form a palladium, nickel, silver, copper, platinum /, mixed / silver, tin / mixed layer, and the like. In addition, after the activation treatment is extended to the surface of the insulating layer 22, the activation treatment portion formed on the surface of the insulating layer 22 may be removed by a process such as cleaning. As shown in FIG. 2C, an intermediate metal layer 23 can be formed in the recess 2 1 0 of the electrical connection pad 21 and the opening 2 2 0 of the insulating layer 22, wherein the intermediate metal Layers 2 and 3 can form barrier metal layers by electroless ore or deposition. It mainly provides the barrier effect of the electrical connection pad 21 and the conductive material formed later to prevent the material of the electrical connection pad 21 from contaminating the conductive material. Material, so that the conductive material can be effectively attached to the electrical connection pad 21. In addition, the intermediate metal layer 23 may be formed on the upper surface of the insulating layer 22 and may be removed after a conductive material is subsequently formed. Thereafter, a conductive material can be formed on the electrical connection pad by electroplating. As shown in FIG. 2D, formed on the intermediate metal layer 23 and the insulating layer 22

17809 全懋 .ptd Page 13 1230427 V. Description of the invention (10) Layer 24 'wherein the conductive layer 24 is mainly used as a current conduction path required for the electric clock process described below. It can be made of metal, alloy, and several metal layers , Carbon / graphite or conductive polymer, such as selected from the group consisting of copper, tin, antimony, gold, silver, palladium, chromium, titanium, copper-chromium alloy, tin-tallium alloy, graphite or Polypyrole conductive polymer By any one of the groups, by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, or chemical precipitation, such as sputtering (Spu 11 eri ng), evaporation (

Evaporation), Arc vapor deposition, Ion beam sputtering, Laser Fused Deposition (

Laser ablation deposition) or plasma-assisted chemical vapor deposition. However, according to practical experience, the conductive layer 24 is preferably composed of electroless copper (metal) particles. As shown in FIG. 2E, a resistive layer 25 is formed on the conductive layer 24 on the surface of the insulating layer 22, and the resistive layer 25 is formed with an opening 2 50 corresponding to the position of the electrical connection pad 21, thereby revealing The opening 2 2 0 of the insulating layer 22 and the recess 2 1 0 of the electrical connection pad 21 1, wherein the resist layer 25 is used as a plating resist layer, and it may be a film or a photoresist, etc. It is formed on the insulation layer 2 2 on the conductive layer 24 on the surface by printing, spin coating or lamination, and then it is exposed to the electrical connection pads 2 through exposure, development, or laser opening. A plurality of openings 2 5 0 are formed at the positions. As shown in FIG. 2F, a plating process is then performed to deposit a guide material 2 6 in the resist layer opening 0, the rim edge opening 2 2 0, and the recess 2 2 of the electrical connection pad 2 丨. The conductive material 25 is filled in the cavity 2 and the insulating layer opening 2 2 0, and a block HS1 m is formed on the conductive layer "on the surface of the insulating layer 22

Page 14 17809 Quan 懋 · ptd 1230427 V. Description of the invention (11) ~ ___ structure. In this way, the contact area of the conductive material 26 and Taida can be used to improve the joint strength, and the encapsulating connection pad 21 is clamped by the insulating layer 2 2 to provide a better push and pull force. The conductive material 26 is Reliability of the electrical connection of the device. Among them, the semi- * is used to increase the semiconductor board, corresponding to the conductive material is the solder material; the volume can be a circuit or a wafer / wafer integrated circuit structure, and the semiconductor device metal bumps are inclined . Corresponding to the conductive material is shown in Figure 2G, and then the conductive layer 24 can be removed. In addition, if the intermediate metal belongs to the upper surface of the insulating layer 22 and / or the upper surface of the insulating layer 22 underneath, the resistive layer extension needs to be removed to cover the layers 24 and the intermediate metal layer 23. As shown in FIG. 2H, the electrical conductivity covered by a person is shown in FIG. 2H. As previously, a semiconductor device such as solder = circuit is formed on the electrical connection pad 21 of Taiji 20, for example, enough solder can be deposited on the plating. After the material is coated with electrical material, the thinning (Ren〇W_soldering) process is performed; under the condition of melting temperature, ΐ :::: Γ is connected to 塾 21 to form a pre-fresh tin bump :: For the tin material, please refer to section Figures 3A to 3D are detailed descriptions: the manufacturing method of the electrical connection structure is described in the second embodiment of the "Semiconductor" = the second embodiment of the manufacturing process and the schematic diagram. ^ The surface of the cavity and insulation of the connection Layer i :: internally: selectively forming a resistive layer on the conductive layer on the surface of the electrically connected pits and the activation of the insulating layer through the activation of the tweeter, and the:

1230427 V. Description of the invention (12) Secondly, an opening corresponding to the position of the electrical connection pad is formed, and a layer opening is formed in the cavity of the electrical connection pad to expose the insulation as an intermediate metal layer, and then the resistance layer The iU:; :: 4 is electrically connected to the structure by depositing a conductive material in the hollow in the opening / mouth and layer opening.形成 ¥ limb device formation As shown in Figure 3A, a set is provided, set 2. ， 料 臂 装置 2。 Material conductor device 2. Table: 彳; Yes, half of the insulating layer 22 is formed corresponding to the electrical connection pad 2 =, 彖 f 22, and a cavity 2 is formed in the electrical connection pad 21] 〇: 幵 1 口 220, The recess of the sub-electrical connection pad 2 1? · | Η 矣 and /, /, the reverse connection to the surface of mu 8 2 10 and the insulating layer or even extending to part of the surface of the insulating layer 22 may be selectively performed. The inner side is subsequently deposited with a metal material thereon. Adhesion. & Refinement to improve As shown in Fig. 3B, the insulating layer 22 and the recess are used as a conductive layer 24 required for the plating process described later. , 乂 -resistance to the insulating layer "face: an opening t Λ is formed on the conductive layer 24 corresponding to 2 50 of the position of the electrical connection pad 21, so that the opening of the insulating layer 2 2 〇 and the cavity 2 1 〇. As in the 3D picture, you can choose to form an intermediate metal layer on the hole 210 of the free connection pad 21 and the conductive layer 24 of the insulating layer opening 220. 23 is mainly to provide the electrical connection to form a rail \ intermetallic layer 23, and the barrier effect of the electrical material [this;:; and the subsequent formation of the upper surface of the insulating layer 22 can also be extended to form a layer 24 as a whole to cover a Middle KdH 2 layer 24, and then a resistance layer 25 and a metal layer 23 are formed on the conductive layer 23, and then on the intermediate metal

17809 Quan 懋 .ptd Page 16 Xiao 1230427 V. Description of the invention (13) As shown in Figures 3E and 3F, the electrical data manufacturing process is performed so that the resistance layer 1 = soil 50, insulation layer opening 22, and electrical properties After connecting the four holes 21 of the 蛰 21, the middle dentist & electrical material 2 6 ′, after the electrical connection structure is formed on the semiconductor device, the resist layer 2 5 and the conductive layer 2 4 covering the lower layer can be removed. . In addition, if the layer 25 is also covered with the intermediate metal layer 23 before the rain, the resistance layer 25 and the intermediate metal layer 23 covering the conductive layer 24 portion of the disk need to be removed. Third Embodiment Please refer to FIG. 4A to FIG. 4E for details of the nature of the semiconductor device of the present invention. The process of the second embodiment of the present invention is similar to that of the first embodiment. The main difference is that a cavity is formed in the electrical connection pad, and then the surface of the cavity of the electrical connection pad and the opening of the insulating layer are selectively opened. The inner side is subjected to activation treatment, and an intermediate gold f layer is formed in the cavity of the electrical, connection pad and the opening of the insulating skin, and then a / resistive layer is formed on the surface of the insulating layer, and the resistive layer forms $ n, the The opening at the position of the electrical connection pad can be removed later and the process reliability can be reduced by using a non-electroplating method such as printing to deposit conductive materials in the opening of the resistance layer, the opening of the insulation layer and the recess of the electrical connection pad. This forms an electrical connection structure on the semiconductor device. Guide: 1 = Figure :: 'Provided-with half of most electrical connection pads 21, the insulating layer 22 is formed with an insulating layer 22 covered on both sides, and at the electrical connection 塾 = 连接 塾 21 处Open. 22〇, 雷雷 W, 查 埶 1 9 1 on on ^ to have a cavity 2 1 0, and then you can selectively electrically connect the entire 2 1 cavity? 1〇 本 二 ^ Straight 说 u said that the surface of the stone and the opening of the insulation layer 2 2 2 2 0 inside or even extend to part of the insulation sound 矣 The surface of the insulation layer is activated to improve

Page 17 17809 Quan Lian. Ptd 1230427 Friends, description of invention (14) Adhesion ability of subsequent deposition of metal materials on it. As shown in Figure 4B, the shop, the ρε detection bucket, and the insulation layer D = ί electrical connection 塾 21 of the concave 210210 23 are mainly provided to form the intermediate metal layer 23, the effect of the intermediate metal layer. "Λ ^ The connection pad 21 and the subsequent conductive material barriers are as shown in Figure 4C-Pigeon resistance layer 25 is formed with: 庳: = edge layer 22 surface formation-resistance layer ⑺, and to expose the insulating layer door : ^ Connect to the opening at 2 1 2 2 0, such as the second Pei ^ 2〇 \ Electrically connect 塾 also concave hole. Use printing, no electricity Thai '^ under the premise of process reliability permission, in order to prevent this Layer opening ^ # Pre-deposition and physical deposition of non-electroplated electrical materials 26, so that the resist layer 25 can be removed after the deposition is performed in the 2 'conductive layer opening 220 and the four holes 210. The platen is placed on An electrical connection structure is formed. For details, please refer to the electrical connection f of the semiconductor device described in Section 2G and yip. After the foregoing process, the electrical connection structure on the surface of the conductor device 20 mainly includes an electrode formed on The half cover is electrically connected to the south connection pad 21, and the semiconductor device 20 is covered with a U connection pad 21. A 20 electrical connection pad 21 is formed in the right 5 hours—bar, 豕Continue to zz and θ 5 # ^ ^ ^ ηπ ^ recess 2 1 〇; and a conductive material 2 6 surface. In addition, the electrical connection junction layer opening and the insulation The layer 22 is formed in the cavity 2 1 0 and the insulation layer D 彳 = ^ includes at least one shape. ^ A 〇1 D 22 0 The intermediate metal layer 23 on the inner surface is formed on the intermediate metal layer- or The middle / middle metal layer 2 3 may have a multi-layer structure, which may be used for the electrical connection pad 2 j.

1230427 V. Description of the invention (15) 乂 and 'electrical materials 2 6 provide a good bonding force, but also have a barrier effect to stop the pen-shaped connection pad 2 1 metal materials (such as copper) invading conductive materials 2 6 (Such as solder material) and destroy its bonding force. The intermediate metal layer 23 may be formed of 4 J such as silicon, copper, tin, titanium, aluminum, silver, chromium, and combinations thereof. The function of the recesses 2 1 0 of the electrical connection pad 21 is to provide subsequent deposition of the conductive material 26 and the electrical connection pad 21 with a larger contact area, so that the conductive material 26 and the electrical connection pad 2 1 has a large binding force and push-pull force. In addition, the form and size of the cavity 2 1 0 of the electrical connection pad 21 are determined according to the method and equipment used in the process. The shape of the cavity 2 1 0 can be shown in Figure 2G, 3F or 4E. It is a hole with a non-fixed inner diameter that gradually decreases downward, and the inner diameter at the largest inner diameter is greater than the inner diameter of the insulating layer 22 = 20. Of course, in another embodiment, the cavity is I, as shown in FIG. 5A, is a hole with an inner diameter that gradually expands downward, and has an inner diameter of 2 openings at the minimum inner diameter. ^ The inner diameter of the opening 22 of the layer 22; It is known that the shape of the recess 91 η can be substantially fixed inside as shown in FIG. 5B / that is, without affecting the mechanical material of the conductive material itself = holes. Also, 2 10 can be changed in any form. With 6 of X, the cavity 21 has a larger contact area. 'Material 26 and the electrical connection pad are therefore the electrical properties of the semiconductor device of the present invention' after the cavity formed in the electrical connection pad in the semiconductor device and its manufacturing method is filled with a trowel area to remove the bottom end (I.e., previously filled in the electro-Ke% '俾, so that the conductive material has a larger contact area to connect the cavity portion) and the electrical connection pad ^ to increase its bonding strength, and further, the conductive material

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1230427 V. Description of the invention (16) The middle part of the material is clamped by the insulating layer, and the opening of the protective layer), which is filled by the subsequent material f; for better push and pull force: electricity: material two It is connected to electricity; it has a large external force and is less likely to fall off, so as to support the electronic device. Then go to Xia Er from k Nan Lei ^ The semiconductor device of the invention t < + (4 _ Health connection point can be used for Cheng Yunsheng it touch P, Xia Zhi electrical connection station, the structure, and its System :: J can be used to carry semiconductor wafers :; Pre-soldering bumps are formed on the top surface of the board. In the $ structuring process of the surface of the circuit board, the structure of the block, do you enter ~ + put it, electrical connection and connection On the surface of the F1 circuit board for pads, two-k white and one-kilometer pre-soldering solder bumps are formed around the surface, and the protective layer is used at the expense of the two-k. The electrical alignment asks the upper surface t of the connection pad portion to open holes in the insulation protection board and when the electrical connection pad size = the tin material is not caused by the accumulation of solder material [the template opened Reduced die size and spacing, accompanied by excessive X-tooth deposition in the mold technology, problems with template privacy, increased manufacturing costs, welded electrical connection and reduced reliability, and other issues such as cleaning lead to poor process strength , The contact area on the pad is limited, and the pre-solder material forms a solder I 'and fails to pass the pre-solder & g t; 'The formation of the pre-solder bonding force structure and its manufacturing method% Attention, the Z-degree test of the present invention is missing, etc. It is applied to wafers, except that it can be applied to the electrical connection of 2 conductor devices on circuit boards / Integrated circuit junctions such as wafers; ^ Pre-solder bump process, work that can also be produced: The examples described are only examples: the electrical connection structure is familiar with this technology to limit the present invention; = characteristics of the invention and its application The second person of the invention does not violate the scope of this smoke two spirits, so it is covered by any. The modification and changes of quadron are all completed under the spirit and scope of the month ~ The scope of patent application described later

1230427 Brief description of the drawings [Simplified description of the drawings] Fig. 1 A is a schematic cross-sectional view of a conventional flip-chip package. Fig. 1B is a cross-sectional schematic view of a conventional circuit board used for the flip-chip package. Figs. 2A to 2H are Sectional schematic diagrams of the first embodiment of the method of manufacturing the electrical connection structure of the semiconductor device of the present invention. Figures 3A to 3F are schematic cross-sectional diagrams of the second embodiment of the method of manufacturing the electrical connection structure of the semiconductor device of the invention. Figure E is a schematic cross-sectional view of the third embodiment of the method for manufacturing the electrical connection structure of the semiconductor device of the present invention. J and 5A and 5B are schematic cross-sectional views of the different implementation modes of the electrical connection structure of the semiconductor device of the present invention. . (Description of component symbols) 11 Metal bumps 12 Electrode pads 13 Semiconductor wafers 14 Pre-solder bumps 140 Barrier layer 1 5 Contact pads 16 Circuit board 160 Insulation protective layer 17 Solder connection 18 Primer material 20 Semiconductor device 21 Electrical Connection pad 210 Cavity 22 Insulation layer 220 Opening 23 Intermediate metal layer 24 Conductive layer 25 Resistive layer 250 Opening 26 Conductive material 260 Pre-soldering bump

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Claims (1)

1230427 VI. Scope of patent application 1. A method for manufacturing an electrical connection structure of a semiconductor device, comprising: providing a semiconductor device having a plurality of electrical connection pads formed thereon, the surface of the semiconductor device is covered with an insulating layer, and the insulating layer is formed with Corresponds to the opening at the electrical connection pad; removes a part of the area of the electrical connection pad so as to form a cavity in the electrical connection pad; and corresponds to the position of the electrical connection pad to the surface of the insulation layer and the opening A conductive material is formed in the cavity of the electrical connection pad, thereby forming an electrical connection structure on the semiconductor device. 2. For example, the method for manufacturing an electrical connection structure of a semiconductor device according to item 1 of the scope of patent application, wherein after forming the cavity of the electrical connection pad, selectively selecting the surface of the cavity of the electrical connection pad and the insulation layer The inside of the opening is activated. 3. For the method of manufacturing an electrical connection structure of a semiconductor device according to item 1 or 2 of the patent application scope, wherein an intermediate gold layer (Intermedium metal) is selectively formed on the recessed surface of the electrical connection pad and the opening surface of the insulating layer. ) To provide effective attachment of conductive materials thereto. 4. For the method for manufacturing an electrical connection structure of a semiconductor device according to item 3 of the patent application, wherein after the intermediate metal layer is formed, a conductive layer can be formed on the surface of the insulation layer, the opening, and the electrical connection pad to make use of Electrical forging forms conductive materials. 5. The method for manufacturing an electrical connection structure of a semiconductor device according to item 3 of the patent application, wherein the intermediate metal layer is a barrier metal layer. 6. The electrical connection structure of the semiconductor device such as the scope of application for patent No. 1 17809 Quan 懋 .ptd Page 22 1230427 6. The method of applying for a patent, wherein the method of forming the conductive material includes: forming a conductive layer on the surface of the insulating layer, the opening and the electrical connection pad; and forming a conductive layer on the surface of the insulating layer. A resist layer is formed on the conductive layer, and the resist layer is formed with an opening corresponding to the position of the electrical connection pad; and a plating process is performed to deposit a conductive material in the opening of the resistance layer, the opening of the insulation layer and the cavity of the electrical connection pad. . 7. If the method for manufacturing an electrical connection structure of a semiconductor device according to item 6 of the patent application, the method further includes removing the resistive layer and covering the conductive layer underneath. 8. For the method for manufacturing an electrical connection structure of a semiconductor device according to item 6 of the application for a patent, wherein after the conductive layer is formed, an intermediate metal layer can be formed on the recess of the electrical connection pad and the opening surface of the insulating layer. (Intermedium metal) in order to provide a conductive material to effectively adhere to it. 9. The manufacturing method of the electrical connection structure of a semiconductor device, such as in the first patent application, wherein the manufacturing method of forming the conductive material includes: on the surface of the insulating layer A resistive layer is formed on the conductive layer, and the resistive layer is formed with an opening corresponding to the position of the electrical connection pad; and a non-electroplating method is used to deposit in the opening of the resistance layer, the opening of the insulation layer and the cavity of the electrical connection pad Conductive material. 10. The method for manufacturing an electrical connection structure of a semiconductor device according to item 9 of the scope of patent application, wherein the non-electroplating method can use one of printing, electroless plating, chemical deposition, and physical deposition. 1 1. The electrical connection structure of the semiconductor device as described in item 1 of the scope of patent application 17809 Quan 懋 .ptd Page 23 1230427 VI. Patent application method, wherein the semiconductor device is one of a circuit board carrying a semiconductor wafer and an integrated circuit (IC) component. 12. The method for manufacturing an electrical connection structure of a semiconductor device according to item 1 of the scope of patent application, wherein the conductive material is a solder material. 1 3. The method for manufacturing an electrical connection structure of a semiconductor device according to item 1 of the scope of patent application, wherein the opening size of the insulating layer is smaller than the size of the electrical connection pad. 1 4. An electrical connection structure for a semiconductor device, comprising: an electrical connection pad formed on a surface of the semiconductor device; covering the semiconductor device with an insulating layer having an opening formed at the electrical connection pad; and the electrical connection pad The electrical connection pad has at least one cavity; and a conductive material corresponding to the position of the electrical connection pad to fill the cavity of the electrical connection pad and the opening of the insulation layer and part of the surface of the insulation layer. 15. The electrical connection structure of a semiconductor device according to item 14 of the scope of patent application, wherein the electrical connection structure further includes an intermediate metal layer formed in a recess of the electrical connection pad and an inner surface of the opening of the insulation layer. . 16. The electrical connection structure of a semiconductor device according to item 15 of the scope of patent application, wherein the electrical connection structure further includes a conductive layer formed on the intermediate metal layer. 1 7. The electrical connection structure of a semiconductor device according to claims 1-5, wherein the electrical connection structure further includes a conductive layer covered by the intermediate metal layer. 18. The electrical connection structure of the semiconductor device as described in item 15 of the scope of patent application 17809 Quan 懋 .ptd Page 24 1230427 6. Scope of patent application, where the intermediate metal layer is a barrier metal layer. 19. The electrical connection structure of the semiconductor device according to item 14 of the scope of patent application, wherein the semiconductor device is a circuit board carrying a semiconductor wafer. 20. The electrical connection structure of the semiconductor device according to item 14 of the scope of patent application, wherein the conductive material is a solder material. 2 1. The electrical connection structure of the semiconductor device according to item 14 of the scope of patent application, wherein the size of the opening of the insulating layer is smaller than the size of the electrical connection pad 17809 懋 .ptd Page 25