TWI622108B - 藉由平坦化減少焊墊拓撲差異 - Google Patents

藉由平坦化減少焊墊拓撲差異 Download PDF

Info

Publication number
TWI622108B
TWI622108B TW103121674A TW103121674A TWI622108B TW I622108 B TWI622108 B TW I622108B TW 103121674 A TW103121674 A TW 103121674A TW 103121674 A TW103121674 A TW 103121674A TW I622108 B TWI622108 B TW I622108B
Authority
TW
Taiwan
Prior art keywords
pad
solder
layer
metal layer
pads
Prior art date
Application number
TW103121674A
Other languages
English (en)
Other versions
TW201503271A (zh
Inventor
賴金
史帝法諾 史恰非諾
亞歷山卓 尼克
黃穆娟
沙爾 雅克藍
Original Assignee
皇家飛利浦有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 皇家飛利浦有限公司 filed Critical 皇家飛利浦有限公司
Publication of TW201503271A publication Critical patent/TW201503271A/zh
Application granted granted Critical
Publication of TWI622108B publication Critical patent/TWI622108B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825—Plating, e.g. electroplating, electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11826—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/11845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13564—Only on the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本發明揭示一種用於引起一晶片上之焊料凸塊之頂面位於相同平面中以確保該晶片與一基板之間之一更可靠接合的技術。該晶片具有可具有不同高度之焊墊。一介電層形成於該等焊墊之間。一相對較厚金屬層電鍍於該等焊墊上方。該金屬層經平坦化以引起該等焊墊上方之該等金屬層部分之頂面位於相同平面中且位於該介電層上方。焊料之一實質上均勻薄層沈積於該等平坦化金屬層部分上方，使得該等焊料凸塊之頂面實質上位於相同平面中。接著，將該晶片定位於具有對應金屬墊之一基板上方，且將該焊料回焊或超音波接合至該等基板墊。

Description

藉由平坦化減少焊墊拓撲差異
本發明係關於將一晶片焊料接合至一基板，且特定言之，本發明係關於一種用於改良該晶片上之墊與該基板上之墊之間之焊料連接之可靠性的技術。
通常，將金屬墊提供於一晶片(諸如一半導體晶片或一陶瓷子基板)上，接著將焊料凸塊沈積於該等墊上。歸因於該晶片之一變動厚度或歸因於具有變動厚度之該等墊，該等墊可具有不同高度。接著，將該晶片定位於含有對應金屬墊之一更大基板上方，且該等焊料凸塊經回焊以將相對墊接合在一起以在該晶片與該基板之間形成電連接。
焊料凸塊可具有數十微米至數百微米之間之高度。此等尺寸通常比晶片上之墊之高度差大諸多倍；因此，在回焊期間，各墊上存在足夠體積之焊料以跨任何間隙橋接至基板上之一相對墊。此外，焊料凸塊本身之大小略微變動，且相對較大體積之焊料足以跨任何間隙橋接至基板上之一相對墊。
然而，對於非常小之晶片墊或對於非常緊密地靠在一起之墊，必須使用更少焊料。存在其中歸因於晶片上之墊之高度差過大而使各墊上之小體積焊料不足以在回焊期間橋接一焊料凸塊與相對墊之間之一間隙的一點。因此，墊之大小及/或其節距受限制。
圖1A至圖1C及圖2A及圖2B繪示與具有高度差之墊一起使用之一大小不足焊料凸塊之問題。
圖1A中展示一晶片10，其可為可受益於小焊料凸塊之一半導體晶片、一陶瓷子基板或其他晶片。晶片10具有一小金屬焊墊12及一小焊料區域14，焊料區域14之高度低於焊墊12之高度。晶片10可具有一陣列之此等墊12或區域14。區域14表示具有低於墊12之一高度的任何焊料附接區域(其亦可為另一金屬墊)。小焊料凸塊16及18沈積於墊12及區域14上方，且在表面上方略微散開。假定：焊料凸塊16及18之體積相同。若墊12或區域14更大，則焊料凸塊16及18可歸因於焊料之表面張力而類似於一球體。
在所有實施例中，焊料凸塊可為習知的，諸如錫、鉛、銀、金、鎳、其他金屬及其等之合金。
在圖1B中，晶片10定位於一基板20上方。應注意如何使焊料凸塊16緊貼基板20上之相對金屬墊22，但焊料凸塊18與基板20上之相對墊24略微分離。
在圖1C中，圖1B之結構經加熱以回焊焊料。焊料凸塊16在墊16與22之間形成一良好接合，但焊料凸塊18分離成兩個部分18A及18B且在墊24與區域14之間形成一不可靠連接。因此，需要更多焊料且需要更大或進一步分離之焊墊/區域。因此，墊/區域之高度差限制焊墊/區域之大小及/或密度。
在圖2A中，一晶片26具有一墊28及一更低高度之焊料區域30，其中一介電部分32介於墊28與區域30之間。具有相同體積焊料之凹進焊料凸塊34及36形成於墊28及區域30上。
在圖2B中，晶片26定位於基板20上方。應注意如何使焊料凸塊34緊貼基板20上之相對金屬墊22，但焊料凸塊36與基板20上之相對墊24略微分離。
在回焊或一超音波接合程序期間，焊料凸塊36不會形成至相對墊24之一良好連接。
需要一種改良使用焊料凸塊來形成之連接之可靠性的技術，其中一晶片上之焊墊或焊料區域之高度不同。
在一實施例中，一晶片經形成以具有至少兩個墊，該兩個墊具有不同高度。為本發明之目的，一墊可包含其中將沈積一焊料凸塊之該晶片之任何區域。該等墊將通常為一圖案化金屬層。一介電區域形成於該等墊之間且具有大於該等墊之一高度。
該等墊經電鍍以形成一相對較厚金屬層。歸因於金屬與該介電區域略微重疊且歸因於電鍍程序之不均勻性，該等墊上方之該等金屬層部分不平坦。亦可使用其他金屬沈積技術；然而，電鍍可導致一更精細解析度及其他優點。
接著，一化學機械平坦化(CMP)程序(或其他平坦化程序)經執行以使該等金屬層部分平坦化至略微高於該介電區域之一高度。該等金屬層部分現形成全部位於相同平面中之焊墊。
接著，(諸如)藉由電鍍、網版印刷或其他方法來在該平坦化金屬層上方形成焊料之一均勻層。因此，該金屬層部分上方之所得焊料層應實質上位於相同平面中。
若使用一毯覆性晶種層及該晶種層上方之一圖案化光阻層來執行電鍍，則該光阻層及該光阻層下方之該晶種層經蝕除以使金屬墊電隔離。
接著，所得焊料部分可接合至一基板之對應墊。因此，連接具有與僅極少焊料量之一高可靠性。可在焊料不短接墊之情況下使墊非常小及/或非常緊密地靠在一起。
通常，焊料凸塊由一貴金屬(諸如金)形成。目前程序顯著減少可 靠互連所需之焊料量以節約相當大成本。
可對單粒化之後之個別晶片或對單粒化之前之一晶圓片執行程序。
本發明揭示各種其他實施例。
吾人已熟知使用於晶圓之後續處理的一半導體晶圓表面平坦化且美國專利6,746,317中描述使用於晶圓之後續處理的一半導體晶圓表面平坦化。本發明之程序僅使具有高於晶片表面之一高度的焊墊平坦化。
吾入亦已知使焊料凸塊本身平坦化，諸如美國專利5,901,437及6,660,944中所描述。然而，由於焊料凸塊具有至墊之一弱接合，故此平坦化可使焊料凸塊脫位。此外，此平坦化可橫向地散佈相對較軟焊料凸塊且產生可靠性問題。
本發明之程序避免與先前技術相關聯之此等缺點。
10‧‧‧晶片
12‧‧‧金屬墊
14‧‧‧區域
16‧‧‧焊料凸塊
18‧‧‧焊料凸塊
18A‧‧‧部分
18B‧‧‧部分
20‧‧‧基板
22‧‧‧金屬墊
24‧‧‧墊
26‧‧‧晶片
28‧‧‧墊
30‧‧‧區域
32‧‧‧介電部分
34‧‧‧焊料凸塊
36‧‧‧焊料凸塊
40‧‧‧晶片
42‧‧‧焊墊
44‧‧‧區域
46‧‧‧介電層
48‧‧‧晶種層
50‧‧‧光阻層
52‧‧‧電鍍層
56‧‧‧平坦化線
58‧‧‧焊料層
62‧‧‧基板
64‧‧‧金屬墊
65‧‧‧金屬層
66‧‧‧光阻層
67‧‧‧晶片
68‧‧‧平坦化線
70‧‧‧步驟
72‧‧‧步驟
74‧‧‧步驟
76‧‧‧步驟
78‧‧‧步驟
圖1A係具有不同高度之焊墊或焊料區域以導致不同高度之焊料凸塊的一先前技術晶片之一橫截面簡化圖。
圖1B繪示定位於一基板上方之圖1A之晶片。
圖1C繪示歸因於焊料凸塊之不同高度而導致低可靠性電連接之回焊之後之圖1B之結構。
圖2A係具有不同高度之焊墊或焊料區域以導致具有不同高度之凹進焊料凸塊的一先前技術晶片之一橫截面簡化圖。
圖2B繪示歸因於焊料凸塊之不同高度而導致低可靠性電連接之定位於一基板上之圖2A之晶片。
圖3繪示其中焊墊或焊料區域具有不同高度且其中一介電部分形成於焊墊/焊料區域之間之一晶片之一簡化拓撲。
圖4繪示毯覆式沈積於將不被電鍍之部分上方之一金屬晶種層及 形成於將不被電鍍之部分上方之一圖案化光阻層。
圖5繪示一電鍍程序之後之晶片。
圖6繪示具有以一虛線位準之平坦化目標之晶片。
圖7繪示平坦化之後以使金屬墊平坦化且因此使該等金屬墊之頂面位於相同表面中之晶片。
圖8繪示沈積於金屬墊上方之焊料之一均勻層。
圖9繪示光阻層移除及晶種層回蝕。
圖10繪示定位於一基板上方之所得晶片，其中所有墊上方之焊料觸碰該基板上之對應墊或與該基板上之對應墊間隔一微小距離，使得回焊程序引起焊料在相對墊之間形成一可靠接合。
圖11繪示可如何形成低於光阻層之電鍍金屬層，因此隨後使金屬層及光阻層兩者平坦化。
圖12係識別可用於本發明之一實施例中之各種步驟的一流程圖。
使用相同元件符號來標記相同或類似元件。
一般而言，本發明能夠使用更少焊料來確保一晶片與一基板之間形成可靠連接。本發明對期望焊墊較小及/或間隔緊密之情況尤其有用。
圖3繪示可為任何電子裝置(諸如一覆晶發光二極體(LED)、一積體電路、一陶瓷子基板、一插入器等等)之一晶片40。
一焊墊42形成於晶片40上。墊42可為接觸一半導體區域之一金屬層或墊42本身可為一半導體層。圖中亦展示一區域44，其可為其中需要一金屬連接之另一金屬墊或半導體區域。墊42及區域44係一例示性實施例，其包含其中將形成一焊料互連之兩個不同起始高度之區域。墊42及區域44之兩者可為具有不同高度之金屬層。高度差可僅為 數微米。
墊42及區域44可電連接至晶片40中或晶片40上之半導體區域或其他電路。
圖案化介電層46形成於墊42與區域44之間且形成於將受保護之其他區域上方。
在圖4中，一金屬晶種層48(諸如)藉由濺鍍來沈積於晶片40之表面上方。晶種層48可為將電鍍於晶種層上方之相同金屬(諸如銅或其他適合材料)，或可為一不同導電材料。
若電鍍程序需要將一電位施加至所有電鍍區域，則晶種層48提供具有所要電位之導電表面。
一圖案化光阻層50形成於將不被電鍍之晶種層48之部分上方。
在圖5中，一電位(諸如)在晶片之一邊緣處耦合至晶種層48，且晶片浸漬於一電鍍溶液中。一銅電極(或待沈積之其他金屬)亦浸漬於該電鍍溶液中，且銅原子遷移至晶種層48以形成一相對較厚電鍍層52。層52可大於10微米厚。亦可使用無電極電鍍。所使用之電鍍技術可為習知的且無需加以詳細描述。可沈積各種金屬。由於假定晶種層與電鍍層52合併，故圖中不再展示晶種層。
電鍍層52在介電層46上方略微延伸，此係因為晶種層48暴露於介電層46之邊緣周圍。電鍍層52可為一不規則形狀或一蘑菇形狀。電鍍層52可具有比晶片40之表面高及低之點。在替代例中，電鍍層52可相對較平滑，但仍將具有相對於晶片40之一最低點。
圖6繪示略微低於電鍍層52之最低點的一目標平坦化線56。平坦化線56可與介電層46齊平或高於介電層46。
在圖7中，一CMP程序或其他平坦化程序經執行以使電鍍層52平坦化至平坦化線56(圖6)。應注意，電鍍層52仍在光阻層50上方延伸，使得平坦化僅使僅一種材料平坦化。所有電鍍層部分之頂面現位 於相同平面中。
在圖8中，一相對較薄且較均勻之焊料層58沈積於平坦化電鍍層52上方，使各墊12及區域14上方之焊料層58之頂面實質上平坦。可藉由網版印刷、電鍍、濺鍍或其他適合方法來沈積焊料層58。焊料層58可為任何習知金屬或金屬組合，諸如金、錫、銀、鎳或其他金屬及其等之合金。焊料層58可歸因於電鍍層52之平坦表面而被製成非常薄。若焊料係一貴金屬，則此導致實質成本節省。一或多個介面層可沈積於電鍍層52與焊料層58之間(諸如)以用於改良潤濕性或接合至電鍍層52。
在圖9中，光阻層50及暴露晶種層48經蝕除以電隔離各電鍍層52之部分上方之焊料層58。通常，蝕刻係一化學蝕刻。
圖10繪示定位於一基板62上方之所得晶片40，其中焊料層58觸碰基板62上之對應金屬墊64或與基板62上之對應金屬墊64間隔一微小距離，使得回焊程序引起焊料層58在相對墊之間形成一可靠接合。基板62可為一印刷電路板、一子基板、另一晶片、一插入器或任何其他類型之基板。
若使用一超音波接合程序，則該接合程序之壓力推動焊料層58抵著墊64，同時軟化焊料層58且將焊料層58熔合至墊64。因此，所有焊料層58之部分與墊64之間將存在一可靠連接。
圖11繪示可如何形成低於晶片67上之光阻層66的電鍍金屬層65，因此隨後在相同平坦化程序期間平坦化金屬層65及光阻層66兩者。圖中展示目標平坦化線68。
圖12係識別可用於本發明之一實施例中之各種步驟的一流程圖。
在步驟70中，給一晶片提供可具有不同高度之焊墊。
在步驟72中，(諸如)藉由電鍍來將一相對較厚金屬層沈積於該等 焊墊上方。
在步驟74中，該金屬層經平坦化使得各墊上方之該金屬層之頂面位於相同平面中。
在步驟76中，將焊料之一實質上均勻薄層沈積於該平坦化金屬層上方，使得各墊上方之焊料之頂面位於相同平面中。
在步驟78中，將該晶片定位於具有對應金屬墊之一基板上方，且將焊料回焊或超音波接合至該等基板墊。
可在單粒化晶片之前對一晶圓片執行本發明或在單粒化晶片之後執行本發明。
本發明適用於改良具有焊墊之任何兩個相對表面之間之焊料連接且不限於晶片。
儘管已展示及描述本發明之特定實施例，然熟習此項技術者將明白，可在不脫離本發明之情況下於本發明之更廣態樣中進行改變及修改，因此，隨附申請專利範圍將使落於本發明之真實精神及範疇內之所有此等改變及修改包含於申請專利範圍之範疇內。

Claims (10)

  1. 一種將一電子裝置與一基板接合之方法，其包括：提供一電子裝置，該電子裝置具有一第一焊墊(solder pad)、一第二焊墊及一介電層，該介電層在該第一焊墊和第二焊墊之間由絕緣材料形成，該第一焊墊及該第二焊墊相對於在其上形成有該第一焊墊及該第二焊墊的該電子裝置之一表面具有不同高度；將一第一金屬層電鍍(plating)於該第一焊墊上方高於該介電層之一高度；將一第二金屬層電鍍於該第二焊墊上方高於該介電層之該高度；平坦化該第一金屬層及該第二金屬層使該第一金屬層及該第二金屬層的各自頂面(top surface)在相同平面(plane)，其中該平坦化包含僅移除延伸於存在於該第一金屬層與該第二金屬層之間的所有絕緣材料之上(above)之該第一金屬層及該第二金屬層之部分；將一第一焊料層沈積於該第一金屬層部分上方(over)；及將一第二焊料層沈積於該第二金屬層部分上方。
  2. 如請求項1之方法，其中該第一金屬層及該第二金屬層部分地與該介電層重疊。
  3. 如請求項1之方法，其中該電子裝置包含一半導體晶片。
  4. 如請求項3之方法，其進一步包括：將該電子裝置定位於具有一第三焊墊及一第四焊墊之一基板；將該第一焊料層接合至該第三焊墊；及 將該第二焊料層接合至該第四焊墊。
  5. 如請求項4之方法，其中：藉由回焊(solder reflow)將該第一焊料層接合至該第三焊墊，及藉由回焊將該第二焊料層接合至該第四焊墊。
  6. 如請求項4之方法，其中：藉由超音波接合將該第一焊料層接合至該第三焊墊，及藉由超音波接合將該第二焊料層接合至該第四焊墊。
  7. 如請求項1之方法，其中在實施平坦化之步驟之後，該第一金屬層及該第二金屬層均具有一第一高度，該第一高度高於該介電層的一第二高度。
  8. 如請求項1之方法，其中該電子裝置係包含一發光二極體。
  9. 如請求項1之方法，其中該電子裝置包含一積體電路。
  10. 如請求項1之方法，其中該第一金屬層及該第二金屬層之各自表面所在(reside)的該平面平行於其上形成有該第一焊墊及該第二焊墊的該電子裝置的該表面。
TW103121674A 2013-06-24 2014-06-24 藉由平坦化減少焊墊拓撲差異 TWI622108B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361838457P 2013-06-24 2013-06-24
US61/838,457 2013-06-24

Publications (2)

Publication Number Publication Date
TW201503271A TW201503271A (zh) 2015-01-16
TWI622108B true TWI622108B (zh) 2018-04-21

Family

ID=51022931

Family Applications (2)

Application Number Title Priority Date Filing Date
TW107101209A TW201816905A (zh) 2013-06-24 2014-06-24 藉由平坦化減少焊墊拓撲差異
TW103121674A TWI622108B (zh) 2013-06-24 2014-06-24 藉由平坦化減少焊墊拓撲差異

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW107101209A TW201816905A (zh) 2013-06-24 2014-06-24 藉由平坦化減少焊墊拓撲差異

Country Status (7)

Country Link
US (1) US9935069B2 (zh)
EP (1) EP3014653B1 (zh)
JP (1) JP6762871B2 (zh)
KR (1) KR102257933B1 (zh)
CN (1) CN105308732B (zh)
TW (2) TW201816905A (zh)
WO (1) WO2014207590A2 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3671861A1 (en) * 2018-12-17 2020-06-24 Nexperia B.V. Semiconductor device and electrical contact

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020052065A1 (en) * 2000-10-26 2002-05-02 Ken Ogura Conductor posts, construction for and method of fabricating semiconductor integrated circuit chips using the conductor post, and method of probing semiconductor integrated circuit chips
US20080217183A1 (en) * 2007-03-09 2008-09-11 Sriram Muthukumar Electropolishing metal features on a semiconductor wafer
US20120025242A1 (en) * 2010-07-30 2012-02-02 Apt Electronics Ltd. Surface mounted led structure and packaging method of integrating functional circuits on a silicon

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56142656A (en) * 1980-04-09 1981-11-07 Fujitsu Ltd Semiconductor device
JP3171477B2 (ja) * 1992-02-26 2001-05-28 株式会社東芝 半導体装置
US5465152A (en) * 1994-06-03 1995-11-07 Robotic Vision Systems, Inc. Method for coplanarity inspection of package or substrate warpage for ball grid arrays, column arrays, and similar structures
JPH09312295A (ja) * 1996-03-21 1997-12-02 Matsushita Electric Ind Co Ltd バンプ形成体及びバンプの形成方法
US6042953A (en) * 1996-03-21 2000-03-28 Matsushita Electric Industrial Co., Ltd. Substrate on which bumps are formed and method of forming the same
JPH1013007A (ja) 1996-03-29 1998-01-16 Ngk Spark Plug Co Ltd 半田バンプを有する配線基板及びその製造方法及び平坦化治具
JP3244001B2 (ja) * 1996-07-08 2002-01-07 松下電器産業株式会社 ワークの実装方法
US6652764B1 (en) 2000-08-31 2003-11-25 Micron Technology, Inc. Methods and apparatuses for making and using planarizing pads for mechanical and chemical-mechanical planarization of microelectronic substrates
TWI244129B (en) 2002-10-25 2005-11-21 Via Tech Inc Bonding column process
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
JP4353845B2 (ja) * 2004-03-31 2009-10-28 富士通株式会社 半導体装置の製造方法
JP4140548B2 (ja) * 2004-04-15 2008-08-27 松下電器産業株式会社 バンプ形成装置およびバンプ形成方法
JP2006066689A (ja) * 2004-08-27 2006-03-09 Optrex Corp 半導体素子及びバンプ電極の平坦化方法
TWI317154B (en) * 2006-07-03 2009-11-11 Phoenix Prec Technology Corp Circuit board structure having conductive bumps and method for fabricating conductive bumps on the circuit board structure
US8120188B2 (en) * 2006-11-28 2012-02-21 Panasonic Corporation Electronic component mounting structure and method for manufacturing the same
US7800239B2 (en) * 2007-12-14 2010-09-21 Semiconductor Components Industries, Llc Thick metal interconnect with metal pad caps at selective sites and process for making the same
JP2010003793A (ja) * 2008-06-19 2010-01-07 Fujitsu Ltd 配線基板、ポスト電極の転写用基板及び電子機器
KR101485105B1 (ko) * 2008-07-15 2015-01-23 삼성전자주식회사 반도체 패키지
TWI411075B (zh) * 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8536701B2 (en) * 2011-05-03 2013-09-17 Industrial Technology Research Institute Electronic device packaging structure
CN102931111B (zh) * 2012-11-08 2015-06-10 南通富士通微电子股份有限公司 半导体封装结构的形成方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020052065A1 (en) * 2000-10-26 2002-05-02 Ken Ogura Conductor posts, construction for and method of fabricating semiconductor integrated circuit chips using the conductor post, and method of probing semiconductor integrated circuit chips
US20080217183A1 (en) * 2007-03-09 2008-09-11 Sriram Muthukumar Electropolishing metal features on a semiconductor wafer
US20120025242A1 (en) * 2010-07-30 2012-02-02 Apt Electronics Ltd. Surface mounted led structure and packaging method of integrating functional circuits on a silicon

Also Published As

Publication number Publication date
US20160181216A1 (en) 2016-06-23
TW201503271A (zh) 2015-01-16
WO2014207590A2 (en) 2014-12-31
CN105308732A (zh) 2016-02-03
CN105308732B (zh) 2018-11-27
EP3014653A2 (en) 2016-05-04
KR20160022917A (ko) 2016-03-02
TW201816905A (zh) 2018-05-01
WO2014207590A3 (en) 2015-05-07
EP3014653B1 (en) 2019-09-18
KR102257933B1 (ko) 2021-05-31
JP2016529693A (ja) 2016-09-23
JP6762871B2 (ja) 2020-09-30
US9935069B2 (en) 2018-04-03

Similar Documents

Publication Publication Date Title
US6258625B1 (en) Method of interconnecting electronic components using a plurality of conductive studs
JP5986178B2 (ja) 超小型電子ユニット
TWI496259B (zh) 封裝裝置及其製造方法
US9257379B2 (en) Coreless packaging substrate and method of fabricating the same
US9681546B2 (en) Wiring substrate and semiconductor device
US20130119012A1 (en) Interconnection element for electric circuits
JP2008218926A (ja) 半導体装置及びその製造方法
JP2008251702A (ja) 配線基板の製造方法及び半導体装置の製造方法及び配線基板
JP2004343030A (ja) 配線回路基板とその製造方法とその配線回路基板を備えた回路モジュール
JP2008112995A (ja) 回路基板及びその製造方法
JP6538596B2 (ja) 電子部品の製造方法及び電子部品の製造装置
US10129980B2 (en) Circuit board and electronic component device
JP2014207452A (ja) ガラス貫通ビアを製造する方法
JP5272922B2 (ja) 半導体装置及びその製造方法
US8486760B2 (en) Method of manufacturing substrate for flip chip and substrate for flip chip manufactured using the same
US20180158695A1 (en) Manufacturing method and wiring substrate with through electrode
TWI622108B (zh) 藉由平坦化減少焊墊拓撲差異
KR101109053B1 (ko) 관통 비아홀이 형성된 웨이퍼 및 이에 대한 적층방법
US6960518B1 (en) Buildup substrate pad pre-solder bump manufacturing
KR20140083584A (ko) 실리콘 인터포저의 제조방법
US10090274B2 (en) Flip chip interconnection with reduced current density
KR20140114932A (ko) 복합기판을 이용한 패키지 및 그 제조방법
JP2012079956A (ja) 半導体装置及び半導体装置の製造方法
JP2000232118A (ja) ベアｉｃチップおよび半導体装置製造方法
JP2013141042A (ja) バンプ構造およびその製造方法