CN105206681A - 宽带隙高密度半导体开关器件及其制造方法 - Google Patents
宽带隙高密度半导体开关器件及其制造方法 Download PDFInfo
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Abstract
本发明的各个实施例涉及宽带隙高密度半导体开关器件及其制造方法。开关器件(100),诸如势垒结肖特基(JBS)二极管,具有第一导电类型的碳化硅的本体(101),该本体(101)容纳有第二导电类型的开关区域(102)。开关区域从本体(101)的顶表面延伸并且在开关区域之间划定出本体表面部(104)。具有均匀化学物理特性的接触金属层(11)在本体的顶表面上延伸并且与本体的顶表面直接接触,并且与本体(101)的表面部(104)形成肖特基接触金属部以及与开关区域(102)形成欧姆接触金属部。通过将镍层或者钴层沉积在本体(101)上并且进行热处理从而使得该金属与本体的半导体材料反应从而形成硅化物,来形成接触金属层(110)。
Description
技术领域
本发明涉及一种宽带隙(WBG)高密度半导体开关器件及其制造方法。更加具体地,下文涉及高电压功率WBG二极管。
背景技术
在市场上,最近已经提出了称为JBS(结势垒肖基特)二极管或者MPS(混合PiN肖基特)二极管的开关器件。这些器件总体上在碳化硅(SiC)衬底中制成,并且包括具有与衬底相反的导电性的注入区域(例如,针对N型衬底为P型)。这些器件具有两种不同类型的接触:在注入区域处的欧姆接触、和在包括在注入区域之间的区域中的肖基特接触。
上述特性使JBS二极管尤其适用于在高电压功率器件中工作。
然而,在注入区域处存在欧姆接触可能会使对准出现临界,并且可能会限制欧姆接触面积,这也取决于所使用的曝光设备的对准质量。这限制了结构的封装和更先进二极管的发展。
发明内容
本发明的目的是提供克服现有技术缺陷的器件和制造方法。
根据本发明,如权利要求1和9所限定的,提供了一种宽带隙半导体开关器件及其制造方法。
附图说明
为了更好地理解本发明,现在仅通过非限制性示例,参考对应附图,对本发明的优选实施例进行描述,其中:
图1是包括已知JBS二极管的半导体器件的基本物理结构的截面;
图2A和图2B示出了作为在三个不同开关器件中的正向和反向电压的函数的电流图;
图3A至图3H是在图1的JBS二极管的连续的制造步骤中的半导体材料裸片的截面;
图4是本半导体器件的基本物理结构的截面;
图5A至图5F是根据一个实施例的在图4的器件的连续的制造步骤中的半导体材料裸片的截面;
图6A和图6B示出了在图5A和图5B中表示的制造工艺步骤的变型。
具体实施方式
图1是JBS二极管的结构的示意性图示。此处,总体上是N型的碳化硅的本体1具有第一表面3和第二表面7。衬底1由N+型低电阻率衬底1A和N型外延层1B形成。例如,衬底1A具有包括在40μm与500μm之间的厚度,通常为350μm,和包括在10mΩ·cm与30mΩ·cm之间的电阻率,通常为20mΩ·cm;外延层1B具有包括在3μm与15μm之间的厚度和包括在1015与5·1016之间的掺杂水平(level)。外延层1B容纳有P型注入区域2,该P型注入区域2面朝本体1的第一表面3。金属的欧姆接触区域4在第一表面3上在注入区域2之上延伸。更薄的第一金属层5在外延层1B和欧姆接触区域4之上延伸,并且在注入区域2处形成肖特基接触。比第一金属层5更厚的第二金属层6在第一金属层5之上延伸。
在俯视平面图中,注入区域2可以是纵向延伸并且垂直于绘图平面的条状的,或者具有例如根据规则或者不规则几何图(诸如,正方形、长方形、多边形、圆形等)的边的任何其他形状。
在该结构中,本体1和注入区域2分别形成双极二极管的阴极区域和阳极区域(在图1中整体标示为8),而金属层5和6和本体1分别形成肖特基二极管的阳极区域和阴极区域(在图1中整体标示为9)。金属层5和6进一步将双极二极管8与肖特基二极管9并联连接。
例如在图2A和图2B中,示出了与使用双极和仅仅肖特基技术集成在碳化硅衬底中的类似器件相比较的JBS器件实验特性,图2A和图2B分别表示这些二极管的正向和反向导通(泄漏电流)的特性。
已知的是,JBS器件能够在工作电流(在示例的情况下,6A)下实现与肖特基二极管相同的正向电压降,并且在接近击穿电压下实现比得上双极二极管的泄漏电流的泄漏电流。在JBS结构中存在良好的欧姆接触进一步使JBS器件能够在正向偏置时通过触发双极结而经受高电流;换句话说,,二极管具有高的IFSM(非重复正向浪涌电流最大值),即,在存在正弦形状的脉冲的情况下其可以经受(无故障)的高的最大正向电流。
可以获得图1的JBS二极管,例如,如图3A至图3H所示和下文详细描述的。
首先,图3A,在本体1的第一表面3上制成具有窗口11的硬掩模10。通过使用窗口11,执行P型的注入,由箭头12示意性地表示,例如,进行铝离子的注入。由此形成P型区域13。
接下来(图3B),去除硬掩模10,并且执行注入离子的热活化过程。该过程在大于1500℃的温度下进行,并且导致形成图1的注入区域2。然后,有源面积被限定出来,从而形成场氧化物区域(未示出),该场氧化物区域按照本身已知的方式划定出待形成JBS二极管的面积。
然后(图3C),将薄掩模层15(具有例如近似100nm的厚度)沉积在本体1的第一表面3上,并且将金属层沉积在第二表面7上以在背部形成欧姆接触。然后,执行用于形成背接触(rearcontact)金属层16的热处理。
接下来(图3D),限定出薄掩模层15,以在注入区域2之上形成开口17。
然后,将前接触(frontcontact)金属层18沉积在第一表面3上(图3E)。前接触金属层18是例如镍。然后,执行热处理(在900℃至1000℃的温度下),以便形成从前接触金属层18开始的欧姆接触区域4(图3F)。然后,去除前接触金属层18的尚未与注入区域2的半导体材料发生反应的部分。
接下来(图3G),在进一步限定有源面积(未示出)之后,去除薄掩模层15,并且将例如钛的接触金属层5沉积在第一表面3上。然后,为了优化对该过程的控制并且使该过程可重复,在低温(低于600℃)下进行进一步的热处理,该热处理使金属/半导体界面稳定并且形成肖特基势垒。
最后(图3H),将厚金属层21沉积在接触金属层5上。
这样,肖特基接触(如所述的,由第一金属层5的与外延层1B接触的部分形成)在形成前欧姆接触(欧姆接触区域4)之后制成,并且不经历在高温下的热处理,在高温下的热处理会破坏肖特基接触并且不会实现其可靠的操作。另一方面,随着器件尺寸的减小,越来越难以获得用于在注入区域2(在俯视图中)所在面积之上和之内形成欧姆接触区域4以便保证有效形成接触的对准精度。
图4示出了解决上面所提到的问题的开关器件100的实施例。开关器件100形成JBS二极管,并且总体上形成集成器件的包括其他电子部件(未示出)的一部分。结果,开关器件100总体上形成在有源面积中,该有源面积按照本身已知的方式由厚场氧化物区域划定出来。
开关器件100包括N型的碳化硅的衬底101。衬底101在此处也由衬底101A并且由外延层101B形成。衬底101A和外延层101B可以具有上面针对相应的层1A和1B提到的值的厚度和导电率。本体101具有第一表面(例如,正表面)103和第二表面(例如,背表面)109。布置为彼此相隔一定距离的P型注入区域102从第一表面103开始在外延层101B内延伸。注入区域102可以纵向地、垂直于绘图平面地、条状地延伸,或者可以沿着规则或者不规则几何图(诸如,正方形、长方形、多边形、圆形等)的边延伸。
外延层101B的顶部的表面层104可以相对于外延层104的剩余部分(也称为本体或块体部)富含N+型,如图4中表示的。例如,在外延层101B具有1016at/cm3等级的掺杂水平的情况下,表面层104可以具有高于1.5·1016at/cm3的掺杂水平。表面层104的深度低于注入区域102;例如,表面层104的深度是0.1μm,而注入区域102的深度总体上包括在0.4μm与0.8μm之间,例如近似0.5μm。
更薄的第一金属层110在本体101的第一表面103之上延伸。第一金属层110由过渡金属(此处为镍)的硅化物层形成,第一金属层110在注入区域102之间的外延层101B处形成肖特基接触。第一金属层110可以具有例如包括在200nm与400nm之间的厚度。作为镍的替代方案,第一金属层也可以是钴。更厚的第二金属层112在第一金属层110之上延伸。第二金属层112是例如铝、铝硅、铝硅铜、或者铜,并且具有例如包括在2μm与10μm(通常,近似5μm)之间的厚度。
而且,背接触金属层116在本体101的第二表面109之上延伸。
参考图5A至图5F,如在后文描述的,可以获得图4的开关器件100。
首先(图5A),对具有顶表面105的外延层101B进行表面导电性调整。为此,实现非被掩模的毯覆式表面注入,在图5A中由箭头120表示。例如,在外延层101B具有1016at/cm3的掺杂的情况下,可以引入剂量在1011at/cm2与5·1012at/cm2之间的磷或氮的掺杂原子。由此形成N+型的表面层104。
作为替代方案,可以使用具有可变化的导电性的外延层101B,在这种情况下,根据已知的技术,在外延生长期间,在顶表面105附近获得最大程度地掺杂的面积,并且形成表面层104。
接下来(图5B),在本体101的顶表面105上形成具有窗口122的硬掩模121。通过使用窗口122来执行P型的注入,由箭头123示意性地表示,例如,进行剂量为1015at/cm3的铝原子的注入。由此形成P型的区域125。
然后(图5C),去除硬掩模121并且热活化注入的离子。该过程在高于1500℃的温度下进行,并且导致形成图4的注入区域102。优化过程参数,从而使得注入区域102的深度大于表面层104,如所提及的。然后限定出有源面积,形成场氧化物区域(未示出),该场氧化物区域按照本身已知的方式划定出待制成JBS二极管的面积。
接下来(图5D),由掩模层126覆盖顶表面105,并且将(例如,镍的)背金属层沉积在本体101的第二表面109上,以在背部形成欧姆接触。然后(例如,在包括在900℃与1100℃之间的温度下)执行热处理,由此形成背接触金属层116。
在将掩模层126从本体101的顶表面105去除(图5E)之后,将例如镍的前接触金属层沉积在其上。然后,在550℃与700℃之间的温度下,例如600℃,进行热处理,由此形成第一金属层110,之后,去除前接触金属层的尚未与外延层101B的半导体材料发生反应的部分。第一金属层110由此形成连续层,该连续层具有在所有方向上基本均匀的化学物理特性,除了可能的表面粗糙度的细微差别。而且,其在开关器件100的整个面积中具有基本均匀的高度,在注入区域102与表面层104的在注入区域102之间延伸的部分之间,无任何可检测到的差别。
最后(图5F),将第二金属层111沉积在第一金属层110上。
根据在图6A和图6B中示出的变型,在表面层104的注入之前,进行P型的区域125的注入。为此,初始地(图6A),在外延层101B的顶表面105上形成具有窗口122的硬掩模121。
通过使用窗口122,对P型的区域125进行注入,如由箭头123示意性地表示。
在去除硬掩模121之后(图6B),通过非被掩模的注入对表面面积的导电性进行修改。为此,将N型的掺杂离子注入到外延层101B中,接近其顶表面105(如由箭头120示意性地表示),由此形成N+型的表面层104。然后在高于1500℃的温度下进行活化步骤,限定出有源面积,并且执行已经参考图5C至图5E描述的步骤。
所描述的开关器件100具有多种优点。
具体而言,其具有在JBS二极管处形成欧姆接触和肖特基接触两者的单个层。连续和均质的金属层110在JBS二极管的整个面积之上延伸,在该面积中具有均匀的结构和特性(具体而言,化学物理组成),这一事实意味着,由于所使用的曝光设备的影响,成品器件不受与两个连续层的对准能力有关的限制。这样,开关器件100的结构可以容易地按比例缩放。
而且,由于肖特基接触是通过硅化由金属与半导体材料的本体101的表面发生反应而获得的,所以肖特基接触完全是均匀和稳定的,以有利于器件的最终质量。
借由沉积与本体101接触的单个金属层、并且消除用于限定欧姆接触和肖特基区域的光刻步骤,进一步简化了制作工艺。而且,其使各个步骤的参数设置能够在欧姆部分与肖特基部分的相反的要求之间达成折衷。
事实上,通过在上面所提到的在550℃与700℃之间的温度下,例如近似600℃的温度下,进行镍的硅化热处理,在第一金属层110与本体101之间的接触是欧姆的。通过非被掩模注入120进一步调制外延层101B的表面浓度,可以适当地增加表面电场并且减少肖特基势垒。
这样,可以获得包括在1.2eV与1.4eV之间的肖特基势垒高度,该值与使用钛层可获得的值相似。
从而,开关器件100可以高效率地用于电压等级高于1200V的功率电路中。
最后,显而易见的是,在不背离本发明的如在所附权利要求中限定的范围的情况下,可以对在本文中描述和图示的器件和制造工艺做出修改和改变。
Claims (15)
1.一种开关器件(100),包括:
本体(101),由半导体材料制成,具有表面(103)和第一导电性类型;
开关区域(102),具有第二导电性类型,所述开关区域在所述本体(101)中从所述表面延伸,并且在所述开关区域(102)之间划定出表面部(104);
肖特基接触金属部,在所述表面上,并且与所述表面部(104)直接接触;以及
欧姆接触金属部,在所述表面上,并且与所述开关区域直接接触,
其中所述肖特基接触金属部和所述欧姆接触金属部由具有均匀的化学物理特性的接触金属层(110)形成。
2.根据权利要求1所述的开关器件,其中所述接触金属层(110)是过渡金属的硅化物。
3.根据权利要求1或者2所述的开关器件,其中所述接触金属层(110)由在硅化镍与硅化钴之间选择的硅化物形成。
4.根据上述权利要求中任一项所述的开关器件,其中所述本体(101)由碳化硅制成。
5.根据上述权利要求中任一项所述的开关器件,其中所述本体(101)包括外延层(101B),所述外延层(101B)具有块体部和面朝所述表面(103)的表面部(104),其中所述表面部(104)具有比所述块体部更高的导电率水平、和比所述开关区域(102)更小的深度。
6.根据上述权利要求中任一项所述的开关器件,其中所述第一导电性是N型,并且所述第二导电性是P型。
7.根据上述权利要求中任一项所述的开关器件,其中所述接触金属层(110)具有第一厚度、并且被具有比所述第一厚度更大的第二厚度的金属层(112)覆盖。
8.根据上述权利要求中任一项所述的开关器件,形成结势垒肖特基(JBS)二极管。
9.一种用于制造开关器件的方法,包括:
在由半导体材料制成的、具有表面(105)和第一导电性类型的本体(101)中,形成具有第二导电性类型的开关区域(102),所述开关区域(102)在所述本体中从所述表面(105)延伸、并且在所述开关区域(102)之间划定出所述本体的表面部(104);以及
在所述表面之上,形成具有均匀的化学物理特性的接触金属层(110),所述接触金属层(110)具有与所述本体的所述表面部(104)直接接触的肖特基接触金属部、和与所述开关区域(102)直接接触的欧姆接触金属部。
10.根据权利要求9中所述的方法,其中形成接触金属层包括:沉积过渡金属层(110)并且执行热处理,从而使所述过渡金属与所述本体(101)的所述半导体材料发生反应,以形成硅化物。
11.根据权利要求10所述的方法,其中执行所述热处理并且发生所述反应,是在包括在550℃与700℃之间的温度下进行的,例如在600℃的温度下。
12.根据权利要求9至12中任一项所述的方法,其中所述接触金属层(110)在镍与钴之间选择。
13.根据权利要求9至12中任一项所述的方法,其中所述本体(101)包括在所述表面(105)之下的外延层(101B),所述方法进一步包括:形成面朝所述表面(105)并且覆盖块体部的表面部(104),所述表面部(104)具有比所述块体部更高的导电率水平。
14.根据权利要求13所述的方法,其中设置所述表面部(104)包括:在形成开关区域(102)之前或者之后注入掺杂剂离子物种。
15.根据权利要求9至14中任一项所述的方法,其中所述本体(101)由碳化硅制成。
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CN105206681B (zh) | 2020-12-08 |
US20150372093A1 (en) | 2015-12-24 |
US9711599B2 (en) | 2017-07-18 |
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