CN105122646B - 具有降低的保留电压的触发器 - Google Patents

具有降低的保留电压的触发器 Download PDF

Info

Publication number
CN105122646B
CN105122646B CN201480020737.8A CN201480020737A CN105122646B CN 105122646 B CN105122646 B CN 105122646B CN 201480020737 A CN201480020737 A CN 201480020737A CN 105122646 B CN105122646 B CN 105122646B
Authority
CN
China
Prior art keywords
flop
flip
stage
control signal
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201480020737.8A
Other languages
English (en)
Chinese (zh)
Other versions
CN105122646A (zh
Inventor
S·H·拉苏里
A·达塔
J·M·沙阿
M·圣-劳伦特
P·K·帕卡
S·巴帕特
R·维兰谷蒂皮查
M·H·阿布-拉玛
P·B·帕特尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105122646A publication Critical patent/CN105122646A/zh
Application granted granted Critical
Publication of CN105122646B publication Critical patent/CN105122646B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type
    • H03K3/35625—Bistable circuits of the primary-secondary type using complementary field-effect transistors

Landscapes

  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
CN201480020737.8A 2013-04-12 2014-04-04 具有降低的保留电压的触发器 Expired - Fee Related CN105122646B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/862,015 2013-04-12
US13/862,015 US9673786B2 (en) 2013-04-12 2013-04-12 Flip-flop with reduced retention voltage
PCT/US2014/033051 WO2014168838A2 (en) 2013-04-12 2014-04-04 A flip-flop with reduced retention voltage

Publications (2)

Publication Number Publication Date
CN105122646A CN105122646A (zh) 2015-12-02
CN105122646B true CN105122646B (zh) 2018-09-07

Family

ID=50631117

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480020737.8A Expired - Fee Related CN105122646B (zh) 2013-04-12 2014-04-04 具有降低的保留电压的触发器

Country Status (6)

Country Link
US (1) US9673786B2 (https=)
EP (1) EP2984756A2 (https=)
JP (1) JP2016518785A (https=)
KR (1) KR20150143603A (https=)
CN (1) CN105122646B (https=)
WO (1) WO2014168838A2 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9270257B2 (en) * 2013-08-13 2016-02-23 Texas Instruments Incorporated Dual-port positive level sensitive reset data retention latch
US20150319685A1 (en) * 2014-05-02 2015-11-05 Qualcomm Incorporated Techniques for managing wireless communications using a distributed wireless local area network driver model
KR102280526B1 (ko) * 2014-12-08 2021-07-21 삼성전자주식회사 저전력 작은-면적 고속 마스터-슬레이브 플립-플롭 회로와, 이를 포함하는 장치들
US9641160B2 (en) * 2015-03-02 2017-05-02 Intel Corporation Common N-well state retention flip-flop
KR102216807B1 (ko) * 2015-03-25 2021-02-19 삼성전자주식회사 반도체 회로
WO2017147895A1 (en) * 2016-03-04 2017-09-08 Qualcomm Incorporated Low-area low clock-power flip-flop
US10394471B2 (en) 2016-08-24 2019-08-27 Qualcomm Incorporated Adaptive power regulation methods and systems
US9990984B1 (en) * 2016-12-06 2018-06-05 Qualcomm Incorporated Pulse-stretcher clock generator circuit for high speed memory subsystems
US10262723B2 (en) 2017-05-25 2019-04-16 Samsung Electronics Co., Ltd. System and method for improving scan hold-time violation and low voltage operation in sequential circuit
US11152347B2 (en) 2018-04-13 2021-10-19 Qualcomm Incorporated Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections
JP2022534821A (ja) * 2019-06-04 2022-08-04 リトル ドラゴン アイピー ホールディング エルエルシー 低消費電力フリップフロップ回路
US11171659B1 (en) * 2021-01-05 2021-11-09 Micron Technology, Inc. Techniques for reliable clock speed change and associated circuits and methods
CN120014957B (zh) * 2025-04-14 2025-07-18 江苏帝奥微电子股份有限公司 一种基于ltps cmos的面板栅极驱动电路

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5711526A (en) * 1980-06-25 1982-01-21 Nec Corp Latch circuit
JPS58210715A (ja) * 1982-05-31 1983-12-08 Matsushita Electric Works Ltd フリツプフロツプ回路
JPS6179318A (ja) * 1984-09-27 1986-04-22 Fujitsu Ltd フリツプフロツプ回路
US4656649A (en) * 1984-12-18 1987-04-07 Nec Corporation Clock frequency divider circuit
US4807266A (en) * 1987-09-28 1989-02-21 Compaq Computer Corporation Circuit and method for performing equal duty cycle odd value clock division and clock synchronization
JPH06104701A (ja) * 1992-09-24 1994-04-15 Nec Ic Microcomput Syst Ltd フリップフロップ回路
US6573775B2 (en) * 2001-10-30 2003-06-03 Integrated Device Technology, Inc. Integrated circuit flip-flops that utilize master and slave latched sense amplifiers

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318814A (ja) * 1986-07-11 1988-01-26 Nec Corp フリツプフロツプ回路
US5015875A (en) 1989-12-01 1991-05-14 Motorola, Inc. Toggle-free scan flip-flop
JPH06140885A (ja) * 1992-10-24 1994-05-20 Nec Ic Microcomput Syst Ltd 半導体集積回路
US5719878A (en) * 1995-12-04 1998-02-17 Motorola Inc. Scannable storage cell and method of operation
JP3033719B2 (ja) * 1997-09-10 2000-04-17 日本電気株式会社 低消費電力半導体集積回路
JP2002185309A (ja) * 2000-12-18 2002-06-28 Hitachi Ltd データ保持回路および半導体装置並びに半導体装置の設計方法
US6794914B2 (en) * 2002-05-24 2004-09-21 Qualcomm Incorporated Non-volatile multi-threshold CMOS latch with leakage control
JP4637512B2 (ja) * 2003-11-13 2011-02-23 ルネサスエレクトロニクス株式会社 半導体集積回路装置
KR101045295B1 (ko) * 2004-04-29 2011-06-29 삼성전자주식회사 Ｍｔｃｍｏｓ 플립-플롭, 그를 포함하는 ｍｔｃｍｏｓ회로, 및 그 생성 방법
US7123068B1 (en) * 2005-04-01 2006-10-17 Freescale Semiconductor, Inc. Flip-flop circuit having low power data retention
US7138842B2 (en) * 2005-04-01 2006-11-21 Freescale Semiconductor, Inc. Flip-flop circuit having low power data retention
JP2006339948A (ja) 2005-06-01 2006-12-14 Renesas Technology Corp パルスラッチ回路及び半導体集積回路
US7375567B2 (en) * 2005-06-30 2008-05-20 Texas Instruments Incorporated Digital storage element architecture comprising dual scan clocks and preset functionality
US20070085585A1 (en) * 2005-10-13 2007-04-19 Arm Limited Data retention in operational and sleep modes
US7868677B2 (en) * 2006-12-28 2011-01-11 Stmicroelectronics Pvt. Ltd. Low power flip-flop circuit
US7768331B1 (en) 2007-01-30 2010-08-03 Marvell International Ltd. State-retentive master-slave flip flop to reduce standby leakage current
JP2008219491A (ja) * 2007-03-05 2008-09-18 Nec Electronics Corp マスタスレーブ型フリップフロップ回路およびラッチ回路
US7804669B2 (en) * 2007-04-19 2010-09-28 Qualcomm Incorporated Stacked ESD protection circuit having reduced trigger voltage
US7652513B2 (en) * 2007-08-27 2010-01-26 Texas Instruments Incorporated Slave latch controlled retention flop with lower leakage and higher performance
US7583121B2 (en) * 2007-08-30 2009-09-01 Freescale Semiconductor, Inc. Flip-flop having logic state retention during a power down mode and method therefor
JP5816407B2 (ja) * 2009-02-27 2015-11-18 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US8427214B2 (en) 2010-06-03 2013-04-23 Arm Limited Clock state independent retention master-slave flip-flop
WO2012157472A1 (en) * 2011-05-13 2012-11-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5711526A (en) * 1980-06-25 1982-01-21 Nec Corp Latch circuit
JPS58210715A (ja) * 1982-05-31 1983-12-08 Matsushita Electric Works Ltd フリツプフロツプ回路
JPS6179318A (ja) * 1984-09-27 1986-04-22 Fujitsu Ltd フリツプフロツプ回路
US4656649A (en) * 1984-12-18 1987-04-07 Nec Corporation Clock frequency divider circuit
US4807266A (en) * 1987-09-28 1989-02-21 Compaq Computer Corporation Circuit and method for performing equal duty cycle odd value clock division and clock synchronization
JPH06104701A (ja) * 1992-09-24 1994-04-15 Nec Ic Microcomput Syst Ltd フリップフロップ回路
US6573775B2 (en) * 2001-10-30 2003-06-03 Integrated Device Technology, Inc. Integrated circuit flip-flops that utilize master and slave latched sense amplifiers

Also Published As

Publication number Publication date
US9673786B2 (en) 2017-06-06
WO2014168838A3 (en) 2014-12-11
CN105122646A (zh) 2015-12-02
EP2984756A2 (en) 2016-02-17
JP2016518785A (ja) 2016-06-23
US20140306735A1 (en) 2014-10-16
WO2014168838A2 (en) 2014-10-16
KR20150143603A (ko) 2015-12-23

Similar Documents

Publication Publication Date Title
CN105122646B (zh) 具有降低的保留电压的触发器
US9336864B2 (en) Silicon germanium read port for a static random access memory register file
KR101651886B1 (ko) 레벨 시프터를 포함하는 감지 증폭기
US8406064B2 (en) Latching circuit
US9473113B1 (en) Power management with flip-flops
US9722585B2 (en) Circuit and method to extend a signal comparison voltage range
JP2016527654A5 (https=)
US8928354B2 (en) Clock-delayed domino logic circuit and devices including the same
US20170288673A1 (en) Power efficient voltage level translator circuit
KR101773307B1 (ko) 쿼드러처 분할기
CN109074833B (zh) 用于加快存储器访问的输出锁存器
US10133285B2 (en) Voltage droop control
CN105027438B (zh) 低泄漏保留寄存器盘
CN111355482A (zh) 低功率低建立时间的集成时钟门控单元
US7557630B2 (en) Sense amplifier-based flip-flop for reducing output delay time and method thereof
US9276575B2 (en) Low leakage state retention synchronizer
US20170077908A1 (en) High speed domino-based flip flop
US20070024322A1 (en) Leakage current reduction scheme for domino circuits

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180907

Termination date: 20200404