CN1050692C - 一种在快速eeprom单元中形成结的方法 - Google Patents

一种在快速eeprom单元中形成结的方法 Download PDF

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CN1050692C
CN1050692C CN96110354A CN96110354A CN1050692C CN 1050692 C CN1050692 C CN 1050692C CN 96110354 A CN96110354 A CN 96110354A CN 96110354 A CN96110354 A CN 96110354A CN 1050692 C CN1050692 C CN 1050692C
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impurity range
ddd
forms
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foreign ion
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CN1146628A (zh
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李熙烈
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

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Abstract

本发明涉及一改进DDD结结构,其特征在于:通过高能量的杂质离子的倾斜注入工艺,形成第一杂质区,然后,通过低能量的杂质离子的倾斜注入工艺,形成第二杂质区,由此,在层叠浮栅和控制栅的层叠栅结构上形成DDD结结构,在劈栅一侧上形成非DDD结结构。

Description

一种在快速EEPROM单元中形成结的方法
本发明涉及一种在快速EEPROM单元中形成结的方法,尤其涉及一种在具有亚微米沟道长度的劈栅型快速EEPROM单元中形成DDD(双扩散漏)结的方法。
下面参照附图1A至1C说明一种形成DDD结的方法。
图1A至1C是用来解释在常规快速EEPROM单元中形成结的方法的器件剖面图。
图1A是器件的剖面图,其中,在硅衬底1上形成隧道氧化膜2后以层叠结构依次形成浮栅3、介质膜4、控制栅5和氧化膜6,和用源/漏杂质离子注入掩模,通过平板印刷术工艺形成第一光致抗蚀剂图形7。然后,通过源/漏杂质离子注入工艺形成第一杂质区8A。
图1B是器件的剖面图,其中,在去除光致抗蚀剂图形7后,通过退火工艺,第一杂质区8A变大。
图1C是器件的剖面图,其中,用源/漏杂质离子注入掩模,通过平板印刷术工艺,形成与第一光致抗蚀剂图形7相同的第二光致抗蚀剂图形9,此后,通过源/漏杂质离子注入工艺形成完全限制在第一杂质区8A内的第二杂质区8B。结果,形成由第一和第二杂质区8A,8B构成的DDD结构的结8。
上述方法的问题是必须用两步连续的掩模工艺。另外,在退火工艺中还存在困难。再者,当DDD结构的结用作单元的漏时,在操作单元没有问题,然而该结用作单元的源时,除发生穿通外,单元的阈值电压下降。
本发明的目的是提供一种通过形成不用源/漏杂质离子注入掩模和退火工艺的改进DDD结构的结来在快速EEPROM单元中形成结的方法,该方法能减少制造工艺步骤并能在单元中保持劈栅沟道长度。
一种根据本发明实现上述目的的在快速EEPROM单元中形成结的方法包括以下步骤:在硅衬底上形成隧道氧化膜;形成层叠栅结构,即在该膜上依次形成浮栅、介质膜、控制栅和氧化膜;在包括层叠栅结构的生成物结构上形成薄氮化物膜;通过能量大于100KeV的杂质离子倾斜注入工艺,在硅衬底中形成第一杂质区;在层叠栅结构的侧壁上形成垫氧化膜;和通过能量小于100KeV的杂质离子倾斜注入工艺,形成限制在第一杂质区内的第二杂质区,及由此形成改进DDD结结构。该DDD结构形成于浮栅和控制栅层叠于其上的层叠栅结构侧上,非DDD结构形成于劈栅一侧上,其中劈栅的长度是根据层叠栅结构的高度和杂质离子注入的倾斜入射来决定的。
为了充分理解本发明的性质和目的,必须参考下面参照附图所作的详细说明。
图1A至1C是解释在常规快速EEPROM单元中形成结的方法的剖面图。
图2A至2C是解释根据本发明在快速EEPRROM单元中形成结的方法的剖视图。
在各附图中相同的附图标记代表相同的部件。
下面参照附图详细说明本发明。
图2A至2C是解释根据本发明在快速EEPRROM单元中形成结的方法的剖面图。
图2A是器件的剖面图,在该器件中,在硅衬底11上形成沟道氧化膜12,在其上依次层叠浮栅13、介质膜14、控制栅15和氧化膜16而形成层叠栅结构。然后,在包括硅衬底11在内的层叠栅结构生成物上形成薄氮化物膜21。
图2B是器件的剖面图,在该器件中,不用源/漏杂质离子注入的掩模,将能量为100-160KeV的杂质离子倾斜注入,在硅衬底内形成第一杂质区18A。
在图2A和2B中,氧化物膜21可以在杂质离子的倾斜注入工艺之前或之后形成。
图2C是器件的剖面图,在该器件中,在层叠栅结构的侧壁上形成垫氧化膜22后,通过能量为40至100KeV的杂质离子倾斜注入,在硅衬底内形成限制在第一杂质区18A内的第二杂质区18B。结果,形成由第一和第二杂质区18A,18B构成的改进结18。
此后,通过除去垫氧化膜22和氮化膜21并在层叠栅结构和结区上形成劈栅而制造劈栅型快速EEPROM单元。
按照本发明的如图2C所示的改进DDD结18的结构不同于如图1C所示的常规DDD结8的结构。为层叠栅结构所覆盖的改进结18的那部分与DDD结构一同形成,而不为层叠栅结构所覆盖的改进结18的另一部分与非DDD结构一同形成。因此,当将本发明的改进结18用作单元的漏时,与常规结8相比单元的特性能得到改进。当将本发明的改进结18用作劈栅的源时,由于该结的那部分不是DDD结构因此该结能防止沟道长度变短、阈值电压减小和发生穿通。
如上所述,通过倾斜杂质离子注入工艺形成第一和第二杂质区。但第一杂质区是用高能量形成的,而第二杂质区是用低能量形成的。
因此,本发明能省去形成具有第一和第二杂质区的DDD结构的掩模工艺和扩散第一杂质区的退火工艺,还能改进劈栅的特性和减小单元尺寸。
尽管上述描述在一定程度上说明了本发明的优选实施例,但它只是对本发明原理的说明。应该明白,本发明并不限于这里所公开和描述的优选实施例。因此,在不脱离本发明的精神和实质的情况下,所有的变型皆包含在本发明的进一步实施例中。

Claims (3)

1.一种在快速EEPROM单元中形成结的方法,其特征在于包括以下步骤:
在硅衬底上形成隧道氧化膜;
依次形成浮栅、介质膜、控制栅和氧化膜以形成层叠栅结构;
在包括所说层叠栅结构的生成物结构上形成薄氮化膜;
通过杂质离子的倾斜注入工艺,在所说硅衬底内形成第一杂质区;
在所说层叠栅结构的侧壁上形成垫氧化膜;
通过杂质离子的倾斜注入工艺,形成包括在所说第一杂质区内的第二杂质区,因而在所说硅衬底内形成结区;以及
在所述层叠栅结构和所述结区上形成劈栅。
2.根据权利要求1的方法,其特征在于:为所说层叠栅结构所覆盖的所说结区的那部分形成在DDD结构内,而不为所说层叠栅结构所覆盖的所说结区的另一部分与非DDD结构一同形成。
3.根据权利要求1的方法,其特征在于:形成所说第一杂质区的所说杂质离子的倾斜注入其能量为100-160KeV,形成第二杂质区的所说杂质离子的倾斜注入其能量为40-100KeV。
CN96110354A 1995-06-02 1996-06-01 一种在快速eeprom单元中形成结的方法 Expired - Fee Related CN1050692C (zh)

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JP (1) JP2907774B2 (zh)
KR (1) KR0172275B1 (zh)
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DE (1) DE19621753B4 (zh)
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JP2907774B2 (ja) 1999-06-21
US5770502A (en) 1998-06-23
TW299501B (zh) 1997-03-01
JPH08330457A (ja) 1996-12-13
DE19621753A1 (de) 1996-12-05
GB2301709B (en) 1999-04-21
KR970004028A (ko) 1997-01-29
DE19621753B4 (de) 2006-01-05
GB9611181D0 (en) 1996-07-31
KR0172275B1 (ko) 1999-02-01
CN1146628A (zh) 1997-04-02

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