CN105051822B - 倒置正交自旋转移叠层 - Google Patents

倒置正交自旋转移叠层 Download PDF

Info

Publication number
CN105051822B
CN105051822B CN201380053738.8A CN201380053738A CN105051822B CN 105051822 B CN105051822 B CN 105051822B CN 201380053738 A CN201380053738 A CN 201380053738A CN 105051822 B CN105051822 B CN 105051822B
Authority
CN
China
Prior art keywords
magnetic
layer
pinned
magnetization vector
free
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201380053738.8A
Other languages
English (en)
Other versions
CN105051822A (zh
Inventor
A·肯特
D·贝克斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New York University NYU
Original Assignee
New York University NYU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New York University NYU filed Critical New York University NYU
Publication of CN105051822A publication Critical patent/CN105051822A/zh
Application granted granted Critical
Publication of CN105051822B publication Critical patent/CN105051822B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N15/00—Thermoelectric devices without a junction of dissimilar materials; Thermomagnetic devices, e.g. using the Nernst-Ettingshausen effect
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F10/00—Thin magnetic films, e.g. of one-domain structure
    • H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
    • H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
    • H01F10/3286—Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/14—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates
    • H01F41/30—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE]
    • H01F41/302—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE] for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices
    • H01F41/305—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE] for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices applying the spacer or adjusting its interface, e.g. in order to enable particular effect different from exchange coupling
    • H01F41/307—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying magnetic films to substrates for applying nanostructures, e.g. by molecular beam epitaxy [MBE] for applying spin-exchange-coupled multilayers, e.g. nanostructured superlattices applying the spacer or adjusting its interface, e.g. in order to enable particular effect different from exchange coupling insulating or semiconductive spacer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F10/00—Thin magnetic films, e.g. of one-domain structure
    • H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
    • H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
    • H01F10/3268—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
    • H01F10/3272—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets

Abstract

一种磁性器件包括钉扎磁性层，钉扎磁性层具有第一固定磁化向量，所述第一固定磁化向量具有第一固定磁化方向。磁性器件还包括自由磁性层，具有可变磁化向量，所述可变磁化向量至少具有第一稳态和第二稳态。磁性器件还具有第一非磁性层和参考磁性层。第一非磁性层在空间上分离钉扎磁性层与自由磁性层。磁性器件还包括第二非磁性层，所述第二非磁性层在空间上分离自由磁性层与参考磁性层。位于钉扎磁性层下的磁隧穿结由自由磁性层、第二非磁性层和参考磁性层形成。穿过磁性器件施加具有正或负极性与选定的振幅和持续时间的电流脉冲切换可变磁化向量。

Description

倒置正交自旋转移叠层
相关申请的交叉参考
本申请要求于2012年10月17日提交的美国临时专利申请No.61/715,111的优先权，其通过参考全文并入本文中。
背景技术
正交自旋转移磁随机存取器件(OST-MRAMTM)包含极化器(polarizer)。在美国专利No.6,980,469中论述了器件和叠层，其整体通过参考并入本文。叠层的磁隧穿结内和附近的粗糙度影响OSTTM器件的性能。增大的粗糙度可能对于磁隧穿结的击穿有负面影响。在堆叠顶上具有极化器的OSTTM叠层可以减小磁隧穿结的粗糙度，增大器件磁阻(magnetoresistance)，并改进OSTTM存储器件的性能。
发明内容
总体上，本说明书中所述的主题的一个方面体现为一种磁性器件，该磁性器件包括钉扎磁性层，钉扎磁性层具有第一固定磁化向量，所述第一固定磁化向量具有第一固定磁化方向。磁性器件还包括自由磁性层，自由磁性层具有可变磁化向量，所述可变磁化向量至少具有第一稳态和第二稳态。磁性器件还具有第一非磁性层和参考磁性层。第一非磁性层在空间上分离钉扎磁性层与自由磁性层。参考磁性层具有第二固定磁化向量，第二固定磁化向量具有第二固定磁化方向。磁性器件还包括第二非磁性层，所述第二非磁性层在空间上分离自由磁性层与参考磁性层。由自由磁性层、第二非磁性层和参考磁性层形成磁隧穿结。穿过磁性器件施加具有正或负极性与选定的振幅和持续时间的电流脉冲切换可变磁化向量。磁隧穿结在空间上位于钉扎磁性层下。下文中更详细地描述了存储器件与存储系统的其他实施方式。
前述发明内容仅是说明性的，绝非旨在是限制性的。除了上述说明性方面、实施方式和特征以外，通过参考以下附图和具体实施方式，其他方面、实施方式和特征将会变得更加清楚。
附图说明
依据以下说明和所附权利要求书并结合附图，本公开内容的前述及其他特征会变得更加清楚。应理解这些附图仅示出了根据本公开内容的几个实施方式，因此不应认为是限制其范围，通过使用附图，将借助额外的特征和细节来描述本公开内容。
图1是磁性器件的图示。
图2是根据说明性实施方式的具有倒置叠层的磁性器件的图示。
图3是根据说明性实施方式的在堆叠顶部具有极化器(FM1)的倒置叠层的图示。
图4是根据说明性实施方式的具有合成反铁磁体(antiferromagnet)极化器的倒置叠层的图示。
图5是根据说明性实施方式的具有钉扎(pinned)合成反铁磁体极化器的倒置叠层的图示。
图6A和6C是非倒置叠层的透射电子显微镜截面。
图6B和6D是根据说明性实施方式的倒置叠层的透射电子显微镜截面。
图7是根据说明性实施方式的在顶上没有极化器的倒置磁隧穿结的图示。
图8是根据说明性实施方式的倒置叠层的图示。
图9是根据说明性实施方式的用于倒置叠层中的fcc非磁性层的图示。
图10是根据说明性实施方式的用于倒置叠层中的bcc非磁性层的图示。
图11是根据说明性实施方式的用于倒置叠层中的fcc和bcc非磁性层的图示。
图12是根据说明性实施方式的两个叠层的磁阻的平面隧穿效应测量中的电流的曲线图。
图中所示的全部数值厚度为纳米(nm)。在以下具体实施方式中参考了附图。在附图中，相似的符号通常标识相似的组件，除非上下文另有规定。具体实施方式、附图和权利要求书中所述的说明性实施方式并非意图是限制性的。在不脱离本文提出的主题的精神或范围的情况下，可以使用其他实施方式，可以做出其他变化。容易理解，本文总体说明的且在附图中示出的本公开内容的方面可以以各种不同结构来布置、替代、组合和设计，它们全都是可以明确地预料到的，并且是本公开内容的部分。
具体实施方式
基本磁性器件的结构
图1显示了现有技术的多层的、柱状磁性器件，该磁性器件包括具有固定磁化方向的钉扎磁性层FM1和具有自由磁化方向的自由磁性层FM2。m1是钉扎磁性层FM1的磁化向量，m2是自由磁性层FM2的磁化向量。钉扎磁性层FM1充当自旋角动量的源。
钉扎磁性层FM1和自由磁性层FM2由第一非磁性层N1分隔，第一非磁性层N1在空间上分隔两个层FM1和FM2。N1可以是非磁性金属(Cu、CuN、Cr、Ag、Au、Al、Ru、Ta、TaN等)，或者是薄非磁性绝缘体，例如Al2O3或MgO。当N1是非磁性金属时，其厚度必须小于或近似等于材料在处于器件温度处的自旋扩散长度。这允许当电子在横穿(traverse)N1时，电子自旋极化被基本保持。在使用Cu的一个实施方式中，对于在室温或室温附近工作的器件，层的厚度小于或近似等于0.5到50nm。当N1是绝缘层时，其厚度必须使得电子能够借助量子力学隧穿效应横穿该层，并在该过程中大体保持其自旋极化的方向。在N1是MgO或Al2O3的实施方式中，层厚度应近似等于0.3到4nm。非磁性层N1的厚度应使得在大致小于层厚度的短长度级别上电子自旋方向无散射。柱状磁性器件的尺寸通常在纳米级别，例如，它在横向上可以小于约200nm。
自由磁性层FM2实质上是磁性薄膜元件，与另外的两个层-钉扎磁性层FM1和非磁性层N1一起嵌入到柱状磁性器件中。层厚度通常约为0.7nm到10nm。
这些柱状磁性器件可以借助许多不同方式(包括通过亚微米镂空掩模的物理气相沉积(溅射法)、热和电子束蒸发)按照层的堆叠顺序来制造。也可以如下来制造这些磁性器件：按照堆叠顺序使用溅射、热和电子束蒸发来形成多层膜，之后使用消减纳米制造(subtractive nanofabrication)工艺，消减纳米制造工艺去除材料以在衬底(例如其它半导体或者绝缘晶片的硅的衬底)表面上留下柱状磁性器件。半导体晶片可以已经包括CMOS电路的部分，用于读写磁性器件。在叠层包含磁隧穿结时，可以使用退火。退火可以使得MgO绝缘阻挡层晶化，并增强结的磁阻。在不同实施方式中，使用单一的退火过程。在一个实施方式中，在300℃到450℃的温度对叠层退火，以热晶化MgO层。退火的持续时间是几分钟(快速热退火)到几小时，较高退火温度需要的退火时间较短。退火常常在1特斯拉或更大的磁场中进行，以设定参考层(FM3)的磁化状态。退火提供了自由层(FM2)的磁各向异性的优选方向和增强的单轴磁各向异性。
用于铁磁体层的材料包括(但不限于)：Fe、Co、Ni；这些元素的合金，例如Ni1-xFex和CoFe；这些铁磁体金属与例如B、Cu、V、Pd和Pt的非磁性金属的合金，其组成使得材料在室温下是铁磁性排序的；导电材料；导磁氧化物，例如CrO2和Fe3O4；和完全自旋极化材料，例如赫斯勒合佥NiMnSb。对于非磁性层，材料包括(但不限于)Cu、CuN、Cr、Ag、Au、Al、Ru、Ta和TaN。
电流源连接到钉扎磁性层FM1和自由磁性层FM2，以使得电流I可以横穿柱状器件。在另一个实施方式中，对包含叠层的柱的顶部和底部形成电接触。
图2是根据本发明的说明性实施方式的倒置叠层200的图示。在该实施方式中，倒置叠层200包含钉扎层FM1。钉扎层FM1可以被垂直于层的平面来磁化，在图2中由m1表示该磁化。钉扎层FM1可以相对于自由磁性层FM2倒置。换句话说，在自由磁性层FM2和参考层FM3之后形成钉扎层FM1。非磁性层N1分隔钉扎层FM1与自由磁性层FM2。自由磁性层FM2可以与作为磁隧穿结的绝缘体的另一个非磁性层N2和参考层FM3形成磁隧穿结。N1也可以是绝缘层，以使得FM1和FM2形成第二磁隧穿结。参考层FM3可以用于读取器件的状态。参考层FM3与自由磁性层FM2通过非磁性层N2分隔。如上详细说明地，各种材料可以用于制成倒置叠层200的各个层。另外，层可以具有各种不同厚度。
图3是根据说明性实施方式的倒置叠层300的图示。各层的厚度在纳米级(nm)。另外，显示了与图2中的层相关的FM1、FM2、FM3、N1和N2层。在倒置叠层300中，磁隧穿结层302在底部，垂直极化器304在顶部。在一些实施方式中，极化器被沉积在磁隧穿结的顶上，磁隧穿结由FM2、N2和FM3层构成。在倒置叠层300中，磁隧穿结层302更接近于衬底或半导体器件(CMOS)晶片。与例如图1的在底部具有极化器的非倒置叠层的磁隧穿结层相比，磁隧穿结层302也更光滑。磁隧穿结层302的光滑度的增大，即粗糙度的减小，减小了磁隧穿结层302和周围层内的尖角。具体而言，与非倒置叠层的第二非磁性层相比，第二非磁性层N2(308)的光滑度增大。绝缘层内的粗糙度影响何时及在何种情况下磁隧穿击穿。倒置叠层300具有更光滑的非磁性层308，其与使用非倒置叠层的正交自旋转移MRAM器件相比，该更光滑的非磁性层308通过增大击穿电压并改进磁开关特性而改进了正交自旋转移MRAM器件的性能。倒置叠层300还可以减小横跨晶片的器件特性中的变化。Cu(N)层是可选的层，在多个实施方式中不存在这个层。Cu(N)层形成了到器件的电接触。这个触点可以是衬底的一部分，例如CMOS驱动器。Cu(N)层也可以由不同材料制成，例如但不限于Al、Ta、Cu。
图6A-6D示出了倒置叠层与非倒置叠层的磁隧穿结层的光滑度之间的区别。图6A和6C是非倒置叠层的透射电子显微镜截面。在图6A和6C中可以以两个不同比例来观看第二非磁性层MgO 602。图6B和6D是根据说明性实施方式的倒置叠层的透射电子显微镜截面。在图6B和6D中可以以两个不同比例来观看第二非磁性层MgO 604。将图6A和6C与图6B和6D相比可以见到，第二非磁性层604比第二非磁性层602更光滑。可以将MgO层的粗糙度的幅度从非倒置叠层中的2.9+/-2.7纳米(nm)减小到倒置叠层中的0.8+/-0.3nm。在此，将幅度定义为最小值与最大值之间的垂直距离。MgO层的粗糙度的波长也从非倒置叠层的33.1+/-11.0nm减小到倒置叠层中的23.2+/-14.6nm。在此，将波长定义为分别在最小值与最大值和最大值与最小值之间的水平距离的两倍。粗糙度减小产性较高的器件击穿电压，其导致在写电压与击穿电压之间较大的间隔。这导致操作过程中器件故障较少的更高的器件性能。
可以借助附加层来性产其他倒置叠层。图4是根据说明性实施方式的具有合成反铁磁体极化器404的倒置叠层400的图示。倒置叠层400类似于图3中所示的倒置叠层300。区别在于垂直极化器304被并入到合成反铁磁体404中。薄反铁磁耦合层402在合成反铁磁体中建立两个铁磁性层304与405的反平行磁取向。这建立了包括垂直极化器304的合成反铁磁体极化器404。在所示示例中，反铁磁耦合层包含钌。在这个示例中，钌是合成反铁磁体中的材料之一，且是在含Ni/Co与含Pd/Co的层之间建立反铁磁耦合的层。在其他实施方式中，可以使用其他合成反铁磁材料，例如但不限于，铬、铜等。Cu(N)层是可选的层，且在多个实施方式中不存在这个层。
合成反铁磁磁体极化器404减小了在倒置叠层400的垂直极化器与自由磁性层FM2之间的磁相互作用。磁相互作用的降低提高了器件性能，例如但不限于，在切换过程中(例如写数据)自由层的更均匀的磁化旋转；减小了不希望有的热引起的切换事件的可能性(例如擦除或破坏存储数据的波动)。
图5是根据说明性实施方式的具有钉扎合成反铁磁体极化器404的倒置叠层500的图示。倒置叠层500类似于图4中所示的倒置叠层400，但增加了为反铁磁体的铱锰层502。在其他实施方式中，使用了其他的反铁磁体。反铁磁体502的添加钉扎住了(pin)合成反铁磁体极化器404，给予垂直交换偏置。这使得垂直极化器304在器件使用过程中，针对不希望出现的退磁，更为硬磁性且更稳定。这可以导致较长的器件寿命以及更多的可重复性器件操作。Cu(N)层是可选层，且在多个实施方式中不存在这个层。
除了使垂直极化器倒置以外，改变N1层内的材料可以影响倒置叠层的特性。图7是根据说明性实施方式的在顶上没有极化器的倒置磁隧穿结700的图示。Cu(N)层是可选的层，且在多个实施方式中不存在这个层。倒置磁隧穿结700包含磁隧穿结层302，但没有垂直极化器。在实验中，使用平面隧穿效应技术(CIPT)中的电流来测量隧穿磁阻(TMR)。取决于MgO层的厚度，在与CoFeB自由层的分界面处，具有铜的叠层呈现出55％到69％的TMR。在另一个实验中，去除了铜层。TMR显著增大到157％。下表1总结了这些发现。MgO层的厚度没有被优化，可以借助优化的MgO层来实现进一步的增大，但这些优化不是用于本发明的操作的材料。
具有Cu覆盖层 无Cu覆盖层
TMR％ 55-69％ 157％
RA Ohm μm2 2.5-14.4 6.18
表1
尽管不限于以下原因，但铜可以在与之共享分界面的CoFeB层中引入其面心立方(fcc)晶体结构。对于最佳TMR，CoFeB的(体心立方)bcc结构是有利的。铜层可以使极化器和磁隧穿结磁去耦。在这些实施方式中，在铜夹层与CoFeB自由层之间的Cu/CoFeB分界面是电气性能降低(例如较小的TMR)的原因。使用bcc结构，而不是诸如铜的fcc结构，可以增大堆叠的TMR。另外，使用比CoFeB在更高的温度处晶化的材料有利于bcc结构的CoFeB的形成，并可以增大TMR。
在一个实施方式中，铜层由bce非磁性层代替。图8是根据说明性实施方式的倒置叠层800的图示。倒置叠层800类似于图3的倒置叠层300，包含非磁性层N1。这个N1层的材料可以是多种材料。Cu(N)层是可选的层，且在多个实施方式中不存在这个层。图9示出了N1层包括铜的一个示例。在这个示例中，倒置叠层800与图3的倒置叠层300相同。但非磁性层N1可以由其他材料制成。如上所述，用bcc非磁性物质代替铜(fcc金属)，可以增大倒置叠层800的TMR。图10示出了这个示例。在图10中，非磁性层N1包括bcc非磁性材料1002。bcc非磁性材料1002与自由磁性层FM2接合(interface)。另外，bcc非磁性材料1002可以支持例如CoFeB层的下面的bcc自由磁性层FM2的生长。bcc非磁性层具有长自旋扩散长度，使得电流在通过极化器后保持大的垂直自旋极化。下表2总结了可以用作bcc非磁性材料1002的一些材料。在与这些材料的任意材料一起使用时，N1层的厚度可以小于或约等于用作bcc非磁性材料1002的材料的自旋扩散长度。
材料 原子序数 晶体结构 磁序 自旋扩散长度/nm
V 23 Bcc 顺磁性 ＞40
Cr 24 Bcc 自旋密度波反铁磁体 在4K为4.5
Nb 41 Bcc 顺磁性 ～25或5.9±0.3
Mo 42 Bcc 顺磁性 8.6±1.3
Ta 73 Bcc 顺磁性 2.7±0.4
表2
在另一个实施方式中，非磁性层N1可以由fcc和bcc材料组成。图11是根据说明性实施方式的具有fcc非磁性层1004和bcc非磁性层1002的倒置叠层的图示。在这个实施方式中，bcc非磁性层1002与例如CoFeB的自由磁性层FM1相邻；fcc非磁性层1004与极化器相邻。这确保了在夹层/极化器分界面的层具有相同的fcc晶体结构，还确保了在夹层/自由层分界面的层具有相同的bcc晶体结构。在这个实施方式中可以使用不同fcc和bcc材料。表3总结了可以使用的材料的一些非限制性组合。
表3
图12是根据说明性实施方式的两个叠层的磁阻的平面隧穿效应测量中的电流的曲线图1200。曲线图1200示出了不具有Ta夹层的倒置叠层的磁阻1202。在图8和9中显示了这个倒置叠层。还显示了包括Ta夹层和铜fcc非磁性层的倒置叠层的磁阻1204。图11示出了示例性bcc非磁性夹层。在测试中，改变MgO厚度以产生具有不同的、系统地变化的电阻和面积(RA)的乘积的叠层。这在曲线图1200的X轴中显示了。对于所研究叠层的所有电阻和面积乘积，针对包括bcc非磁性夹层的倒置叠层来说，磁阻被增大了。
尽管本说明书包含许多特定实施方式细节，但这些不应解释为对任何发明或者可以要求的范围的限制，而应当解释为针对特定发明的特定实施方式的特征的说明。在单独的实施方式环境下在本说明书中所述的某些特征也可以组合到单一实施方式中来实施。相反，在单一实施方式环境下所述的不同特征也可以分别在多个实施方式中或者任何适合的子组合中实施。此外，尽管以上将特征说明为在某些组合中操作，甚至最初按此提出权项，但在一些情况下，来自要求保护的组合的一个或多个特征能够脱离该组合，要求保护的组合可以涉及子组合或者子组合的变型。
类似地，尽管在附图中按照特定顺序示出了操作，但这不应理解为要求以所示的特定顺序或者顺序性地执行这些操作，或者要求执行全部所示的操作以实现期望的结果。在某些情况下，多任务和并行处理是有利的。此外，上述实施方式中不同系统组件的分离不应理解为在所有实施方式中都要求这种分离，应理解，所述的程序组件和系统通常可以集成到单一软件产品中或者封装到多个软件产品中。
因而，描述了本发明的特定实施方式。其他实施方式也在所附权利要求书的范围内。本领域技术人员在阅读了本公开内容后会理解，在一些情况下，在权利要求中表述的操作可以以不同顺序执行，仍可以实现期望的结果。另外，为了实现期望的结果，在附图中所示的过程不一定要求所示的特定顺序，或者是顺序性排序的。在某些实施方式中，多任务和并行处理是有利的。

Claims (20)

1.一种磁性器件，包括：
钉扎磁性层，所述钉扎磁性层具有第一固定磁化向量，所述第一固定磁化向量具有第一固定磁化方向；
自由磁性层，所述自由磁性层具有可变磁化向量，所述可变磁化向量至少具有第一稳态和第二稳态；
第一非磁性层，所述第一非磁性层在空间上分离所述钉扎磁性层与所述自由磁性层；
参考磁性层，所述参考磁性层具有第二固定磁化向量，所述第二固定磁化向量具有第二固定磁化方向；及
第二非磁性层，所述第二非磁性层在空间上分离所述自由磁性层与所述参考磁性层，
其中，由所述自由磁性层、所述第二非磁性层和所述参考磁性层形成磁隧穿结，其中穿过所述磁性器件施加具有选定的振幅和持续时间的电流脉冲切换所述可变磁化向量，且其中所述磁隧穿结在空间上位于所述钉扎磁性层下。
2.根据权利要求1所述的磁性器件，其中，所述第一固定磁化向量与所述钉扎磁性层的平面垂直。
3.根据权利要求1所述的磁性器件，进一步包括包含所述钉扎磁性层的合成反铁磁体层。
4.根据权利要求3所述的磁性器件，其中，所述合成反铁磁体层减小了在所述钉扎磁性层与所述自由磁性层之间的磁相互作用。
5.根据权利要求3所述的磁性器件，其中，所述合成反铁磁体层是选自于包括钌、铬或铜的组的材料。
6.根据权利要求3所述的磁性器件，进一步包括反铁磁体，所述反铁磁体钉扎住所述合成反铁磁体层，提供垂直交换偏置。
7.根据权利要求6所述的磁性器件，其中，所述反铁磁体由铱锰组成。
8.根据权利要求1所述的磁性器件，其中，第二非磁性绝缘层具有小于或等于0.8纳米的粗糙度的幅度。
9.根据权利要求1所述的磁性器件，其中，第二非磁性绝缘层具有小于或等于23.2纳米的粗糙度的波长。
10.根据权利要求1所述的磁性器件，进一步包括第二磁隧穿结，所述第二磁隧穿结包括所述钉扎磁性层和所述自由磁性层。
11.根据权利要求1所述的磁性器件，其中，所述可变磁化向量表示信息的位。
12.一种存储系统，包括：
存储器单元，包括：
钉扎磁性层，所述钉扎磁性层具有第一固定磁化向量，所述第一固定磁化向量具有第一固定磁化方向；
自由磁性层，所述自由磁性层具有可变磁化向量，所述可变磁化向量至少具有第一稳态和第二稳态；
第一非磁性层，所述第一非磁性层在空间上分离所述钉扎磁性层与所述自由磁性层；
参考磁性层，所述参考磁性层具有第二固定磁化向量，所述第二固定磁化向量具有第二固定磁化方向；和
第二非磁性层，所述第二非磁性层在空间上分离所述自由磁性层与所述参考磁性层，其中，由所述自由磁性层、所述第二非磁性层和所述参考磁性层形成磁隧穿结，其中穿过所述存储器单元施加具有选定的振幅和持续时间的电流脉冲切换所述可变磁化向量，且其中所述磁隧穿结在空间上位于所述钉扎磁性层下；及
电流源，所述电流源连接到所述钉扎磁性层和所述参考磁性层，以使得电流从所述第二非磁性层传送到所述钉扎磁性层。
13.根据权利要求12所述的存储系统，其中，所述存储器单元进一步包括合成反铁磁体层，其中，所述合成反铁磁体层包括所述钉扎磁性层。
14.根据权利要求13所述的存储系统，其中，所述合成反铁磁体层减小了在所述钉扎磁性层与所述自由磁性层之间的磁相互作用。
15.根据权利要求13所述的存储系统，其中，所述合成反铁磁体层是选自于包括钌、铬或铜的组的材料。
16.根据权利要求13所述的存储系统，进一步包括反铁磁体，所述反铁磁体针扎住所述合成反铁磁体层，提供垂直交换偏置。
17.根据权利要求12所述的存储系统，进一步包括第二磁隧穿结，所述第二磁隧穿结包括所述钉扎磁性层和所述自由磁性层。
18.一种制造存储器件的方法，包括：
形成参考磁性层，所述参考磁性层具有第二固定磁化向量，所述第二固定磁化向量具有第二固定磁化方向；
形成第二非磁性层，所述第二非磁性层在空间上分离自由磁性层与所述参考磁性层；
形成所述自由磁性层，所述自由磁性层具有可变磁化向量，所述可变磁化向量至少具有第一稳态和第二稳态；
形成第一非磁性层，所述第一非磁性层在空间上分离钉扎磁性层与所述自由磁性层；以及
形成所述钉扎磁性层，所述钉扎磁性层具有第一固定磁化向量，所述第一固定磁化向量具有第一固定磁化方向，
其中，由所述自由磁性层、所述第二非磁性层和所述参考磁性层形成磁隧穿结，其中，穿过所述存储器件施加具有正或负极性与选定的振幅和持续时间的电流脉冲切换所述自由磁性层的可变磁化向量，且其中所述磁隧穿结在空间上位于所述钉扎磁性层下。
19.根据权利要求18所述的制造存储器件的方法，进一步包括形成合成反铁磁体层，其中，所述合成反铁磁体层包括所述钉扎磁性层。
20.根据权利要求19所述的制造存储器件的方法，其中，所述合成反铁磁体层减小了在所述钉扎磁性层与所述自由磁性层之间的磁相互作用。
CN201380053738.8A 2012-10-17 2013-10-15 倒置正交自旋转移叠层 Expired - Fee Related CN105051822B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261715111P 2012-10-17 2012-10-17
US61/715,111 2012-10-17
PCT/US2013/065055 WO2014062681A1 (en) 2012-10-17 2013-10-15 Inverted orthogonal spin transfer layer stack

Publications (2)

Publication Number Publication Date
CN105051822A CN105051822A (zh) 2015-11-11
CN105051822B true CN105051822B (zh) 2017-12-12

Family

ID=50474632

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380053738.8A Expired - Fee Related CN105051822B (zh) 2012-10-17 2013-10-15 倒置正交自旋转移叠层

Country Status (6)

Country Link
US (1) US9082888B2 (zh)
EP (1) EP2909838A4 (zh)
JP (1) JP2015537376A (zh)
KR (1) KR20150068970A (zh)
CN (1) CN105051822B (zh)
WO (1) WO2014062681A1 (zh)

Families Citing this family (87)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9299923B2 (en) * 2010-08-24 2016-03-29 Samsung Electronics Co., Ltd. Magnetic devices having perpendicular magnetic tunnel junction
US8836061B2 (en) * 2012-06-06 2014-09-16 Avalanche Technology, Inc. Magnetic tunnel junction with non-metallic layer adjacent to free layer
US20150279904A1 (en) * 2014-04-01 2015-10-01 Spin Transfer Technologies, Inc. Magnetic tunnel junction for mram device
US9263667B1 (en) 2014-07-25 2016-02-16 Spin Transfer Technologies, Inc. Method for manufacturing MTJ memory device
US9337412B2 (en) * 2014-09-22 2016-05-10 Spin Transfer Technologies, Inc. Magnetic tunnel junction structure for MRAM device
KR102238527B1 (ko) * 2014-09-29 2021-04-09 삼성전자주식회사 수직 자기 터널 접합 패턴을 포함하는 자기 기억 소자
US10468590B2 (en) 2015-04-21 2019-11-05 Spin Memory, Inc. High annealing temperature perpendicular magnetic anisotropy structure for magnetic random access memory
US9728712B2 (en) 2015-04-21 2017-08-08 Spin Transfer Technologies, Inc. Spin transfer torque structure for MRAM devices having a spin current injection capping layer
US9853206B2 (en) 2015-06-16 2017-12-26 Spin Transfer Technologies, Inc. Precessional spin current structure for MRAM
US9773974B2 (en) 2015-07-30 2017-09-26 Spin Transfer Technologies, Inc. Polishing stop layer(s) for processing arrays of semiconductor elements
US10163479B2 (en) 2015-08-14 2018-12-25 Spin Transfer Technologies, Inc. Method and apparatus for bipolar memory write-verify
US9852782B2 (en) 2015-08-31 2017-12-26 Western Digital Technologies, Inc. Tilted synthetic antiferromagnet polarizer/reference layer for STT-MRAM bits
US9741926B1 (en) 2016-01-28 2017-08-22 Spin Transfer Technologies, Inc. Memory cell having magnetic tunnel junction and thermal stability enhancement layer
JP2017183560A (ja) * 2016-03-31 2017-10-05 ソニー株式会社 メモリ素子、及びメモリ素子の製造方法
JP2018037616A (ja) * 2016-09-02 2018-03-08 株式会社サムスン日本研究所 磁気トンネル接合素子
US10546625B2 (en) 2016-09-27 2020-01-28 Spin Memory, Inc. Method of optimizing write voltage based on error buffer occupancy
US10460781B2 (en) 2016-09-27 2019-10-29 Spin Memory, Inc. Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank
US10991410B2 (en) 2016-09-27 2021-04-27 Spin Memory, Inc. Bi-polar write scheme
US10818331B2 (en) 2016-09-27 2020-10-27 Spin Memory, Inc. Multi-chip module for MRAM devices with levels of dynamic redundancy registers
US10366774B2 (en) 2016-09-27 2019-07-30 Spin Memory, Inc. Device with dynamic redundancy registers
US10360964B2 (en) 2016-09-27 2019-07-23 Spin Memory, Inc. Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device
US10437723B2 (en) 2016-09-27 2019-10-08 Spin Memory, Inc. Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device
US10628316B2 (en) 2016-09-27 2020-04-21 Spin Memory, Inc. Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register
US10437491B2 (en) 2016-09-27 2019-10-08 Spin Memory, Inc. Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register
US10446210B2 (en) 2016-09-27 2019-10-15 Spin Memory, Inc. Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers
US11151042B2 (en) 2016-09-27 2021-10-19 Integrated Silicon Solution, (Cayman) Inc. Error cache segmentation for power reduction
US11119936B2 (en) 2016-09-27 2021-09-14 Spin Memory, Inc. Error cache system with coarse and fine segments for power optimization
US11119910B2 (en) 2016-09-27 2021-09-14 Spin Memory, Inc. Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments
US10665777B2 (en) 2017-02-28 2020-05-26 Spin Memory, Inc. Precessional spin current structure with non-magnetic insertion layer for MRAM
US10672976B2 (en) 2017-02-28 2020-06-02 Spin Memory, Inc. Precessional spin current structure with high in-plane magnetization for MRAM
US10032978B1 (en) 2017-06-27 2018-07-24 Spin Transfer Technologies, Inc. MRAM with reduced stray magnetic fields
US10481976B2 (en) 2017-10-24 2019-11-19 Spin Memory, Inc. Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers
US10656994B2 (en) 2017-10-24 2020-05-19 Spin Memory, Inc. Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques
US10489245B2 (en) 2017-10-24 2019-11-26 Spin Memory, Inc. Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them
US10529439B2 (en) 2017-10-24 2020-01-07 Spin Memory, Inc. On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects
US10679685B2 (en) 2017-12-27 2020-06-09 Spin Memory, Inc. Shared bit line array architecture for magnetoresistive memory
US10811594B2 (en) 2017-12-28 2020-10-20 Spin Memory, Inc. Process for hard mask development for MRAM pillar formation using photolithography
US10516094B2 (en) 2017-12-28 2019-12-24 Spin Memory, Inc. Process for creating dense pillars using multiple exposures for MRAM fabrication
US10360962B1 (en) 2017-12-28 2019-07-23 Spin Memory, Inc. Memory array with individually trimmable sense amplifiers
US10424726B2 (en) 2017-12-28 2019-09-24 Spin Memory, Inc. Process for improving photoresist pillar adhesion during MRAM fabrication
US10395711B2 (en) 2017-12-28 2019-08-27 Spin Memory, Inc. Perpendicular source and bit lines for an MRAM array
US10395712B2 (en) 2017-12-28 2019-08-27 Spin Memory, Inc. Memory array with horizontal source line and sacrificial bitline per virtual source
US10891997B2 (en) 2017-12-28 2021-01-12 Spin Memory, Inc. Memory array with horizontal source line and a virtual source line
US10840439B2 (en) 2017-12-29 2020-11-17 Spin Memory, Inc. Magnetic tunnel junction (MTJ) fabrication methods and systems
US10355045B1 (en) * 2017-12-29 2019-07-16 Spin Memory, Inc. Three dimensional perpendicular magnetic junction with thin-film transistor
US10360961B1 (en) 2017-12-29 2019-07-23 Spin Memory, Inc. AC current pre-charge write-assist in orthogonal STT-MRAM
US10367139B2 (en) 2017-12-29 2019-07-30 Spin Memory, Inc. Methods of manufacturing magnetic tunnel junction devices
US10236048B1 (en) 2017-12-29 2019-03-19 Spin Memory, Inc. AC current write-assist in orthogonal STT-MRAM
US10629649B2 (en) 2017-12-29 2020-04-21 Spin Memory, Inc. Method of making a three dimensional perpendicular magnetic tunnel junction with thin-film transistor
US10199083B1 (en) 2017-12-29 2019-02-05 Spin Transfer Technologies, Inc. Three-terminal MRAM with ac write-assist for low read disturb
US10840436B2 (en) 2017-12-29 2020-11-17 Spin Memory, Inc. Perpendicular magnetic anisotropy interface tunnel junction devices and methods of manufacture
US10886330B2 (en) 2017-12-29 2021-01-05 Spin Memory, Inc. Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch
US10236047B1 (en) 2017-12-29 2019-03-19 Spin Memory, Inc. Shared oscillator (STNO) for MRAM array write-assist in orthogonal STT-MRAM
US10424723B2 (en) 2017-12-29 2019-09-24 Spin Memory, Inc. Magnetic tunnel junction devices including an optimization layer
US10784439B2 (en) 2017-12-29 2020-09-22 Spin Memory, Inc. Precessional spin current magnetic tunnel junction devices and methods of manufacture
US10270027B1 (en) 2017-12-29 2019-04-23 Spin Memory, Inc. Self-generating AC current assist in orthogonal STT-MRAM
US10546624B2 (en) 2017-12-29 2020-01-28 Spin Memory, Inc. Multi-port random access memory
US10236439B1 (en) 2017-12-30 2019-03-19 Spin Memory, Inc. Switching and stability control for perpendicular magnetic tunnel junction device
US10255962B1 (en) 2017-12-30 2019-04-09 Spin Memory, Inc. Microwave write-assist in orthogonal STT-MRAM
US10229724B1 (en) 2017-12-30 2019-03-12 Spin Memory, Inc. Microwave write-assist in series-interconnected orthogonal STT-MRAM devices
US10339993B1 (en) 2017-12-30 2019-07-02 Spin Memory, Inc. Perpendicular magnetic tunnel junction device with skyrmionic assist layers for free layer switching
US10141499B1 (en) 2017-12-30 2018-11-27 Spin Transfer Technologies, Inc. Perpendicular magnetic tunnel junction device with offset precessional spin current layer
US10319900B1 (en) 2017-12-30 2019-06-11 Spin Memory, Inc. Perpendicular magnetic tunnel junction device with precessional spin current layer having a modulated moment density
US10468588B2 (en) 2018-01-05 2019-11-05 Spin Memory, Inc. Perpendicular magnetic tunnel junction device with skyrmionic enhancement layers for the precessional spin current magnetic layer
US10438995B2 (en) 2018-01-08 2019-10-08 Spin Memory, Inc. Devices including magnetic tunnel junctions integrated with selectors
US10438996B2 (en) 2018-01-08 2019-10-08 Spin Memory, Inc. Methods of fabricating magnetic tunnel junctions integrated with selectors
US10388861B1 (en) 2018-03-08 2019-08-20 Spin Memory, Inc. Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same
US10446744B2 (en) 2018-03-08 2019-10-15 Spin Memory, Inc. Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same
US11107974B2 (en) 2018-03-23 2021-08-31 Spin Memory, Inc. Magnetic tunnel junction devices including a free magnetic trench layer and a planar reference magnetic layer
US20190296228A1 (en) 2018-03-23 2019-09-26 Spin Transfer Technologies, Inc. Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer
US10784437B2 (en) 2018-03-23 2020-09-22 Spin Memory, Inc. Three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer
US11107978B2 (en) 2018-03-23 2021-08-31 Spin Memory, Inc. Methods of manufacturing three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer
US11417829B2 (en) 2018-05-18 2022-08-16 Integrated Silicon Solution, (Cayman) Inc. Three dimensional perpendicular magnetic tunnel junction with thin film transistor array
US10411185B1 (en) 2018-05-30 2019-09-10 Spin Memory, Inc. Process for creating a high density magnetic tunnel junction array test platform
US10593396B2 (en) 2018-07-06 2020-03-17 Spin Memory, Inc. Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations
US10600478B2 (en) 2018-07-06 2020-03-24 Spin Memory, Inc. Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations
US10692569B2 (en) 2018-07-06 2020-06-23 Spin Memory, Inc. Read-out techniques for multi-bit cells
US10559338B2 (en) 2018-07-06 2020-02-11 Spin Memory, Inc. Multi-bit cell read-out techniques
US10650875B2 (en) 2018-08-21 2020-05-12 Spin Memory, Inc. System for a wide temperature range nonvolatile memory
US10699761B2 (en) 2018-09-18 2020-06-30 Spin Memory, Inc. Word line decoder memory architecture
US10971680B2 (en) 2018-10-01 2021-04-06 Spin Memory, Inc. Multi terminal device stack formation methods
US11621293B2 (en) 2018-10-01 2023-04-04 Integrated Silicon Solution, (Cayman) Inc. Multi terminal device stack systems and methods
US10580827B1 (en) 2018-11-16 2020-03-03 Spin Memory, Inc. Adjustable stabilizer/polarizer method for MRAM with enhanced stability and efficient switching
JP7136492B2 (ja) * 2018-11-29 2022-09-13 国立研究開発法人物質・材料研究機構 磁気抵抗効果素子、磁気センサ、再生ヘッドおよび磁気記録再生装置
US11107979B2 (en) 2018-12-28 2021-08-31 Spin Memory, Inc. Patterned silicide structures and methods of manufacture
US10788547B2 (en) 2019-01-17 2020-09-29 Sandisk Technologies Llc Voltage-controlled interlayer exchange coupling magnetoresistive memory device and method of operating thereof
US11049538B2 (en) 2019-01-17 2021-06-29 Western Digital Technologies, Inc. Voltage-controlled interlayer exchange coupling magnetoresistive memory device and method of operating thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1938874A (zh) * 2004-02-19 2007-03-28 弘世科技公司 具有低饱和磁化强度自由层的自旋转移磁性元件
CN1947272A (zh) * 2004-02-26 2007-04-11 弘世科技公司 具有高垂直各向异性和平面内平衡磁化的自由层的自旋转移磁性元件

Family Cites Families (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5597437A (en) 1995-01-12 1997-01-28 Procter & Gamble Zero scrap absorbent core formation process
US5541868A (en) 1995-02-21 1996-07-30 The United States Of America As Represented By The Secretary Of The Navy Annular GMR-based memory element
US6140838A (en) 1995-04-21 2000-10-31 Johnson; Mark B. High density and high speed magneto-electronic logic family
US5629549A (en) 1995-04-21 1997-05-13 Johnson; Mark B. Magnetic spin transistor device, logic gate & method of operation
US5654566A (en) 1995-04-21 1997-08-05 Johnson; Mark B. Magnetic spin injected field effect transistor and method of operation
US5896252A (en) 1995-08-11 1999-04-20 Fujitsu Limited Multilayer spin valve magneto-resistive effect magnetic head with free magnetic layer including two sublayers and magnetic disk drive including same
JP3207094B2 (ja) 1995-08-21 2001-09-10 松下電器産業株式会社 磁気抵抗効果素子及びメモリー素子
US5695864A (en) 1995-09-28 1997-12-09 International Business Machines Corporation Electronic device using magnetic components
DE19701509C2 (de) 1996-01-19 2003-08-21 Fujitsu Ltd Magnetsensoren
US5640343A (en) 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
JP3327375B2 (ja) 1996-04-26 2002-09-24 富士通株式会社 磁気抵抗効果型トランスデューサ、その製造方法及び磁気記録装置
JP3447468B2 (ja) 1996-06-17 2003-09-16 シャープ株式会社 磁気抵抗効果素子及びその製造方法並びにそれを用いた磁気ヘッド
US5768069A (en) 1996-11-27 1998-06-16 International Business Machines Corporation Self-biased dual spin valve sensor
JP3557078B2 (ja) 1997-06-27 2004-08-25 株式会社東芝 不揮発性半導体記憶装置
JP4040173B2 (ja) 1998-06-05 2008-01-30 キヤノン株式会社 メモリ
JP4066477B2 (ja) 1997-10-09 2008-03-26 ソニー株式会社 不揮発性ランダムアクセスメモリー装置
US5966323A (en) 1997-12-18 1999-10-12 Motorola, Inc. Low switching field magnetoresistive tunneling junction for high density arrays
US6055179A (en) 1998-05-19 2000-04-25 Canon Kk Memory device utilizing giant magnetoresistance effect
US6130814A (en) 1998-07-28 2000-10-10 International Business Machines Corporation Current-induced magnetic switching device and memory including the same
US6172902B1 (en) 1998-08-12 2001-01-09 Ecole Polytechnique Federale De Lausanne (Epfl) Non-volatile magnetic random access memory
US6016269A (en) 1998-09-30 2000-01-18 Motorola, Inc. Quantum random address memory with magnetic readout and/or nano-memory elements
US6278594B1 (en) 1998-10-13 2001-08-21 Storage Technology Corporation Dual element magnetoresistive read head with integral element stabilization
JP3766565B2 (ja) 1999-05-31 2006-04-12 Ｔｄｋ株式会社 磁気抵抗効果膜および磁気抵抗効果型ヘッド
JP3589346B2 (ja) * 1999-06-17 2004-11-17 松下電器産業株式会社 磁気抵抗効果素子および磁気抵抗効果記憶素子
WO2001001396A1 (fr) 1999-06-29 2001-01-04 Fujitsu Limited Tete magnetoresistive et dispositif de reproduction d'informations
US6292389B1 (en) 1999-07-19 2001-09-18 Motorola, Inc. Magnetic element with improved field response and fabricating method thereof
US6134138A (en) 1999-07-30 2000-10-17 Honeywell Inc. Method and apparatus for reading a magnetoresistive memory
JP3793669B2 (ja) 1999-08-26 2006-07-05 株式会社日立グローバルストレージテクノロジーズ 巨大磁気抵抗効果ヘッド、薄膜磁気ヘッドならびに磁気記録再生装置
US6611405B1 (en) 1999-09-16 2003-08-26 Kabushiki Kaisha Toshiba Magnetoresistive element and magnetic memory device
KR100373473B1 (ko) 1999-09-24 2003-02-25 가부시끼가이샤 도시바 자기 저항 효과 소자, 자기 저항 효과 헤드, 자기 재생장치 및 자성 적층체
JP3891540B2 (ja) 1999-10-25 2007-03-14 キヤノン株式会社 磁気抵抗効果メモリ、磁気抵抗効果メモリに記録される情報の記録再生方法、およびｍｒａｍ
US6447935B1 (en) 1999-11-23 2002-09-10 Read-Rite Corporation Method and system for reducing assymetry in a spin valve having a synthetic pinned layer
US6233172B1 (en) 1999-12-17 2001-05-15 Motorola, Inc. Magnetic element with dual magnetic states and fabrication method thereof
US6272036B1 (en) 1999-12-20 2001-08-07 The University Of Chicago Control of magnetic direction in multi-layer ferromagnetic devices by bias voltage
TW504713B (en) 2000-04-28 2002-10-01 Motorola Inc Magnetic element with insulating veils and fabricating method thereof
US6522137B1 (en) 2000-06-28 2003-02-18 Schlumberger Technology Corporation Two-dimensional magnetic resonance imaging in a borehole
US6493259B1 (en) 2000-08-14 2002-12-10 Micron Technology, Inc. Pulse write techniques for magneto-resistive memories
US6385082B1 (en) 2000-11-08 2002-05-07 International Business Machines Corp. Thermally-assisted magnetic random access memory (MRAM)
FR2817999B1 (fr) 2000-12-07 2003-01-10 Commissariat Energie Atomique Dispositif magnetique a polarisation de spin et a empilement(s) tri-couche(s) et memoire utilisant ce dispositif
FR2817998B1 (fr) 2000-12-07 2003-01-10 Commissariat Energie Atomique Dispositif magnetique a polarisation de spin et a rotation d'aimantation, memoire et procede d'ecriture utilisant ce dispositif
JPWO2002050924A1 (ja) 2000-12-21 2004-04-22 富士通株式会社 磁気抵抗効果素子、磁気ヘッド及びこれを用いる磁気再生装置
US6713195B2 (en) 2001-01-05 2004-03-30 Nve Corporation Magnetic devices using nanocomposite materials
JP3576111B2 (ja) 2001-03-12 2004-10-13 株式会社東芝 磁気抵抗効果素子
US6653154B2 (en) 2001-03-15 2003-11-25 Micron Technology, Inc. Method of forming self-aligned, trenchless mangetoresistive random-access memory (MRAM) structure with sidewall containment of MRAM structure
JP2002334971A (ja) 2001-05-09 2002-11-22 Nec Corp 磁性メモリ及びその動作方法
US6744086B2 (en) 2001-05-15 2004-06-01 Nve Corporation Current switched magnetoresistive memory cell
JP2002357489A (ja) 2001-05-31 2002-12-13 Matsushita Electric Ind Co Ltd 応力センサー
US6347049B1 (en) 2001-07-25 2002-02-12 International Business Machines Corporation Low resistance magnetic tunnel junction device with bilayer or multilayer tunnel barrier
US6902807B1 (en) 2002-09-13 2005-06-07 Flex Products, Inc. Alignable diffractive pigment flakes
US6777730B2 (en) 2001-08-31 2004-08-17 Nve Corporation Antiparallel magnetoresistive memory cells
US6545906B1 (en) 2001-10-16 2003-04-08 Motorola, Inc. Method of writing to scalable magnetoresistance random access memory element
FR2832542B1 (fr) 2001-11-16 2005-05-06 Commissariat Energie Atomique Dispositif magnetique a jonction tunnel magnetique, memoire et procedes d'ecriture et de lecture utilisant ce dispositif
US6750491B2 (en) 2001-12-20 2004-06-15 Hewlett-Packard Development Company, L.P. Magnetic memory device having soft reference layer
JP3583102B2 (ja) 2001-12-27 2004-10-27 株式会社東芝 磁気スイッチング素子及び磁気メモリ
US6773515B2 (en) 2002-01-16 2004-08-10 Headway Technologies, Inc. FeTa nano-oxide layer as a capping layer for enhancement of giant magnetoresistance in bottom spin valve structures
JP3769241B2 (ja) 2002-03-29 2006-04-19 株式会社東芝 磁気抵抗効果素子及び磁気メモリ
WO2003090290A1 (fr) 2002-04-22 2003-10-30 Matsushita Electric Industrial Co., Ltd. Element a effet de resistance magnetique, tete magnetique en comportant, memoire magnetique, et enregistreur magnetique
JP2003318461A (ja) 2002-04-22 2003-11-07 Matsushita Electric Ind Co Ltd 磁気抵抗効果素子とこれを用いた磁気ヘッドおよび磁気メモリならびに磁気記録装置
US6879512B2 (en) 2002-05-24 2005-04-12 International Business Machines Corporation Nonvolatile memory device utilizing spin-valve-type designs and current pulses
US7005958B2 (en) 2002-06-14 2006-02-28 Honeywell International Inc. Dual axis magnetic sensor
US7095646B2 (en) 2002-07-17 2006-08-22 Freescale Semiconductor, Inc. Multi-state magnetoresistance random access cell with improved memory storage density
US6654278B1 (en) 2002-07-31 2003-11-25 Motorola, Inc. Magnetoresistance random access memory
US6714444B2 (en) 2002-08-06 2004-03-30 Grandis, Inc. Magnetic element utilizing spin transfer and an MRAM device using the magnetic element
US6888742B1 (en) 2002-08-28 2005-05-03 Grandis, Inc. Off-axis pinned layer magnetic element utilizing spin transfer and an MRAM device using the magnetic element
US6838740B2 (en) 2002-09-27 2005-01-04 Grandis, Inc. Thermally stable magnetic elements utilizing spin transfer and an MRAM device using the magnetic element
US6958927B1 (en) 2002-10-09 2005-10-25 Grandis Inc. Magnetic element utilizing spin-transfer and half-metals and an MRAM device using the magnetic element
US6956257B2 (en) 2002-11-18 2005-10-18 Carnegie Mellon University Magnetic memory element and memory device including same
US7190611B2 (en) 2003-01-07 2007-03-13 Grandis, Inc. Spin-transfer multilayer stack containing magnetic layers with resettable magnetization
US6829161B2 (en) 2003-01-10 2004-12-07 Grandis, Inc. Magnetostatically coupled magnetic elements utilizing spin transfer and an MRAM device using the magnetic element
GB2415304B (en) 2003-02-10 2006-11-15 Massachusetts Inst Technology Magnetic memory elements using 360 degree walls
US6847547B2 (en) 2003-02-28 2005-01-25 Grandis, Inc. Magnetostatically coupled magnetic elements utilizing spin transfer and an MRAM device using the magnetic element
JP3546238B1 (ja) 2003-04-23 2004-07-21 学校法人慶應義塾 磁気リングユニット及び磁気メモリ装置
US6933155B2 (en) 2003-05-21 2005-08-23 Grandis, Inc. Methods for providing a sub .15 micron magnetic memory structure
US7054119B2 (en) 2003-06-18 2006-05-30 Hewlett-Packard Development Company, L.P. Coupled ferromagnetic systems having modified interfaces
US7151652B2 (en) * 2003-06-18 2006-12-19 Hewett-Packard Development Company, L.P. Top-pinned magnetoresistive device having adjusted interface property
US6818961B1 (en) 2003-06-30 2004-11-16 Freescale Semiconductor, Inc. Oblique deposition to induce magnetic anisotropy for MRAM cells
US7911832B2 (en) 2003-08-19 2011-03-22 New York University High speed low power magnetic devices based on current induced spin-momentum transfer
US7573737B2 (en) * 2003-08-19 2009-08-11 New York University High speed low power magnetic devices based on current induced spin-momentum transfer
US6980469B2 (en) 2003-08-19 2005-12-27 New York University High speed low power magnetic devices based on current induced spin-momentum transfer
US7245462B2 (en) 2003-08-21 2007-07-17 Grandis, Inc. Magnetoresistive element having reduced spin transfer induced noise
US6985385B2 (en) 2003-08-26 2006-01-10 Grandis, Inc. Magnetic memory element utilizing spin transfer switching and storing multiple bits
US7161829B2 (en) 2003-09-19 2007-01-09 Grandis, Inc. Current confined pass layer for magnetic elements utilizing spin-transfer and an MRAM device using such magnetic elements
US20050128842A1 (en) 2003-11-07 2005-06-16 Alexander Wei Annular magnetic nanostructures
US7009877B1 (en) 2003-11-14 2006-03-07 Grandis, Inc. Three-terminal magnetostatically coupled spin transfer-based MRAM cell
JP2005150482A (ja) 2003-11-18 2005-06-09 Sony Corp 磁気抵抗効果素子及び磁気メモリ装置
US7602000B2 (en) 2003-11-19 2009-10-13 International Business Machines Corporation Spin-current switched magnetic memory element suitable for circuit integration and method of fabricating the memory element
US20050136600A1 (en) 2003-12-22 2005-06-23 Yiming Huai Magnetic elements with ballistic magnetoresistance utilizing spin-transfer and an MRAM device using such magnetic elements
US6936479B2 (en) 2004-01-15 2005-08-30 Hewlett-Packard Development Company, L.P. Method of making toroidal MRAM cells
US7110287B2 (en) 2004-02-13 2006-09-19 Grandis, Inc. Method and system for providing heat assisted switching of a magnetic element utilizing spin transfer
US7203129B2 (en) 2004-02-16 2007-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Segmented MRAM memory array
US6967863B2 (en) 2004-02-25 2005-11-22 Grandis, Inc. Perpendicular magnetization magnetic element utilizing spin transfer
US7233039B2 (en) 2004-04-21 2007-06-19 Grandis, Inc. Spin transfer magnetic elements with spin depolarization layers
US7098494B2 (en) 2004-06-16 2006-08-29 Grandis, Inc. Re-configurable logic elements using heat assisted magnetic tunneling elements
US7270896B2 (en) * 2004-07-02 2007-09-18 International Business Machines Corporation High performance magnetic tunnel barriers with amorphous materials
US7576956B2 (en) 2004-07-26 2009-08-18 Grandis Inc. Magnetic tunnel junction having diffusion stop layer
US7369427B2 (en) 2004-09-09 2008-05-06 Grandis, Inc. Magnetic elements with spin engineered insertion layers and MRAM devices using the magnetic elements
US7149106B2 (en) * 2004-10-22 2006-12-12 Freescale Semiconductor, Inc. Spin-transfer based MRAM using angular-dependent selectivity
JP4682585B2 (ja) 2004-11-01 2011-05-11 ソニー株式会社 記憶素子及びメモリ
JP4550552B2 (ja) * 2004-11-02 2010-09-22 株式会社東芝 磁気抵抗効果素子、磁気ランダムアクセスメモリ、磁気抵抗効果素子の製造方法
JP4575136B2 (ja) 2004-12-20 2010-11-04 株式会社東芝 磁気記録素子、磁気記録装置、および情報の記録方法
JP4693450B2 (ja) 2005-03-22 2011-06-01 株式会社東芝 磁気抵抗効果素子および磁気メモリ
JP5181672B2 (ja) 2005-03-29 2013-04-10 日本電気株式会社 磁気ランダムアクセスメモリ
US20070019337A1 (en) 2005-07-19 2007-01-25 Dmytro Apalkov Magnetic elements having improved switching characteristics and magnetic memory devices using the magnetic elements
FR2888994B1 (fr) 2005-07-21 2007-10-12 Commissariat Energie Atomique Dispositif radiofrequence avec element magnetique et procede de fabrication d'un tel element magnetique
US8324154B2 (en) 2005-12-22 2012-12-04 Novabiotics, Ltd. Treatment of fungal infections with cyclic antimicrobial peptides
US8084835B2 (en) 2006-10-20 2011-12-27 Avalanche Technology, Inc. Non-uniform switching based non-volatile magnetic based memory
TWI320929B (en) 2006-04-18 2010-02-21 Ind Tech Res Inst Structure and access method for magnetic memory cell structure and circuit of magnetic memory
US7502253B2 (en) 2006-08-28 2009-03-10 Everspin Technologies, Inc. Spin-transfer based MRAM with reduced critical current density
JP2008066612A (ja) * 2006-09-11 2008-03-21 Fujitsu Ltd トンネル磁気抵抗効果素子及びその製造方法。
US7508042B2 (en) * 2006-12-22 2009-03-24 Magic Technologies, Inc. Spin transfer MRAM device with magnetic biasing
FR2910716B1 (fr) 2006-12-26 2010-03-26 Commissariat Energie Atomique Dispositif magnetique multicouches, procede pour sa realisation, capteur de champ magnetique, memoire magnetique et porte logique mettant en oeuvre un tel dispositif
JP4380707B2 (ja) 2007-01-19 2009-12-09 ソニー株式会社 記憶素子
US7778074B2 (en) 2007-03-23 2010-08-17 Sigmatel, Inc. System and method to control one time programmable memory
US7750421B2 (en) 2007-07-23 2010-07-06 Magic Technologies, Inc. High performance MTJ element for STT-RAM and method for making the same
AU2008219354B2 (en) 2007-09-19 2014-02-13 Viavi Solutions Inc. Anisotropic magnetic flakes
JP5236244B2 (ja) 2007-10-16 2013-07-17 株式会社日立製作所 磁気記録媒体の製造方法
FR2925725B1 (fr) 2007-12-21 2011-03-25 Commissariat Energie Atomique Procede de modelisation d'une jonction tunnel magnetique a ecriture par courant polarise en spin
CN101546598B (zh) * 2008-03-27 2011-12-14 台湾积体电路制造股份有限公司 磁阻随机存取存储器装置与其切换方法与存储器阵列
JP5010565B2 (ja) * 2008-09-26 2012-08-29 株式会社東芝 磁気抵抗素子及び磁気メモリ
GB2465369B (en) 2008-11-13 2011-01-12 Ingenia Holdings Magnetic data storage device and method
US8378438B2 (en) 2008-12-04 2013-02-19 Grandis, Inc. Method and system for providing magnetic elements having enhanced magnetic anisotropy and memories using such magnetic elements
US8053255B2 (en) 2009-03-03 2011-11-08 Seagate Technology Llc STRAM with compensation element and method of making the same
US7936598B2 (en) 2009-04-28 2011-05-03 Seagate Technology Magnetic stack having assist layer
FR2946183B1 (fr) 2009-05-27 2011-12-23 Commissariat Energie Atomique Dispositif magnetique a polarisation de spin.
US8779538B2 (en) 2009-08-10 2014-07-15 Samsung Electronics Co., Ltd. Magnetic tunneling junction seed, capping, and spacer layer materials
JP5644198B2 (ja) * 2010-06-15 2014-12-24 ソニー株式会社 記憶装置
JP2012015213A (ja) * 2010-06-29 2012-01-19 Sony Corp 記憶素子、記憶素子の製造方法、及び、メモリ
US8546896B2 (en) * 2010-07-16 2013-10-01 Grandis, Inc. Magnetic tunneling junction elements having magnetic substructures(s) with a perpendicular anisotropy and memories using such magnetic elements
US8492860B2 (en) * 2011-02-25 2013-07-23 Avalanche Technology, Inc. Magnetic random access memory with switching assist layer
US8704319B2 (en) 2010-12-31 2014-04-22 Samsung Electronics Co., Ltd. Method and system for providing magnetic layers having insertion layers for use in spin transfer torque memories
US9245608B2 (en) 2011-09-22 2016-01-26 Qualcomm Incorporated Thermally tolerant perpendicular magnetic anisotropy coupled elements for spin-transfer torque switching device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1938874A (zh) * 2004-02-19 2007-03-28 弘世科技公司 具有低饱和磁化强度自由层的自旋转移磁性元件
CN1947272A (zh) * 2004-02-26 2007-04-11 弘世科技公司 具有高垂直各向异性和平面内平衡磁化的自由层的自旋转移磁性元件

Also Published As

Publication number Publication date
EP2909838A1 (en) 2015-08-26
CN105051822A (zh) 2015-11-11
US20140103472A1 (en) 2014-04-17
US9082888B2 (en) 2015-07-14
EP2909838A4 (en) 2016-06-01
WO2014062681A1 (en) 2014-04-24
JP2015537376A (ja) 2015-12-24
KR20150068970A (ko) 2015-06-22

Similar Documents

Publication Publication Date Title
CN105051822B (zh) 倒置正交自旋转移叠层
US10516103B1 (en) Magnetoresistive stack and method of fabricating same
US10147872B2 (en) Spin transfer torque structure for MRAM devices having a spin current injection capping layer
CN108292703B (zh) 自旋流磁化反转元件、磁阻效应元件及磁存储器
KR100900109B1 (ko) 자기저항 효과 소자 및 자기저항 랜덤 액세스 메모리
US20150279904A1 (en) Magnetic tunnel junction for mram device
US20120267733A1 (en) Magnetic stacks with perpendicular magnetic anisotropy for spin momentum transfer magnetoresistive random access memory
WO2017131894A1 (en) Memory cell having magnetic tunnel junction and thermal stability enhancement layer
US9082950B2 (en) Increased magnetoresistance in an inverted orthogonal spin transfer layer stack
WO2011062005A1 (ja) 強磁性トンネル接合素子
JP2011014602A (ja) 二重障壁強磁性トンネル接合および磁気デバイス

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171212

Termination date: 20201015