CN104821307B - 智能卡载带及封装方法 - Google Patents

智能卡载带及封装方法 Download PDF

Info

Publication number
CN104821307B
CN104821307B CN201510203554.6A CN201510203554A CN104821307B CN 104821307 B CN104821307 B CN 104821307B CN 201510203554 A CN201510203554 A CN 201510203554A CN 104821307 B CN104821307 B CN 104821307B
Authority
CN
China
Prior art keywords
chip
belt
carrier band
smart card
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510203554.6A
Other languages
English (en)
Other versions
CN104821307A (zh
Inventor
高洪涛
陆美华
刘玉宝
沈爱明
张立
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Inore Information Electronics Co., Ltd.
Original Assignee
SHANGHAI ETERNAL INFORMATION TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHANGHAI ETERNAL INFORMATION TECHNOLOGY Co Ltd filed Critical SHANGHAI ETERNAL INFORMATION TECHNOLOGY Co Ltd
Priority to CN201510203554.6A priority Critical patent/CN104821307B/zh
Publication of CN104821307A publication Critical patent/CN104821307A/zh
Application granted granted Critical
Publication of CN104821307B publication Critical patent/CN104821307B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明提供一种智能卡载带及封装方法，所述智能卡载带包括多个载带单元，每一所述载带单元包括一芯片放置区及至少一焊垫区，所述芯片放置区用于承载芯片，所述焊垫区包括多个焊垫，所述芯片放置区的芯片与所述至少一个焊垫电连接，所述芯片放置区与所有所述焊垫区沿所述智能卡载带前进方向平行放置。本发明的优点在于，在相同的载带宽度内，载带单元分布密度至少提高30%，提高了载带利用率，且同时进行封装的芯片数目增加，封装效率提高。同时对于较长的焊线采用桥式打线，降低了焊线的弧高，从而在封装体封装后将封装高度降低至少50微米，实现薄型封装。

Description

智能卡载带及封装方法
技术领域
本发明涉及智能卡领域，尤其涉及一种智能卡载带及封装方法。
背景技术
目前智能卡载带的设置如图1所示，所述载带10包括多个载带单元11，每一所述载带单元11的焊垫区12及芯片放置区13平行所述载带10的前进方向设置，所述载带10的前进方向如图1中箭头所示，其中GND表示接地焊垫。这种载带单元11的排布的缺点在于，在载带10宽度方向，放置的载带单元11的数量较少，使得载带10利用率低，在载带10宽度方向的载带单元11密度低，且同时进行封装的芯片数目少，封装效率低。
目前亟需一种利用率高的载带。
发明内容
本发明所要解决的技术问题是，提供一种智能卡载带及封装方法，其能够提高智能卡载带利用率，提高智能卡载带宽度方向的载带单元密度，提高封装效率。
为了解决上述问题，本发明提供了一种智能卡载带，包括多个载带单元，每一所述载带单元包括一芯片放置区及至少一焊垫区，所述芯片放置区用于承载芯片，所述焊垫区包括多个焊垫，所述芯片放置区的芯片与所述至少一个焊垫电连接，所述芯片放置区与所有所述焊垫区沿所述智能卡载带前进方向平行放置。
进一步，所述载带单元包括第一焊垫区和第二焊垫区，所述芯片放置区位于所述第一焊垫区与第二焊垫区之间，沿所述智能卡载带前进方向，所述第一焊垫区、所述芯片放置区及所述第二焊垫区依次平行设置。
进一步，在所述智能卡载带宽度方向，多个所述载带单元依次设置，所述智能卡载带宽度方向与所述智能卡载带前进方向垂直。
本发明还提供一种上述的智能卡载带的封装方法，包括如下步骤：
固晶，将所述芯片粘贴在芯片放置区，所述芯片上的焊点与所述焊垫区的焊垫对应设置；打线，将所述芯片的焊点与所述焊垫区的焊垫电连接；塑封，将所述芯片与焊垫塑封，形成封装体。
进一步，在打线步骤中，所述芯片的接地焊点与所述焊垫区的接地焊垫之间进行两次打线，以降低焊线弧度。
本发明的一个优点在于，在相同的智能卡载带宽度内，载带单元分布密度至少提高30%，提高了智能卡载带利用率，且同时进行封装的芯片数目增加，封装效率提高。
本发明的另一个优点在于，对于较长的焊线采用桥式打线，降低了焊线的弧高，从而在封装体封装后将封装高度降低至少50微米，实现薄型封装。
附图说明
图1是现有的载带示意图；
图2是本发明智能卡载带示意图；
图3A~图3C是本发明封装方法的工艺流程图；
图4是图3B中打线后的截面示意图；
图5是现有技术中打线后的截面示意图。
具体实施方式
下面结合附图对本发明提供的智能卡载带及封装方法的具体实施方式做详细说明。
参见图2，本发明智能卡载带20，包括多个载带单元21。在所述智能卡载带20的宽度方向，多个所述载带单元21依次设置。所述智能卡载带20的宽度方向与所述智能卡载带20前进方向垂直，所述智能卡载带20前进方向如图2中箭头所示。
每一所述载带单元21包括一芯片放置区22及至少一焊垫区。所述芯片放置区22用于承载芯片（附图中未标示），所述芯片可粘贴在所述芯片放置区22，所述粘贴方法为现有技术，本发明不赘述。
在本具体实施方式中，所述焊垫区包括第一焊垫区23及第二焊垫区24。所述芯片放置区22与所有所述焊垫区沿所述智能卡载带前进方向平行放置，即在本具体实施方式中，所述芯片放置区22位于所述第一焊垫区23与第二焊垫区24之间，沿所述智能卡载带前进方向，所述第一焊垫区23、所述芯片放置区22及所述第二焊垫区24依次平行设置。所述焊垫区包括多个焊垫25，所述芯片放置区22的芯片与所述至少一个焊垫25电连接。
在现有技术中，参见图1，所述载带单元11的焊垫区12及芯片放置区13平行所述载带10的前进方向设置，所述载带单元11的较长边沿所述载带10宽度方向分布，使得在载带10的宽度方向分布的载带单元的个数较少。而本发明中，参见图2，所述芯片放置区22与所有所述焊垫区沿所述智能卡载带前进方向平行放置，所述载带单元21的较短边沿所述智能卡载带20宽度方向分布，使得在智能卡载带20的宽度方向分布的载带单元21的个数较多。相较于现有技术，所述载带单元的分布密度提高30%以上，从而能够提高生产效率，节约成本。
本发明还提供一种智能卡载带的封装方法，包括如下步骤：（1）固晶，将所述芯片粘贴在芯片放置区，所述芯片上的焊点与所述焊垫区的焊垫对应设置；（2）打线，将所述芯片的焊点与所述焊垫区的焊垫电连接；（3）塑封，将所述芯片与焊垫塑封，形成封装体。
图3A~图3C是本发明封装方法的工艺流程图。
参见图3A及步骤（1），固晶，将所述芯片30粘贴在芯片放置区32，所述芯片30上的焊点（附图中未标示）与所述焊垫区的焊垫35对应设置。在本具体实施方式中，所述焊垫区包括第一焊垫区33及第二焊垫区34，所述芯片放置区32设置在所述第一焊垫区33与第二焊垫区34之间，沿所述智能卡载带前进方向，所述第一焊垫区33、所述芯片放置区32及所述第二焊垫区34依次平行设置，所述焊垫区的接地焊垫位于所述第一焊垫区33上。与现有技术相比，本申请焊垫区旋转了90度，因此，为了使得所述芯片30上的焊点与所述焊垫区的焊垫35对应设置，在固晶时，需要将所述芯片30旋转90度进行固晶。
参见图3B、图4及步骤（2），打线，将所述芯片30的焊点与所述焊垫区的焊垫35电连接。打线工艺为现有的打线工艺，在此不赘述。由于接地焊垫GND与芯片相隔较远，采用一次打线会导致焊线过长或者弧度过高或者焊线塌陷，图5是现有的打线后的示意图，可见，打线后，焊线50弧度过高。因此，本发明采用两次打线，即桥式打线，先从芯片30的焊点打线至芯片，再从芯片打线至接地焊垫GND。两次打线能够降低焊线50的弧高，同时还可将封装高度降低至少50微米，实现薄型封装。本发明两次打线并不限于接地焊垫GND与芯片焊点的连接，其他间隔较大的焊垫与焊点之间也可以采用两次打线的方法。
参见图3C及步骤（3）塑封，将所述芯片30与焊垫35塑封，形成封装体40。该塑封方法为现有的塑封方法，在此不赘述。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (2)

1.一种智能卡载带，包括多个载带单元，其特征在于，每一所述载带单元包括一芯片放置区及至少一焊垫区，所述芯片放置区用于承载芯片，所述焊垫区包括多个焊垫，所述芯片放置区的芯片与所述至少一个焊垫电连接，所述芯片放置区与所有所述焊垫区沿所述智能卡载带前进方向平行放置，所述载带单元包括第一焊垫区和第二焊垫区，所述芯片放置区位于所述第一焊垫区与第二焊垫区之间，沿所述智能卡载带前进方向，所述第一焊垫区、所述芯片放置区及所述第二焊垫区依次平行设置。
2.根据权利要求1所述的智能卡载带，其特征在于，在所述智能卡载带宽度方向，多个所述载带单元依次设置，所述智能卡载带宽度方向与所述智能卡载带前进方向垂直。
CN201510203554.6A 2015-04-27 2015-04-27 智能卡载带及封装方法 Active CN104821307B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510203554.6A CN104821307B (zh) 2015-04-27 2015-04-27 智能卡载带及封装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510203554.6A CN104821307B (zh) 2015-04-27 2015-04-27 智能卡载带及封装方法

Publications (2)

Publication Number Publication Date
CN104821307A CN104821307A (zh) 2015-08-05
CN104821307B true CN104821307B (zh) 2017-12-19

Family

ID=53731556

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510203554.6A Active CN104821307B (zh) 2015-04-27 2015-04-27 智能卡载带及封装方法

Country Status (1)

Country Link
CN (1) CN104821307B (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1466198A (zh) * 2002-06-18 2004-01-07 ��Ʒ���ܹ�ҵ�ɷ����޹�˾ 用以缩短打线长度的半导体封装件
CN1497693A (zh) * 2002-10-08 2004-05-19 �ն��繤��ʽ���� 用于载带自动焊的载带
CN101409275A (zh) * 2007-11-28 2009-04-15 上海长丰智能卡有限公司 一种双界面智能卡模块及载带
CN102446868A (zh) * 2011-12-28 2012-05-09 上海长丰智能卡有限公司 一种新型双界面智能卡模块及其实现方式

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1466198A (zh) * 2002-06-18 2004-01-07 ��Ʒ���ܹ�ҵ�ɷ����޹�˾ 用以缩短打线长度的半导体封装件
CN1497693A (zh) * 2002-10-08 2004-05-19 �ն��繤��ʽ���� 用于载带自动焊的载带
CN101409275A (zh) * 2007-11-28 2009-04-15 上海长丰智能卡有限公司 一种双界面智能卡模块及载带
CN102446868A (zh) * 2011-12-28 2012-05-09 上海长丰智能卡有限公司 一种新型双界面智能卡模块及其实现方式

Also Published As

Publication number Publication date
CN104821307A (zh) 2015-08-05

Similar Documents

Publication Publication Date Title
CN102437141B (zh) 密节距小焊盘铜线键合单ic芯片封装件及其制备方法
CN104851863B (zh) 一种集成电路、引线键合封装芯片及倒装封装芯片
CN103887292A (zh) 堆叠式双芯片封装结构及其制备方法
CN104821307B (zh) 智能卡载带及封装方法
CN202977380U (zh) 一种qfn，dfn集成电路封装用线条式压焊夹具
CN206727065U (zh) 一种用于多组半导体芯片堆叠封装的结构
CN203733785U (zh) 一种具有改进型封装结构的半导体器件
CN106783793A (zh) 一种采用to型封装的半导体器件引线框架
CN208796987U (zh) 一种引线框架及其超薄型小外形倒装封装件
CN209544332U (zh) 具有转接焊垫的半导体封装结构及所使用的导线架
CN206558497U (zh) 一种采用to型封装的半导体器件引线框架
CN206364006U (zh) 一种半导体封装结构
CN105097747A (zh) 智能卡芯片封装结构及封装方法
CN106449517A (zh) 一种堆叠式单基岛sip封装工艺
CN107180809A (zh) 半导体封装结构及其封装方法
CN204991695U (zh) 智能卡芯片封装结构
CN207965944U (zh) 一种芯片卡
CN202150453U (zh) 一种双扁平无载体无引线内引脚交错型ic芯片封装件
CN107146777A (zh) 一种免切割封装结构及其制造工艺
CN104658985B (zh) 超薄半导体器件及制备方法
CN104409430B (zh) 一种半导体器件及其封装方法
CN202178252U (zh) 多圈排列无载体双ic芯片封装件
CN210040173U (zh) 半导体封装结构
CN202736909U (zh) 一种引线框架的宝塔式ic芯片堆叠封装件
CN210224022U (zh) 一种集成芯片及其集成框架

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20190620

Address after: Room 301, Room 3, Building 2, No. 3576 Zhaolou Road, Minhang District, Shanghai, 201112

Patentee after: Shanghai Inore Information Electronics Co., Ltd.

Address before: Room 1001, Building No. 1628 Suzhao Road, Minhang District, Shanghai 201158

Patentee before: Shanghai Eternal Information Technology Co., Ltd.

TR01 Transfer of patent right