CN1466198A - 用以缩短打线长度的半导体封装件 - Google Patents

用以缩短打线长度的半导体封装件 Download PDF

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CN1466198A
CN1466198A CNA021228728A CN02122872A CN1466198A CN 1466198 A CN1466198 A CN 1466198A CN A021228728 A CNA021228728 A CN A021228728A CN 02122872 A CN02122872 A CN 02122872A CN 1466198 A CN1466198 A CN 1466198A
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semiconductor package
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wire
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CN1303676C (zh
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廖致钦
陈冠成
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Siliconware Precision Industries Co Ltd
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Abstract

一种用以缩短打线长度的半导体封装件，具有一基板，其上设有一芯片黏置区俾供一半导体芯片接置，且该芯片黏置区外围并铺设有众多焊线垫，另于该芯片黏置区及该等焊线垫之间的基板表面上接设有若干个参差列置的桥接组件，以利导电连结该芯片及桥接组件的第一金线群以及电性藕接该桥接组件至焊线垫上的第二金线群之间相互电性通连而作为多次打线的中途连接点；多次打线方式取代单一金线焊接能够明显地缩短每次打线距离，降低单次打线的线弧跨距以及线弧高度，同时线弧跨距减少会增加连接端对于金线的支撑能力以承受模流冲击，避免金线发生倾倒(Wire Sweeping)或下陷(Wire Sagging)。

Description

用以缩短打线长度的半导体封装件
技术领域
本发明是关于一种半导体封装件，特别是一种缩短打线长度的引线焊接型球栅阵列(Wire Bond Ball Grid Array，WBBGA)半导体封装件。
背景技术
球栅阵列(Ball Grid Array，BGA)封装技术具备充足数量的输入/输出连接端(I/O Connections)以满足高密度电子组件及电子电路连接所需，现已成为高性能电子产品的封装主流。随着该方法技术不断进步，BGA半导体封装件上输入/输出连接端的数量及密度均大幅提高，因而须在基板上密集地布设多个与该输入/输出连接端电性通连的焊线垫(Fingers)作为半导体芯片的外接电性连接点，该半导体芯片能进行引线焊接(Wire Bonding)至该焊线垫上，再电性连结到外部电路。
一般提供BGA半导体封装件使用的焊线垫布局方式。如附图1所示，是先备一基板10，其上接置有一半导体芯片12，且该芯片12表面上是形成有若干个焊垫(Bond Pads)122；弧形排开的多个焊线垫103，是环置于该半导体芯片12外围；以及若干条金线13，分别地焊连该芯片12上各焊垫122与该焊线垫103而作为半导体芯片12的外接电路。(本图是为简化的示意图式，仅显示与本发明有关的部分；其实际实施封装单元的布局型态可能更形复杂)。
因传统蚀刻技术的限制，基板10上形成的多个焊线垫103中，每一焊线垫103最小宽度约为3密耳(mil，相当于千分之一英时)，加上相邻焊线垫103间最短距离约为3密耳，因此每增设一个焊线垫103即需占据约6密耳宽的距离(如图中P所示)。如附图1所示，若将该焊线垫103圆形环列在该半导体芯片12外围，且以半导体芯片12的几何中心作为圆心，则每一焊线垫距离芯片12中心的最短距离R即为6n/2π(其中n是表示焊线垫103的设置数量，而6n则是n个焊线垫构成的圆周长)；同理，芯片12上焊垫122距离芯片12中心的最短距离如以d表示，则焊线垫103与芯片12焊垫122间的打线最短距离，亦即线弧跨距(Wire Span)(如图中s所示)理论上应为R-d；因而，当基板10上输入/输出连接端(未图标)的数量大量增加，导致该焊线垫103设置数量n明显增多时，该焊线垫103形成的圆周6n会随之扩张。相对地该焊线垫103与芯片12焊垫122间的线弧跨距s亦会显著增加。
线弧跨距s增加会使线弧长度(Wire Length)拉长(一般线弧长度受弧度影响，约为线弧跨距的1.2倍)，从而造成打线作业执行困难，并且执行胶体封装时，极易受模流冲击引发焊线倾倒(Wire Sweeping)或下陷(Wire Sagging)，如附图2所示(图中虚线部分是原本金线位置，现受模流冲击(如箭头所示)造成偏移)进而形成短路。美国专利第6,031,281号案曾发明一种于模流冲击力最强的芯片部位增设多条伪焊线(Dummy Wire)以增加金线抗性而抵挡模流冲击，减少焊线倾倒现象发生；然而伪焊线的设置会增加制造过程的复杂性又使焊线成本明显地提升。
为改善上述打线作业的诸多问题，美国专利第5,898,213号案另提出一种缩短打线距离的焊线垫布局方式。如附图3所示，相比较于传统焊线垫布局方式，线弧长度会因焊线垫设置数量增加而拉长，该技术是以相邻焊线垫110′，111′间呈一上下交错方式(Staggered)环列于芯片12′外围以构成一圆周；其中，距离芯片12′中心较远的焊线垫定义为第一焊线垫群110′，距离芯片12′中心较近者定义作第二焊线垫群111′。因该第一焊线垫110′与第二焊线垫111′并非全部排开在同一弧面上，而是互相交错列置，因此实际上两相邻焊线垫110′，111′的最小间距P2已因交叉效应而减半为3密耳，故而焊线垫距离芯片中心的最短距离(未图标)为3n/2π(亦即1/2R)，明显缩短线弧打线距离。
此技术理论上虽能明显缩短线弧打线距离，然而实际运用时由于该第一焊线垫群110′与第二焊线垫群111′是互呈交错排列，金线焊接位置亦须配合焊线垫位置而调整，在打线机(Bonder)执行打线时常常无法辨识焊线垫位置，造成金线未能正确焊接到焊线垫反而打线到连接焊线垫的导电迹线上，导致焊接品质较差。
发明内容
本发明的主要目的是提供一种于芯片黏置区及焊线垫间的基板表面上接设若干个桥接组件，以供多次打线时连结线弧之用，借以缩短每次打线线弧长度，提升打线操作性的BGA半导体封装。
本发明的另一目的是提供一种于芯片黏置区及焊线垫间的基板表面上接设若干个桥接组件，以供多次打线时连结线弧之用，借以缩短每次打线线弧长度，增加连接端对于线弧支撑能力以承受模流冲击，令金线免于倾倒或下陷的BGA半导体封装件。
本发明的再一目的是提供一种运用现有制造技术，于芯片黏置区及焊线垫间的基板表面上参差配置若干个桥接组件，使封装成本符合经济效益的BGA半导体封装件。
鉴于上述及其它目的，本发明用以缩短打线长度的半导体封装件包含：一基板，其表面设有一芯片黏置区且该芯片黏置区外围并环布有众多焊线垫；若干个桥接组件，是参差列置于该芯片黏置区及焊线垫之间的基板表面上，供多次打线时连接线弧之用；至少一片半导体芯片，该芯片粘接到该芯片黏置区且其作用表面上形成有多个焊垫；一第一金线群及一第二金线群，是分别地提供该芯片焊垫与该桥接组件，以及该桥接组件与该焊线垫间进行电性导接；以及，一用以包覆该半导体芯片，多个金线以及该桥接组件的封装胶体。
封装件内增设桥接组件的目的，主是用以导电连结该第一金线群以及第二金线群，以顺利地实施多次打线作业；使得半导体芯片输出的电子讯号可经由芯片焊垫、第一金线群、桥接组件、第二金线群传递至焊线垫乃至于外部电路。
相较于传统单一金线焊接的封装结构，本发明的半导体封装件通过多次打线方式明显地缩短每次打线的打线距离，降低单次打线的线弧跨距以及线弧高度，借以提升打线操作性，同时线弧跨距减小将增加连接端对于金线的支撑能力以承受模流冲击，遂能避免金线倾倒(Wire Sweeping)或下陷(Wire Sagging)情况的发生。
附图说明
以下较佳实施例配合附图详细说明本发明的特点及功效：
附图1是为现有BGA半导体封装件其局部平面上视示意简图；
附图2是为附图1的封装结构受到封装树脂模流影响的立体示意图；
附图3是为美国专利第5,898,213号案发明的半导体封装件其上视示意图；
附图4是为本发明缩短打线长度的半导体封装件的剖面示意图；
附图5A是为本发明半导体封装件中，基板的上视示意图；
附图5B是为本发明半导体封装件施以多次打线后的局部剖面图；
附图5C是为本发明半导体封装件施以多次打线后的平面上视图；
附图6是为本发明半导体封装件与现有封装结构的剖面比较图；以及，
附图7是为本发明第二实施例的半导体封装件进行模压时的模流透视图。
具体实施方式
以下即配合附图4至附图6详细说明本发明用以缩短打线长度的半导体封装件具体实施例(下述各附图均为简化的示意图，且仅显示与本发明有关的组件，此类组件并非以实际数量或尺寸比例绘制；实际的封装结构布局可能更加复杂)，本发明封装结构中的桥接组件是参差列置于基板表面上以供多次打线之用，遂以引线焊接型球栅阵列(Wire Bond Ball Grid Array，WBBGA)半导体封装件作为本发明实施例的例示。
实施例1
如附图4所示，本发明半导体封装件2是包含一基板20，其上设有一芯片黏置区202，且该芯片黏置区202外围并环布有众多焊线垫203；若干个桥接组件21，是参差列置于该芯片黏置区202及焊线垫203之间的基板20表面上，以供多次打线时连接线弧之用；至少一片半导体芯片22，是粘接到该芯片黏置区202上；若干条金线23，用以提供该芯片22与该桥接组件21，以及该桥接组件21与该焊线垫203间的电性藕接；以及，一用以包覆该半导体芯片22，多个金线23以及该桥接组件21的封装胶体24。
附图5A是为本发明BGA半导体封装件的基板上视图。如图所示，此基板20具有一正面200及一相对的背面201，于该基板20正面200上预先规划有一芯片黏置区202以供一半导体芯片(未图标)粘接其上，且该芯片黏置区202外围是铺设有若干个连接导电迹线(未图标)并略呈弧形排开的焊线垫203；于该芯片黏置区202和各焊线垫203之间的基板20正面200上形成有多个参差列置的桥接组件21，以供每次打线时连结线弧之用。该桥接组件21为一类似焊垫的金属结构，其上分别具有一第一焊接部210及另一第二焊接部211以供不同金线群(未图标)焊连，然为使该桥接组件21与焊线(未图标)间具有较佳的焊接性，一般会于该桥接组件21表面镀上金属镍及金(Ni/Au)。
该桥接组件21采用参差列置方式散布至基板20上，使得相邻桥接组件21间拥有更大的安置空间，故能克服蚀刻技术对于间距宽度的限制，使得本发明半导体封装件在不提高封装成本的情况下，运用现有方法来进行实施。
请参阅附图5B(部分剖视图)及附图5C(平面上视图)，使用至少一片半导体芯片22，该芯片22具有一作用表面220(即铺设有多个电子电路及电子组件的表面)及一非作用表面221，且该作用表面220上是接设有若干个焊接焊垫222；借一胶粘层223将该半导体芯片22粘接至该基板20芯片黏置区202上，再进行两次打线作业：首先依现用打线方式自该芯片22焊垫222上打线连接至该桥接组件21第一焊接部210上以形成一第一金线群230，之后，再从该桥接组件21第二焊接部211进行第二次打线连结到该焊线垫203上，此第二次打线的线弧即称为第二金线群231。(本发明实施例是以两次打线方式做为范例解释的，真正作业情况需视该桥接组件在基板上的实际布局型态进行三次甚至多次打线作业)。最后，再看附图4，用一封装胶体24包覆该半导体芯片22、众多桥接组件21、第一金线群230以及第二金线群231，即完成本发明的BGA半导体封装件2。
本发明的半导体封装件2的特点是在基板20正面200上增设有多个参差列置的桥接组件21，该桥接组件21同时具有一第一焊接部210及一第二焊接部211，借以作为该第一焊接部210上的第一金线群230和第二焊接部211上的第二金线群231间电性相接的继电器(RelayContacts)，致使半导体芯片22输入/输出的电子讯号可通过焊垫222、第一金线群230、桥接组件21、第二金线群231再传递至焊线垫203上而形成一条提供芯片连通外部的导电路径。
参阅附图6所示，相较于仅经一次打线的现有封装结构(如附图6左半部所示)，本发明半导体封装件(如附图6右半部所示)采用多次打线技术可明显地缩短每次打线的线弧跨距(L减为L1和L2)以及线弧高度(Loop Height)(H降为H1和H2)，使打线困难度降低而提升其打线操作性(Operability)；同时，减少线弧弧长会使连接端对于线弧的支撑性提高，使金线不致受模流冲击而偏移，进一步维护焊线作业的品质。
实施例2
附图7所示是为本发明半导体封装件的第二实施例，本实施例与前述第一实施例的结构大致相同，其不同之处在于该桥接组件21并非广泛设置于半导体芯片22与所有焊线垫203之间的基板20表面上，而是选择胶体封装过程中模流冲击力最强的位置进行安置。如图所示，形成封装胶体(未图标)的树脂模流240流入模穴26后，与模流方向(如图中箭号所示)互为垂直的芯片22对角角端224位置承受模流240冲击力最强，导致金线230遭模流240冲击而发生倾倒或下陷，遂于该处增置若干个桥接组件21可以强化金线230支撑能力抵挡模流240冲击。本实施例只在部分芯片22位置设置桥接组件21，此举不仅能降低打线的复杂程度，亦可更有效地节省封装成本。
上述的具体实施例仅是用以解释本发明的特点及功效，而非用以限定本发明的实施范畴，在本发明权利要求书所限定的范围内，任何运用本发明内容而完成的等效改变及修饰，均应为本专利保护范围之内。

Claims (11)

1.一种半导体封装件，其特征在于，该半导体封装件包括：
一基板，其上设有一芯片黏置区，以及多数环布于该芯片黏置区外且与外界电性导通的导电部，其中，该芯片黏置区及该导电部间的基板上另接设有多数参差列置的桥接组件；
至少一片半导体芯片，是粘接至该芯片黏置区上；
多数第一导电组件，以供该半导体芯片电性导接至该等桥接组件上；
多数第二导电组件，是提供该等桥接组件与该导电部间进行电性藕接；以及
一封装胶体，用以包覆该半导体芯片、桥接组件、第一导电组件及第二导电组件。
2.如权利要求1所述的半导体封装件，其特征在于，该半导体封装件是为引线焊接型球栅阵列半导体封装件。
3.如权利要求1所述的半导体封装件，其特征在于，该导电部是为一焊线垫。
4.如权利要求1所述的半导体封装件，其特征在于，该桥接组件是接设于该半导体芯片的对角角端位置处。
5.如权利要求1所述的半导体封装件，其特征在于，该桥接组件是为一金属结构，且同时具有一第一焊接部及另一第二焊接部。
6.如权利要求1所述的半导体封装件，其特征在于，该等桥接组件表面镀有金属金及镍。
7.如权利要求1所述的半导体封装件，其特征在于，该半导体芯片具有一作用表面及一相对的非作用表面，且该作用表面上是接设有若干个焊接焊垫。
8.如权利要求1所述的半导体封装件，其特征在于，该第一导电组件是为第一金线。
9.如权利要求1或4或6所述的半导体封装件，其特征在于，该第一导电组件是电性连接该等焊接焊垫至该第一焊接部上。
10.如权利要求1所述的半导体封装件，其特征在于，该第二导电组件是为第二金线。
11.如权利要求1或4或6所述的半导体封装件，其特征在于，该第二导电组件是电性连接该第二焊接部至该导电部上。
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CN102222655A (zh) * 2010-04-13 2011-10-19 鸿富锦精密工业（深圳）有限公司 芯片转接板
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