CN102437141B - 密节距小焊盘铜线键合单ic芯片封装件及其制备方法 - Google Patents

密节距小焊盘铜线键合单ic芯片封装件及其制备方法 Download PDF

Info

Publication number
CN102437141B
CN102437141B CN201110408681.1A CN201110408681A CN102437141B CN 102437141 B CN102437141 B CN 102437141B CN 201110408681 A CN201110408681 A CN 201110408681A CN 102437141 B CN102437141 B CN 102437141B
Authority
CN
China
Prior art keywords
pad
ball
welding
bronze medal
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110408681.1A
Other languages
English (en)
Other versions
CN102437141A (zh
Inventor
慕蔚
李习周
郭小伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
Original Assignee
Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianshui Huatian Technology Co Ltd, Huatian Technology Xian Co Ltd filed Critical Tianshui Huatian Technology Co Ltd
Priority to CN201110408681.1A priority Critical patent/CN102437141B/zh
Publication of CN102437141A publication Critical patent/CN102437141A/zh
Application granted granted Critical
Publication of CN102437141B publication Critical patent/CN102437141B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48481—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a ball bond, i.e. ball on pre-ball
    • H01L2224/48482—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a ball bond, i.e. ball on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48499—Material of the auxiliary connecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

密节距小焊盘铜线键合单IC芯片封装件，塑封体内设置引线框架载体和框架引线内引脚，引线框架载体上固接有IC芯片，IC芯片上多个焊盘与多个框架引线内引脚为一一对应，每个焊盘和相对应的框架引线内引脚通过键合线相连接，每列焊盘组中的焊盘上或间隔的焊盘上分别焊接有金球，金球上焊接有第一铜键合球，并在对应的内引脚上打一个月牙形的铜焊点，形成第一铜键合线；未焊接金球的焊盘上焊接有第二铜键合球，并在对应的内引脚上打一个月牙形的铜焊点，形成第二铜键合线，两列焊盘组中的金球交错设置。本发明封装件与制备方法避免了焊盘上产生弹坑、相邻焊点短路和容易碰伤前一根线而造成的塑封冲线开路的隐患。

Description

密节距小焊盘铜线键合单IC芯片封装件及其制备方法
技术领域
    本发明属于电子信息自动化元器件制造技术领域，涉及一种IC芯片封装件，具体说是一种密节距小焊盘铜线键合单IC芯片封装件，本发明还涉及该封装件的制备方法。
背景技术
    随着电子信息产业的高速发展，芯片制造业迈入了纳米时代，芯片制造的工艺尺寸从90nm缩小到45nm，再到30nm、13nm快速递进。芯片的几何尺寸也越来越小，由1.0mm×1.0mm到0.8mm×0.8mm、0.5mm×0.5mm、0.3mm×0.3mm，最小0.15mm×0.15mm，相应地，芯片制造中使用的焊盘节距也由120μm逐步缩小到100μm、70μm、60μm、50μm和45μm。划道也由100μm逐渐缩小到70μm、60μm、50μm和45μm。使得焊盘尺寸也由最初的100μm×100μm渐次缩小为70μm×70μm、55μm×55μm、最小为38μm×38μm。焊盘尺寸的变化给键合工艺带来了难题和巨大的挑战。
正常的球焊键合工艺中，焊球的直径大于/等于线径的2倍，小于线径的5倍为合格。一般金线焊球的直径可控制在2～2.3(倍) 线径，铜线焊球的直径可控制在2.5～ 3(倍) 线径。对于38μm×38μm的焊盘，相邻焊盘间距41μm～43μm，只能使用Φ15μm～Φ16μm的焊线，并且键合焊球的直径必须控制在37μm以内。那么金线无论Φ15μm（2.3×15=34.5＜37）或取上限16（16×2.3=36.8＜37）,均符合压焊要求。而铜线无论Φ15μm（取下限15×2.5=37.5＞37），还是16μm（取上限16×2.5=40＞37），都不符合压焊要求。并且从压焊质量检验的角度讲，相邻键合线间的空隙应等于2倍的焊线直径。实际上，去除线径，相邻焊线间空隙1.69～1.86倍线径，相邻两键合线间距也不能满足一般质量要求。但是，实践证明，随着焊线质量的提高、线径规格的增多，封装技术的发展和高密度封装形式及产品的增加，在保证塑封冲线率满足工艺要求的前提下，焊线与焊线间不短路，相邻引线间空隙大于1倍的线径也被行业公认可以满足焊线工艺要求。但对密节距小焊盘的键合而言，键合球的直径很难控制，稍不注意，键合球会超出焊盘，造成相邻焊点短路，导致产品报废。另外，由于线间距过小，打第二根线时会碰到前一根线，造成前一根线的损伤。所以说，节距≤43μm的密节距小焊盘（38μm×38μm）产品键合的最大难度是键合点焊球直径的控制和碰伤相邻焊线的问题。
发明内容
本发明为了解决现有节距≤43μm、38μm×38μm的密节距小焊盘IC芯片铜线键合中存在相邻焊点间短路和碰伤相邻焊线的问题，提供一种相邻焊点不易短路的密节距小焊盘铜线键合单IC芯片封装件，本发明的另一目的是提供一种上述封装件的制备方法，在键合过程中能够控制键合球的直径，并且能避免碰伤相邻焊线，实现单芯片键合封装。
本发明的技术问题采用下述技术方案解决：
一种密节距小焊盘铜线键合IC芯片封装件，包括塑封体，塑封体内设有引线框架载体和框架引线内引脚，引线框架载体的上面固接有IC芯片，所述IC芯片的上表面设置数个焊盘，所述数个焊盘平行设置成两列焊盘组， 分别为第一焊盘组和第二焊盘组，每个焊盘对应连接一框架引线内引脚；所述每列焊盘组中的每个焊盘上分别焊接一个金球，每个金球上焊接一个第一铜键合球，拱丝拉弧在对应内引脚上打一铜焊点，形成第一铜键合线。
所述每列焊盘组中间隔的焊盘上分别焊接有一个金球，所述第一焊盘组中的金球与第二焊盘组中的金球交错设置，每个金球上焊接一个第一铜键合球，每列焊盘组中未焊接金球的焊盘上直接焊接一个第二铜键合球，拱丝拉弧在对应内引脚上打一铜焊点，形成第二铜键合线。
所述每列焊盘组中相邻两焊盘之间留有空隙，焊盘的外形尺寸为 38μm×38μm，焊盘的节距为43μm。
所述第一铜键合球采用Φ15μm铜线制成，其直径为35μm～38μm。
所述金球的直径为30μm～36.8μm。
所述第二铜键合球采用Φ15μm铜线制成，其直径为34μm～37μm。
上述封装件按下述工艺步骤进行：
步骤1、减薄、划片：
常规方法将晶圆减薄至300μm并划片；
步骤2、上芯：
取引线框架载体将步骤1已减薄划片的IC芯片固接于引线框架载体上，采用N2气流量25~30ml/min烘烤3小时，烘烤温度150℃；
步骤3、压焊：在每个焊盘上进行压焊；
a）将金线轴固定于压焊台上，然后穿入金线；
 b）将引线框架载体预热至200℃～210℃后送到压焊台上，在焊盘上分别焊接金球；
c）将铜线轴固定于压焊台上，穿入铜线，将步骤b）中焊接有金球的引线框架载体预热至200℃～210℃后送到压焊台上，在每个金球上堆叠一个第一铜键合球，然后向上拱丝拉弧至与焊接有该金球的焊盘相对应的引线框架内引脚，并在该引线框架内引脚上打一铜焊点，形成第一铜键合线；
d）在两列焊盘组中未焊接金球的每个焊盘上分别用铜丝球焊形成第二铜键合球，拱丝拉弧至与该焊盘相对应的引线框架内引脚，并在该引线框架内引脚上打一铜焊点，形成第二铜键合线；
步骤4：采用常规方法对压焊后形成的半成品框架依次进行塑封、后固化、打印、冲切分离或切割分离（QFN/DFN），制成密节距小焊盘铜线键合IC芯片封装产品。
本发明封装件采用多重球焊方法，即在IC芯片焊盘上先植金球，并在金球上焊接铜键合球以及在其余的焊盘上直接焊接铜键合球的结构，避免了焊盘上产生弹坑和相邻焊点短路，既解决了密节距小焊盘高密度键合时容易碰伤前一根线而造成的塑封冲线开路的问题，又避免键合球径过大造成相邻焊点短路的难题，结构简单合理，能用于多引脚封装。可应用于多引脚封装和堆叠封装。同时，选用铜丝进行键合，其键合强度优于金线，从而减少了塑封冲线率，提高了产品质量，节约了焊线成本。
附图说明
图1为本发明每个芯片焊盘上植金球结构示意图；
图2为每个芯片焊盘上植金球平面示意图；
图3为间隔焊盘上植金球平面示意图；
图4为间隔焊盘上植金球剖面示意图；
图5为本发明载体外露示意图；
图6为本发明的芯片焊盘尺寸间距示意图。
具体实施方式
下面结合附图和实施例对本发明进行详细说明。
如图1所示，本发明提供一种节距b≤43μm、焊盘4(a×a)为38μm×38μm的密节距小焊盘IC芯片铜线键合封装件，引线框架载体1上是IC芯片3，引线框架载体1和IC芯片3通过粘片胶2固接，IC芯片3的上表面设置有多个焊盘4，该多个焊盘4组成平行设置的两列焊盘组，分别为第一焊盘组和第二焊盘组。每列焊盘组中相邻两焊盘4之间留有空隙，第一焊盘组中的焊盘4与第二焊盘组中的焊盘4错开，焊盘4的外形尺寸为 38μm×38μm，焊盘4的节距为43μm，相邻两焊盘4之间的空隙为3μm～5μm。本封装件每个焊盘4一一对应连接一个框架引线内引脚7，每个框架引线内引脚7上分别设置有铜键合点10。
本发明的第一种实施方式如图2、图4所示，每个焊盘4上分别先植金球5，金球5的直径为30μm～36.8μm，每个金球5上焊接一个第一铜键合球6，拱丝拉弧在对应内引脚7上打一铜焊点10，形成第一铜键合线9。上述各组件封装于塑封装体11内，构成了电路整体。塑封体11对IC芯片3、金球5、第一铜键合球6、第一铜键合线9起到保护作用。
本发明的第二种实施方式如图3、图5所示，每组焊盘组中间隔的焊盘4上分别焊接有一个金球5，金球5的直径为30μm～36.8μm，第一焊盘组中的金球5与第二焊盘组中的金球5交错设置，每个金球5上焊接一个第一铜键合球6，每列焊盘组中未焊接金球5的焊盘4上直接焊接一个第二铜键合球8，拱丝拉弧在对应内引脚7上打一个月牙形的键合点10，形成第二铜键合线14。第一铜键合线9和第二铜键合线14及在IC芯片焊盘上的焊点构成了电路的电源和信号通道。上述各组件封装于塑封装体11内，构成了电路整体。塑封体11对IC芯片3、金球5、第一铜键合球6和第二铜键合球8、第一铜键合线9和第二铜键合线14起到保护作用。
实施例1
制备封装件的工艺流程为减薄、划片、上芯、压焊、塑封、后固化、切筋、电镀、打印、成形分离和包装，其中除了上芯、压焊工序以外的其它工序均采用相关封装形式的常规方法，其上芯、压焊操作工艺过程为：
1、减薄、划片
采用封装通用减薄设备和工艺，将晶圆减薄到280μm并划片；
2、上芯
采用载体外露的eSOP、eMSOP、eTSSOP、e/TLQFP、QFN、DFN引线框架，将1已减薄划片的IC芯片3用粘片胶2固定在上述引线框架载体1上，上芯设备和工艺同相关封装形式常规产品生产；
3、烘烤
采用N2气流量25ml/min的防离层烘烤技术将引线框架载体烘烤3小时，烘烤温度150℃；
4、压焊
⑴ 在步骤1安装的IC芯片3的上表面平行设置两列焊盘组，该两列焊盘组分别由数量相同的焊盘4组成，且两列焊盘组中的各焊盘4之间互不接触，一列焊盘组中的焊盘4与另一列焊盘组中的焊盘4为错开，焊盘4的各条边的边长为38μm×38μm，焊盘4之间的节距为43μm，相邻两焊盘4之间的空隙为3μm；
⑵ 植金球
将直径16μm的金线轴固定于压焊台上，穿好金线后，将已粘IC芯片3的引线框架载体1自动传送到轨道上，通过轨道压板固定，预热至200℃后，在每列焊盘组的焊盘4上分别焊接直径30μm的金球5，打完金球的引线框架载体1传送到收料夹；
⑶ 叠铜球
在铜线压焊台上固定铜线轴，然后穿入直径为15μm的铜线，穿好线后，将已植金球5的引线框架载体1自动传送到轨道上，预热至210℃后传送到压焊夹具上，通过轨道压板进行固定，在每个金球5上堆叠一个直径为35μm的第一铜键合球6；
⑷ 拱丝打点
堆叠第一铜键合球6后，向上拱丝拉弧到与被植金球5的焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线9；
5、采用相关封装形式的常规方法对压焊后形成的器件进行塑封、后固化、打印和冲切分离或切割分离，制成密节距小焊盘铜线键合IC芯片封装产品。
实施例2
1、减薄、划片
采用封装通用减薄设备和工艺，将晶圆减薄到300μm并划片；
2、上芯
采用载体外露的eSOP、eMSOP、eTSSOP、e/TLQFP、QFN、DFN引线框架，将1已减薄划片的IC芯片3用导电胶固定在上述引线框架载体1上，上芯设备和工艺同相关封装形式常规产品生产；
3、烘烤
采用N2气流量30ml/min的防离层烘烤技术将引线框架载体烘烤3小时，烘烤温度150℃；
4、压焊
⑴ 在步骤1安装的IC芯片3的上表面平行设置两列焊盘组，该两列焊盘组分别由数量相同或不相同的焊盘4组成，且两列焊盘组中的各焊盘4之间互不接触，一列焊盘组中的焊盘4与另一列焊盘组中的焊盘4为错开，控制焊盘4的各条边a的边长为38μm×38μm，焊盘4之间的节距为43μm，相邻两焊盘4之间的空隙c为5μm，见图1；
⑵ 植金球
将直径15μm的金线轴固定于压焊台上，穿好线后，将已粘IC芯片3的引线框架载体1自动传送到轨道上，预热至210℃后传送到压焊台，用轨道压板进行固定，在每列焊盘组的焊盘4上隔行分别焊接直径36.8μm的金球5，控制一列焊盘组中焊接的金球5与另一列焊盘组中焊接的金球5交错设置；打完金球的引线框架载体1传送到收料夹；
⑶ 叠铜球
在铜线键合压焊台上固定铜线轴，然后穿入直径为15μm的铜线，将已植金球5的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在每个金球5上堆叠一个直径38μm的第一铜键合球6；
⑷ 拱丝打点
堆叠第一键键合球6后，向上拱丝拉弧到与被植金球5的焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第一铜键合线9；
（5） 不植（焊接）金球的焊盘直接铜线键合
在两列焊盘组中未植金球5的每个焊盘4上分别用直径为15μm的铜丝打直径为37μm的第二铜键合球8，然后，拱丝拉弧至与该焊盘4相对应的引线框架内引脚7，并在该引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14；
5、采用相关封装形式（如eSOP、eMSOP、eTSSOP、eLQFP、QFN、DFN）常规方法对压焊后形成的器件进行塑封、后固化、打印和冲切分离或切割分离，制成密节距小焊盘铜线键合IC芯片封装产品。
实施例3
1. 减薄、划片
采用相关封装形式减薄通用设备和工艺，将晶圆减薄250μm并划片；
2、上芯
上芯采用载体不外露的SOP、SSOP、MSOP、TSSOP、QFPL、QFP、QFN、DFN引线框架，将已减薄到时250μm划片好的IC芯片3用绝缘胶固定在上述引线框架载体1上，上芯设备和工艺同相关封装形式常规产品生产；
3. 压焊
⑴ 在步骤1安装的IC芯片3的上表面平行设置两列焊盘组，该两列焊盘组分别由数量相同的焊盘4组成，且两列焊盘组中的各焊盘4之间互不接触，一列焊盘组中的焊盘4与另一列焊盘组中的焊盘4为一一对应，如图1所示，控制焊盘4的各条边的边长为38μm×38μm，焊盘4之间的节距为50μm，相邻两焊盘4之间的空隙为5μm；
⑵ 植金球
将直径15μm的金线轴固定于压焊台上，穿好线后，将已粘IC芯片3的引线框架载体1自动传送到轨道上，由轨道板固定，预热至210℃后，在每列焊盘4上分别焊接金球5，控制一列焊盘组中焊接的金球5与另一列焊盘组中焊接的金球5交错设置，如图2 所示；打完金球5的引线框架载体1传送到收料夹。
⑶ 叠铜球
将已植金球的传递盒送到铜线键合台，在压焊台上固定直径为15μm的铜线轴，穿好线后，将已植金球5的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在每个金球5上堆叠一个第一铜键合球6；
⑷ 拱丝打点
堆叠第一键合球6后，向上拱丝拉弧到与被植金球5的焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第一铜键合线9；
⑸ 重复动作
依次类推直到打完所有焊点为止，并收料到传递盒。
4、采用相关封装形式（如SOP、MSOP、TSSOP、L/TQFP）常规方法对压焊后形成的器件进行塑封、后固化、打印和冲切分离或切割分离，制得密节距小焊盘铜线键合IC芯片封装产品。
实施例4
1. 减薄、划片
采用相关封装形式减薄通用设备和工艺，将晶圆减薄250μm并划片；
2、上芯
采用载体不外露的SOP、SSOP、MSOP、TSSOP、QFPL、QFP、QFN、DFN引线框架，将已减薄到时250μm划片好的IC芯片3用粘片胶（导电胶或绝缘胶）4固定在上述引线框架载体1上，上芯设备和工艺同相关封装形式常规产品生产；
3. 压焊
⑴ 在步骤1安装的IC芯片3的上表面平行设置两列焊盘组，该两列焊盘组分别由数量相同的焊盘4组成，且两列焊盘组中的各焊盘4之间互不接触，一列焊盘组中的焊盘4与另一列焊盘组中的焊盘4为一一对应，如图1所示，控制焊盘4的各条边a的边长为38μm×38μm，焊盘4之间的节距b为50μm，相邻两焊盘4之间的空隙c为3μm～5μm。
⑵ 植金球
将直径15μm的金线轴固定于压焊台上，穿好线后，将已粘IC芯片3的引线框架载体1自动传送到轨道上，由轨道板固定，预热至210℃后，在每列焊盘组间隔的焊盘4上分别焊接金球5，控制一列焊盘组中焊接的金球5与另一列焊盘组中焊接的金球5交错设置，如图3所示；打完金球5的引线框架载体1传送到传递盒。
⑶ 叠铜球
将已植金球的传递盒送到铜线键合台，在压焊台上固定直径为15μm的铜线轴，穿好线后，将已植金球5的引线框架载体1自动传送到轨道上，预热至200℃后传送到压焊夹具上，通过轨道压板进行固定，在每个金球5上堆叠一个第一键合球6；
⑷ 拱丝打点
堆叠第一键合球6后，向上拱丝拉弧到与被植金球5的焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第一铜键合线9；
⑸ 不植金球的焊盘直接铜线键合
接着在两列焊盘组中未植金球5的每个焊盘4上直接打直径34μm的第二铜键合球8，并拱丝拉弧到与该焊盘4相对应的引线框架内引脚7上打一个月牙形的铜焊点10，形成第二铜键合线14；
（6）重复动作
依次类推直到打完所有焊点为止，并收料到传递盒。
3、采用相关封装形式（如SOP、MSOP、TSSOP、L/TQFP）常规方法对压焊后形成的器件进行塑封、后固化、打印和冲切分离或切割分离，制得密节距小焊盘铜线键合IC芯片封装产品。
    虽然结合优选实施例已经示出并描述了本发明，本领域技术人员可以理解，在不违背所附权利要求限定的本发明的精神和范围的前提下可以进行修改和变换。

Claims (7)

1.一种密节距小焊盘铜线键合单IC芯片封装件，包括塑封体（11），塑封体（11）内设有引线框架载体（1）和框架引线内引脚（7），引线框架载体（1）的上面固接有IC芯片（3），其特征在于：所述IC芯片（3）的上表面设置数个焊盘（4），所述数个焊盘（4）平行设置成两列焊盘组，分别为第一焊盘组和第二焊盘组，所述每列焊盘组中的每个焊盘（4）对应连接一框架引线内引脚（7），每个焊盘（4）上分别焊接一个金球（5），每个金球（5）上焊接一个第一铜键合球（6），拱丝拉弧在对应内引脚（7）上打一铜焊点（10），形成第一铜键合线(9)。
2.如权利要求1所述的密节距小焊盘铜线键合单IC芯片封装件，其特征在于所述第一焊盘组和第二焊盘组中间隔的焊盘（4）上分别焊接有一个金球（5），所述第一焊盘组中的金球（5）与第二焊盘组中的金球（5）交错设置，每个金球（5）上焊接一个第一铜键合球（6），每列焊盘组中未焊接金球（5）的焊盘（4）上直接焊接一个第二铜键合球（8），拱丝拉弧在对应内引脚（7）上打一铜焊点（10），形成第二铜键合线(14)。
3.如权利要求1所述的密节距小焊盘铜线键合单IC芯片封装件，其特征在于所述每列焊盘组中相邻两焊盘（4）之间留有空隙，焊盘（4）的外形尺寸为 38μm×38μm，焊盘（4）的节距为43μm。
4.如权利要求1所述的密节距小焊盘铜线键合单IC芯片封装件，其特征在于所述第一铜键合球（6）采用Φ15μm铜线制成，第一铜键合球（6）直径为35μm～38μm。
5.如权利要求1所述的密节距小焊盘铜线键合单IC芯片封装件，其特征在于所述金球（5）的直径为30μm～36.8μm。
6.如权利要求1或2所述的密节距小焊盘单IC芯片封装件，其特征在于所述第二铜键合球（8）采用Φ15μm铜线制成，第二铜键合球（8）直径为34μm～37μm。
7.一种如权利要求1或2所述密节距小焊盘单IC芯片封装件的制备方法，工艺流程为减薄、划片、上芯、压焊、塑封、后固化、切筋、电镀、打印、成形分离和包装，其中除上芯、压焊工序以外，其它工序均采用相关封装形式的常规方法，其特征在于：所述工艺过程为：
步骤1、减薄、划片：
常规方法将晶圆减薄至250～300μm并划片；
步骤2、上芯：
取引线框架载体将步骤1已减薄划片的IC芯片固接于引线框架载体上，采用N2气流量25~30ml/min烘烤3小时，烘烤温度150℃；
步骤3、压焊：
在焊盘（4）上进行压焊：
a）将金线轴固定于压焊台上，然后穿入金线；
b）将引线框架载体预热至200℃～210℃后送到压焊台上，在焊盘上分别焊接金球；
c）将铜线轴固定于压焊台上，穿入铜线，将步骤b）中焊接有金球的引线框架载体预热至200℃～210℃后送到压焊台上，在每个金球上堆叠一个第一铜键合球，然后向上拱丝拉弧至与焊接有该金球的焊盘相对应的引线框架内引脚，并在该引线框架内引脚上打一铜焊点，形成第一铜键合线；
d）在两列焊盘组中未焊接金球的每个焊盘上分别用铜丝球焊形成第二铜键合球，拱丝拉弧至与该焊盘相对应的引线框架内引脚，并在该引线框架内引脚上打一铜焊点，形成第二铜键合线；
步骤4：对压焊后形成的半成品框架依次进行塑封、后固化、打印、冲切分离或切割分离，制成密节距小焊盘铜线键合IC芯片封装产品。
CN201110408681.1A 2011-12-09 2011-12-09 密节距小焊盘铜线键合单ic芯片封装件及其制备方法 Active CN102437141B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110408681.1A CN102437141B (zh) 2011-12-09 2011-12-09 密节距小焊盘铜线键合单ic芯片封装件及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110408681.1A CN102437141B (zh) 2011-12-09 2011-12-09 密节距小焊盘铜线键合单ic芯片封装件及其制备方法

Publications (2)

Publication Number Publication Date
CN102437141A CN102437141A (zh) 2012-05-02
CN102437141B true CN102437141B (zh) 2015-04-01

Family

ID=45985124

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110408681.1A Active CN102437141B (zh) 2011-12-09 2011-12-09 密节距小焊盘铜线键合单ic芯片封装件及其制备方法

Country Status (1)

Country Link
CN (1) CN102437141B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035546B (zh) * 2012-12-18 2018-01-16 可天士半导体（沈阳）有限公司 一种小尺寸键合点双线键合方法
US9974175B2 (en) 2013-04-29 2018-05-15 Samsung Display Co., Ltd. Electronic component, electric device including the same, and bonding method thereof
US11457531B2 (en) 2013-04-29 2022-09-27 Samsung Display Co., Ltd. Electronic component, electric device including the same, and bonding method thereof
CN103559967B (zh) * 2013-11-25 2017-03-29 杭州士兰集成电路有限公司 贴片式无源电子元件安装结构和方法
EP3093705B1 (en) * 2014-04-10 2017-12-20 Samsung Display Co., Ltd. Electronic component
CN106252246B (zh) * 2016-08-30 2018-08-24 长电科技（滁州）有限公司 一种锡球包裹的焊丝键合工艺及芯片封装方法
CN106783780A (zh) * 2016-12-21 2017-05-31 长电科技（宿迁）有限公司 一种半导体封装结构及其工艺方法
CN107492534A (zh) * 2017-08-03 2017-12-19 中南大学 细节距单ic芯片封装件及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101599483A (zh) * 2008-06-04 2009-12-09 奇景光电股份有限公司 堆叠式裸芯封装
CN101626008A (zh) * 2009-05-11 2010-01-13 天水华天科技股份有限公司 一种铜线键合ic芯片封装件的生产方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074542B (zh) * 2010-12-15 2013-04-17 天水华天科技股份有限公司 一种双扁平短引脚ic芯片封装件及其生产方法
CN202339915U (zh) * 2011-12-09 2012-07-18 天水华天科技股份有限公司 密节距小焊盘铜线键合单ic芯片封装件

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101599483A (zh) * 2008-06-04 2009-12-09 奇景光电股份有限公司 堆叠式裸芯封装
CN101626008A (zh) * 2009-05-11 2010-01-13 天水华天科技股份有限公司 一种铜线键合ic芯片封装件的生产方法

Also Published As

Publication number Publication date
CN102437141A (zh) 2012-05-02

Similar Documents

Publication Publication Date Title
CN102437141B (zh) 密节距小焊盘铜线键合单ic芯片封装件及其制备方法
CN102437147B (zh) 密节距小焊盘铜线键合双ic芯片堆叠封装件及其制备方法
US10515934B2 (en) Semiconductor device
CN102522383B (zh) 一种中心布线双圈排列ic芯片堆叠封装件及其生产方法
US20110084374A1 (en) Semiconductor package with sectioned bonding wire scheme
CN101626008A (zh) 一种铜线键合ic芯片封装件的生产方法
WO2012068763A1 (zh) 一种无载体栅格阵列ic芯片封装件及其制备方法
CN102522391B (zh) 一种具有接地环的e/LQFP堆叠封装件及其生产方法
CN102522392B (zh) 一种具有接地环的e/LQFP平面封装件及其生产方法
CN105826209A (zh) 一种封装结构及其制造方法
EP2603929A2 (en) Stitch bump stacking design for overall package size reduction for multiple stack
CN202977380U (zh) 一种qfn，dfn集成电路封装用线条式压焊夹具
CN114050136A (zh) 一种芯片焊盘植球整平及二次焊接的方法
US20030197267A1 (en) Ultrathin leadframe BGA circuit package
US20080246129A1 (en) Method of manufacturing semiconductor device and semiconductor device
CN202339915U (zh) 密节距小焊盘铜线键合单ic芯片封装件
CN210142645U (zh) 一种适用于双向tvs芯片的封装结构
CN106409702A (zh) 一种多芯片堆叠封装结构及其制作方法
CN102543931A (zh) 中心布线双圈排列单ic芯片封装件及其制备方法
CN107492534A (zh) 细节距单ic芯片封装件及其制备方法
CN202339914U (zh) 密节距小焊盘铜线键合双ic芯片堆叠封装件
CN202394966U (zh) 一种具有接地环的e/LQFP堆叠封装件
CN107845600A (zh) 一种键合式晶圆级封装结构及其工艺流程
CN202394965U (zh) 一种具有接地环的e/LQFP平面封装件
CN111885849A (zh) 一种qfp封装芯片焊接方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant