CN104752338B - 用于半导体器件的互连结构 - Google Patents

用于半导体器件的互连结构 Download PDF

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Publication number
CN104752338B
CN104752338B CN201410843919.7A CN201410843919A CN104752338B CN 104752338 B CN104752338 B CN 104752338B CN 201410843919 A CN201410843919 A CN 201410843919A CN 104752338 B CN104752338 B CN 104752338B
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dielectric layer
layer
conductive material
density single
density
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CN104752338A (zh
Inventor
郭涵馨
柯忠祁
杨能杰
黄富明
蔡及铭
陈亮光
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种互连件和形成用于半导体器件的互连件的方法。通过处理介电层的上表面以产生高密度层来形成互连件。例如，处理可以包括使用六甲基二硅氮烷(HMDS)、三甲基硅烷基二乙胺(TMSDEA)或乙酸三甲基硅酯(OTMSA)生成高密度单层。处理之后，可以图案化介电层以生成随后用导电材料填充的开口。例如，可以使用化学机械抛光去除过量的导电材料。本发明涉及用于半导体器件的互连结构。

Description

用于半导体器件的互连结构
技术领域
本发明涉及用于半导体器件的互连结构。
背景技术
在集成电路领域中，用于形成互连结构(包括金属线和通孔)的常用方法被称为“镶嵌”。通常，这种方法包括在介电层形成开口，其分离垂直间隔开的金属化层。该开口通常使用光刻和蚀刻技术形成。开口形成后，用铜或铜合金填充该开口。然后通过化学机械抛光(CMP)去除介电层的表面上的过量的铜。剩余的铜或铜合金形成通孔和/或金属线。
因为铜的低电阻率而被常用于镶嵌结构中。典型地，互连结构由多个金属化层形成，每个金属化层均包括多条铜线。位于不同金属化层中的铜线通过通孔互连。虽然铜由于其电特性通常是优选的，但是可以使用其他材料。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种形成集成电路结构的方法，所述方法包括：提供具有介电层的衬底，所述介电层形成在所述衬底上；处理所述介电层的表面以形成沿着所述介电层的表面比所述介电层具有更高密度的层；图案化所述介电层以形成开口；以及在所述介电层中的所述开口中形成导电材料。
在上述方法中，处理所述表面在所述介电层上方生成高密度单层。
在上述方法中，处理所述表面包括利用六甲基二硅氮烷(HMDS)处理所述介电层的表面。
在上述方法中，利用HMDS处理包括利用HMDS蒸气处理。
在上述方法中，处理所述表面包括利用三甲基硅烷基二乙胺(TMSDEA)处理所述介电层的表面。
在上述方法中，利用TMSDEA处理包括将所述介电层浸在稀释的TMSDEA溶液中。
在上述方法中，处理所述表面包括利用乙酸三甲基硅酯(OTMSA)处理所述介电层的表面。
在上述方法中，利用OTMSA处理包括将所述介电层浸在稀释的OTMSA溶液中。
在上述方法中，还包括使用化学机械抛光(CMP)工艺从所述介电层的表面去除过量的导电材料。
根据本发明的另一方面，还提供了一种形成集成电路结构的方法，所述方法包括：提供具有介电层的衬底，所述介电层形成在所述衬底上；在所述介电层上方形成高密度单层，所述高密度单层比所述介电层具有更高的密度；图案化所述介电层和所述高密度单层以形成一个或多个开口；用导电材料填充所述开口，所述导电材料在所述高密度单层的上表面上方延伸；以及去除在所述高密度单层的上表面上方延伸的所述导电材料的至少部分。
在上述方法中，形成所述高密度单层包含用六甲基二硅氮烷(HMDS)处理所述介电层的表面。
在上述方法中，形成所述高密度单层包括利用三甲基硅烷基二乙胺(TMSDEA)处理所述介电层的表面。
在上述方法中，形成所述高密度单层包括利用乙酸三甲基硅酯(OTMSA)处理所述介电层的表面。
在上述方法中，所述高密度单层包括Si(CH3)3。
根据本发明的又一方面，还提供了一种集成电路结构，包括：具有介电层的衬底，所述介电层形成在所述衬底上；以及高密度单层,位于所述介电层上方。
在上述集成电路结构中，所述高密度单层包括以Si(CH3)3终止的介电层。
在上述集成电路结构中，所述介电层由低k材料形成。
在上述集成电路结构中，所述介电层由超低k材料形成。
在上述集成电路结构中，还包括延伸穿过所述高密度单层并且延伸至所述介电层内的导电线。
附图说明
为更完全地理解本发明以及其优势，现在将结合附图进行的以下描述作为参考，其中：
图1至图4示出了根据实施例的在制造半导体器件中的各个中间阶段；以及
图5是示出根据实施例的形成半导体器件的方法的流程图。
具体实施方式
下面详细地讨论了本发明的实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的适用的发明概念。讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，并且不限制本发明的范围。
提供了用于在集成电路的金属化层中形成金属部件的方法。示出本发明的制造实施例的中间阶段。贯穿本发明的各个视图和说明性实施例，相同的参考标号用于表示相同的元件。
图1至4示出了根据实施例的形成半导体器件的方法的各个中间阶段。首先参照图1，示出了晶圆100，晶圆100具有在其上形成的第一介电层102。晶圆100可包括位于第一介电层102下面的衬底(未明确示出)，并且可以包括，例如，掺杂或未掺杂的块状硅，或绝缘体上半导体(SOI)衬底的有源层。一般地，SOI衬底包括半导体材料层，诸如形成于绝缘层上的硅。该绝缘层可以是，例如，埋氧(BOX)层或氧化硅层。在衬底上提供绝缘层，典型地为硅或玻璃衬底。也可以使用诸如多层衬底或梯度衬底的其他衬底。
在实施例中，电路形成在衬底上，并且可以是适合于特定应用的任何类型的电路。在实施例中，该电路包括形成在衬底上的电器件，一个或多个介电层位于电器件上面。诸如那些本文所讨论的，可以在上面的介电层之间形成金属层以在电器件之间路由电信号。电器件也可以形成在一个或多个介电层之间。
例如，该电路可包括相互连以执行一种或多种功能的各种N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。功能可以包括存储结构、处理结构、传感器、放大器、功率分配、输入/输出电路等的功能。本领域的普通技术人员将理解，所提供的上述实例仅用于说明目的，以进一步解释一些说明性实施例的应用，并且不意味着以任何方式限制本发明。只要适合用于给定的应用，可以使用其他电路。
第一介电层102可以通过诸如旋压、化学汽相沉积(CVD)和等离子体增强CVD(PECVD)的任何合适的方法由例如低K介电材料(具有比二氧化硅的介电常数更低的介电常数的材料)来形成，诸如氮氧化硅、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合物、它们的组合等。也可以使用其他材料，诸如超低k材料(例如，具有小于约2.9的介电常数)，诸如k＝2.5-2.6。提供这些材料和工艺作为实例，可以使用其他材料和工艺。
也在图1中示出了在第一介电层102中形成的导电元件104。例如，可以通过使用光刻技术在第一介电层102中产生开口来形成导电元件104。一般地，光刻技术包括施加光刻胶材料(未示出)和根据期望的图案曝光该光刻胶材料。然后显影光刻胶材料以去除光刻胶材料的部分，从而根据期望的图案暴露下面的材料。剩余的光刻胶材料保护下面的材料免受后续处理步骤的影响，诸如为了在第一介电层102中形成开口(将在开口中形成导电元件104)而实施的蚀刻。蚀刻工艺可以是湿或干、各向异性或各向同性的蚀刻工艺，诸如各向异性干蚀刻工艺。在第一介电层102中形成开口之后，可以沉积导电材料以填充开口。导电元件104可以包括金属、元素金属、过渡金属等，诸如铜互连件。此外，导电元件104可以包括一个或多个阻挡/粘附层。
可选地，根据实施例，第一介电层102和导电元件104上方是蚀刻停止层(ESL)106。一般地，当形成通孔和/或接触件时，蚀刻停止层提供了停止蚀刻工艺的机制。蚀刻停止层由与相邻的层(例如，下面的第一介电层102或衬底)具有不同的蚀刻选择性的介电材料形成。在实施例中，可以由SiN、SiCN、SiCO、CN、及它们的组合等通过CVD或PECVD技术沉积来形成蚀刻停止层。
根据实施例，ESL 106上方是第二介电层108。如下面更详细的讨论，例如，第二介电层108是随后将被图案化以形成导电线和/或通孔的层。例如，可以图案化第二介电层108以形成延伸到导电元件104的通孔和形成导电线以互连各个电元件。
第二介电层108可以使用与用于形成第一介电层102的类似的工艺和类似的材料来形成；然而，可以使用不同的材料和工艺。此外，第一介电层102可以由与用于形成第二介电层108的材料相同或不同的材料形成。
应当注意的是，示出第一介电层102和导电元件104用于说明目的。在其他实施例中，第一介电层102可以用具有或不具有ESL 106的半导体衬底代替。例如，在另一实施例中，第二介电层108(要被图案化的层)是形成在衬底(其上形成有电器件)上方的层间介电层。在本实施例中，例如，可选的ESL 106可以是在晶体管(形成在衬底上)上方形成的氮化硅接触蚀刻停止层/应力层。随后图案化第二介电层108以形成至电器件的接触件，诸如至晶体管的源极或漏极接触件。
在实施例中，对第二介电层108的暴露表面实施工艺以产生疏水性表面，或降低该表面的亲水性。图1示出了在第二介电层108上方形成高密度单层109的实施例。例如，高密度单层109可以使用六甲基二硅氮烷(HMDS)，三甲基硅烷基二乙胺(TMSDEA)或乙酸三甲基硅酯(OTMSA)来形成。高密度单层109表现出比下面的第二介电层108的密度更高的密度。一般地，低k介电材料具有约0.9g/cm3至约1.4g/cm3的密度。例如，如果第二介电层108由具有密度约1.0g/cm3的材料形成，则高密度单层109具有大于1.0g/cm3的密度。
在实施例中，可以通过将晶圆放置在工艺室中和将第二介电层108暴露于90℃或更高(例如，从约90℃至约180℃)的温度下的HMDS蒸气，使用HMDS来处理第二介电层108，并且工艺持续时间为从约20分钟至约40分钟，诸如约30分钟。在HMDS蒸气可以是纯HMDS或用甲苯、苯等稀释以在约10mmHg至30mm Hg的分压下得到的约5％至约10％浓度的HMDS。工艺室还可以具有低浓度的氧气，诸如约1毫托的分压。浸在TMSDEA溶液之后，也可以实施清洁程序，诸如去离子水冲洗、异丙醇(IPA)冲洗、丙酮冲洗等以去除未反应的部分。
在另一实施例中，可以通过将晶圆浸在90℃或更高(例如，从约90℃至约180℃)的温度下的稀释的TMSDEA溶液浴中，使用TMSDEA来处理第二介电层108，并且工艺持续时间为从约20分钟至约40分钟，诸如约30分钟。工艺室还可以具有低O2浓度，诸如约1毫托的分压。浸在TMSDEA溶液之后，也可以实施清洁程序，诸如去离子水冲洗、异丙醇(IPA)冲洗、丙酮冲洗等以去除未反应的部分。
在又一个实施例中，可以通过将晶圆浸在90℃或更高(例如，从约90℃至约180℃)的温度下的在稀释的OTMSA溶液浴中，使用OTMSA来处理第二介电层，并且工艺持续时间为从约20分钟至约40分钟，诸如约30分钟。工艺室还可以具有低O2浓度，诸如约1毫托的分压。浸没在OTMSA溶液之后，也可以实施清洁程序，诸如去离子水冲洗、异丙醇(IPA)冲洗、丙酮冲洗等以去除未反应的部分。
在实施例中，终止OH基团被Si(CH3)3基团取代，从而产生高密度单层。随后的CMP工艺将频繁地导致Cu2+/Cu+残留在下面的层的表面上，从而引起时间相关电介质击穿(TDDB)和击穿电压(VBD)的问题。在较小的技术节点上这是特别的问题，诸如在20nm和更低的技术节点处的那些问题，其中，互连件之间的距离(例如，互连节距尺寸)缩小。
图1还示出了将在随后的蚀刻工艺中使用的图案化的掩模110。在实施例中，图案化的掩模110包括已经沉积在第二介电层108上方的光刻胶材料。如图1所示，一旦已经沉积光刻胶材料，则曝光和显影光刻胶材料以暴露下面的层的表面。
可以使用硬掩模层112以在随后的蚀刻工艺中提供帮助。一般地，硬掩模层112由与将被蚀刻的下层材料相比较而言表现低蚀刻速率的材料形成。例如，如果将被图案化的第二介电层108由氧化硅制成，则硬掩模层112可以由例如氮化硅形成。在这种情况下，硬掩模层112的氮化硅将具有比第二介电层108的氧化硅更低的蚀刻速率，从而允许硬掩模层112用作用于蚀刻第二介电层108的掩模。也应当注意的是，硬掩模层112可以包括多个层。硬掩模层112具有足够的厚度以在基于材料和蚀刻剂的蚀刻工艺期间提供保护。在实施例中，硬掩模层112形成为介于约200和约600之间的厚度。
可选地，抗反射涂(ARC)层114可以形成在高密度层109上方以在随后的光刻工艺中提供帮助以图案化上面的层，诸如图案化的掩模110。在随后的光刻工艺中ARC层114防止辐射反射(reflect off)下面的层并干涉曝光工艺。这种干涉可以提高光刻工艺的临界尺寸。该ARC层114可以包括SiON、聚合物等或它们的组合，并且可以通过CVD、旋涂工艺等或它们的组合来形成。ARC层114具有足够的厚度以提供基于材料和波长的充分的抗反射特性。在实施例中，该ARC层114形成为介于约200到约1000之间的厚度。
现在参考图2，示出了根据实施例的在用于图案化第二介电层108的一个或多个图案化步骤之后的晶圆100。图案化的掩模110(见图1)的图案被转印到下面的层。提供在本文中示出的图案仅用于说明目的。图案化可以包括线、通孔、线和通孔或其他部件的形成，并且可以包括诸如先通孔(via-first)图案化和/或先沟槽图案化的双镶嵌图案化技术。本文中所描述的技术也可以利用双图案化技术。一些图案化技术(诸如双镶嵌和双图案化技术)利用多个光刻胶层。
以举例的方式，图2示出了在第二介电层108中形成的沟槽开口230和通孔开口232。在随后的处理中，将用导电材料填充沟槽开口230和通孔开口232。浅沟槽开口230将形成导电线并且通孔开口232将形成导电通孔以互连金属化层。
由于蚀刻步骤，可以消耗掉图案化的掩模110和/或硬掩模层112和/或ARC层114(见图1)的部分或整体。图2示出硬掩模层112的部分保留的实施例。可选地，可以去除图案化的掩模110和/或硬掩模层112的剩余部分。
图3示出了根据实施例的由导电材料330填充沟槽开口230和通孔开口232(见图2)。导电材料330可以通过CVD、电镀、化学镀、ALD、PVD来沉积，并且可以由铜形形成，但是可以可选地利用其他合适的材料，诸如铝、钨、氮化钨、钌、银、金、铑、钼、镍、钴、镉、锌、它们的合金、它们的组合等。导电材料330可沉积到沟槽开口230内和通孔开口232内并且可以继续沉积直到导电材料330填充沟槽开口230和通孔开口232并且延伸到硬掩模层112(如果存在的话)之上。
可选地，在形成导电材料330之前可沿着沟槽开口230和通孔开口232的侧壁形成一个或多个阻挡/粘附层(未示出)。在实施例中，诸如使用铜导电材料的那些，阻挡层可以是满足需要地限制铜扩散到周围的介电材料内。在实施例中，阻挡层可以由一层或多层氮化钛、钛、钽、氮化钽、氮化钨、钌、铑、铂、其他贵金属、其他难熔金属、它们的氮化物形成、它们的组合等来形成。阻挡层可通过化学汽相沉积来形成，但是也可以可选地使用诸如PVD或ALD的其他技术。
图4示出了根据实施例的导电材料330的过量部分的去除。在实施例中，使用诸如化学机械抛光工艺(CMP)的平坦化工艺去除形成在硬掩模层112上方的过量的导电材料330(和任何可选的阻挡层/粘附层)。在此平坦化工艺期间，也可以去除ARC层114的剩余部分。
此后，可以实施额外的工艺以完成制造。例如，图4示出了形成在高密度单层109上方的另一介电层420。例如，介电层420可以是用于后续的蚀刻工艺的蚀刻停止层、用于上面的金属化层的介电层、钝化层等。
如以上所讨论的，高密度单层109使得第二介电层108的表面具有疏水性，并且疏水性能减少或消除残留在下面的第二介电层108层的表面上的Cu2+/Cu+。因此，可以减少与TDDB和VBD相关的问题，尤其是在较小的技术节点，诸如在20纳米和更低的那些节点。
图5示出了根据实施例的用于形成互连件的方法的步骤。该方法开始于步骤502，其中，提供衬底，衬底具有形成其上的将被图案化的介电层。例如，将被图案化的层可以是介电层，诸如用于半导体器件的金属化层的介电层。在步骤504中，处理介电层的表面以使介电层是疏水性的，或较小亲水性的。处理可以包括形成诸如上述参考图1描述的高密度单层。
接下来，在步骤506中，如在上面参考图2中所讨论的，例如，通过使用光刻技术来图案化介电层，从而在介电层中产生开口。如在上面参考图1中所讨论的，图案化可以包括形成ARC层和硬掩模层。如在步骤508所示和如在上面参考图3所讨论的，一旦图案化，用导电材料填充开口。
在步骤510中，如在上面参考图4所讨论的，可以去除过量的导电材料，。
在实施例中，提供了一种形成集成电路结构的方法。该方法包括提供具有介电层的衬底。处理介电层的表面以形成高密度层。图案化介电层以形成填充有导电材料的开口。
在另一实施例中，提供了另一种形成集成电路结构的方法。该方法包括提供具有介电层的衬底和在介电层上方形成高密度单层。图案化介电层和高密度单层以形成一个或多个填充有导电材料的开口。从高密度单层的表面去除过量的导电材料。
在又一实施例中，提供了一种集成电路结构。该结构包括其上形成有介电层的衬底和位于介电层上方的高密度单层。
尽管已经详细地描述了本发明及其优势，但应该理解，在不背离所附权利要求限定的本发明主旨和范围的情况下，本文可以做出各种不同的改变、替换和更改。而且，本申请的范围并不旨在限制于说明书中描述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域普通技术人员将容易从本发明的公开理解，根据本发明，可以利用现有的或今后开发的实施与本文所描述的相应实施例基本相同的功能或实现基本相同的结果的工艺、机器、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在将这样的工艺、机器、制造、物质组成、工具、方法或步骤包括在它们的范围内。

Claims (16)

1.一种形成集成电路结构的方法，所述方法包括：
提供具有介电层的衬底，所述介电层形成在所述衬底上；
处理所述介电层的表面以形成沿着所述介电层的表面比所述介电层具有更高密度的层，比所述介电层具有更高密度的层包括终止Si(CH3)3基团；
图案化所述介电层以形成开口；
在所述介电层中的所述开口中形成导电材料；以及
在所述导电材料和比所述介电层具有更高密度的层上方形成与所述导电材料和比所述介电层具有更高密度的层直接接触的另一介电层；
其中，在形成所述导电材料之后，所述开口内不含比所述介电层具有更高密度的层。
2.根据权利要求1所述的方法，其中，处理所述表面在所述介电层上方生成高密度单层。
3.根据权利要求1所述的方法，其中，处理所述表面包括利用六甲基二硅氮烷(HMDS)处理所述介电层的表面。
4.根据权利要求3所述的方法，其中，利用六甲基二硅氮烷处理包括利用六甲基二硅氮烷蒸气处理。
5.根据权利要求1所述的方法，其中，处理所述表面包括利用三甲基硅烷基二乙胺(TMSDEA)处理所述介电层的表面。
6.根据权利要求5所述的方法，其中，利用三甲基硅烷基二乙胺处理包括将所述介电层浸在稀释的三甲基硅烷基二乙胺溶液中。
7.根据权利要求1所述的方法，其中，处理所述表面包括利用乙酸三甲基硅酯(OTMSA)处理所述介电层的表面。
8.根据权利要求7所述的方法，其中，利用乙酸三甲基硅酯处理包括将所述介电层浸在稀释的乙酸三甲基硅酯溶液中。
9.根据权利要求1所述的方法，还包括使用化学机械抛光(CMP)工艺从所述介电层的表面去除过量的导电材料。
10.一种形成集成电路结构的方法，所述方法包括：
提供具有介电层的衬底，所述介电层形成在所述衬底上；
在所述介电层上方形成高密度单层，所述高密度单层比所述介电层具有更高的密度并且包括终止Si(CH3)3基团；
图案化所述介电层和所述高密度单层以形成一个或多个开口；
用导电材料填充所述开口，所述导电材料在所述高密度单层的上表面上方延伸；
去除在所述高密度单层的上表面上方延伸的所述导电材料的至少部分；以及
在所述导电材料和所述高密度单层上方形成与所述导电材料和所述高密度单层直接接触的另一介电层；
其中，在填充所述开口之后，所述开口内不含所述高密度单层。
11.根据权利要求10所述的方法，其中，形成所述高密度单层包含用六甲基二硅氮烷(HMDS)处理所述介电层的表面。
12.根据权利要求10所述的方法，其中，形成所述高密度单层包括利用三甲基硅烷基二乙胺(TMSDEA)处理所述介电层的表面。
13.根据权利要求10所述的方法，其中，形成所述高密度单层包括利用乙酸三甲基硅酯(OTMSA)处理所述介电层的表面。
14.一种集成电路结构，包括：
具有介电层的衬底，所述介电层形成在所述衬底上；
高密度单层，位于所述介电层上方，所述高密度单层比所述介电层具有更高的密度并且包括以Si(CH3)3终止的介电层；
导电线，形成在延伸穿过所述高密度单层并且延伸至所述介电层内的开口内；以及
另一介电层，位于所述导电线和所述高密度单层上方且与所述导电线和所述高密度单层直接接触；
其中，所述开口内不含所述高密度单层。
15.根据权利要求14所述的集成电路结构，其中，所述介电层由低k材料形成。
16.根据权利要求14所述的集成电路结构，其中，所述介电层由超低k材料形成。
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