CN104508811B - Led封装和制造方法 - Google Patents
Led封装和制造方法 Download PDFInfo
- Publication number
- CN104508811B CN104508811B CN201380041899.5A CN201380041899A CN104508811B CN 104508811 B CN104508811 B CN 104508811B CN 201380041899 A CN201380041899 A CN 201380041899A CN 104508811 B CN104508811 B CN 104508811B
- Authority
- CN
- China
- Prior art keywords
- led
- semiconductor substrate
- switching transistor
- connection
- encapsulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 238000005538 encapsulation Methods 0.000 claims abstract description 54
- 239000004065 semiconductor Substances 0.000 claims description 46
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000004224 protection Effects 0.000 description 4
- ALFHIHDQSYXSGP-UHFFFAOYSA-N 1,2-dichloro-3-(2,4-dichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC=C1C1=CC=CC(Cl)=C1Cl ALFHIHDQSYXSGP-UHFFFAOYSA-N 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- IHIDFKLAWYPTKB-UHFFFAOYSA-N 1,3-dichloro-2-(4-chlorophenyl)benzene Chemical compound C1=CC(Cl)=CC=C1C1=C(Cl)C=CC=C1Cl IHIDFKLAWYPTKB-UHFFFAOYSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/40—Details of LED load circuits
- H05B45/44—Details of LED load circuits with an active control inside an LED matrix
- H05B45/48—Details of LED load circuits with an active control inside an LED matrix having LEDs organised in strings and incorporating parallel shunting devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13244—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/13395—Base material with a principal constituent of the material being a gas not provided for in groups H01L2224/133 - H01L2224/13391
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
一种LED封装(40)和制造方法,其中该封装具有接合在一起的LED衬底(50)和电路衬底(54),其中LED在集成电路上方,并且在LED和对应的集成电路之间具有电连接。该封装仅在带有提供LED衬底和电路衬底之间的连接的通孔(58a、58b)的一个面上具有封装端子(56a、56b)。
Description
技术领域
本发明涉及LED封装和制造这样的封装的方法。
背景技术
各种LED封装是已知的。例如,在适当的衬底上直接可焊的晶片级芯片规模的LED封装是已知的。这样的封装通常具有到二极管的p-n结的两个触头。LED封装可以例如被安装至承载用于LED的控制电路(例如,ESD二极管或者控制晶体管)的衬底。
举例来说,LED管芯可以被安装在硅衬底上,其中该衬底包含嵌入式ESD保护二极管。在衬底顶部上的触头做出与LED管芯端子的电连接,并且衬底在相同顶面上、在LED管芯被安装所在的区域之外具有另外的外部触头。这要求衬底上方的每个LED管芯的单独放置,例如使用球栅阵列。
还已知的是,除了ESD保护之外,通过将LED与控制晶体管相关联,驱动和控制LED串成为可能。例如,通过将各个FET晶体管并联连接至每个LED,可以单独地控制串联的多个LED。通过闭合晶体管开关,对应的LED被短路并且将被切断。
仍然有针对用于LED和相关联的控制器件(例如晶体管或者ESD保护二极管或者更复杂的控制电路)的有成本效益且紧凑的封装解决方案的需要。
US6281032B1公开了制备半导体激光器晶片,其中多个半导体激光器形成在衬底上的半导体层上并且通过足够深以到达衬底的槽彼此分离,并且在每个半导体激光器中形成p-侧电极和n-侧电极。通过将p-侧电极和n-侧电极定位成分别与焊接电极对准,半导体激光器晶片被接合至具有形成的用于监视光输出的光电二极管和每个片状器件(pellet)中的焊接电极的光电二极管内置晶片。
US2007/0272939A1公开了在支撑硅芯片的第一表面上形成第一和第二电极,在支撑硅芯片的第二表面上形成第三和第四电极。第一和第二电极分别与第三和第四电极电连接。第二电极的位置和形状对应于半导体芯片的接合层的位置和形状,而第一电极的位置和形状对应于保护塞的位置和形状。
US2012/0018745A1公开了至少包括照明器件、控制器件和连接器的集成照明装置,所述控制器件包括集成电路,所述连接器被用于电连接照明器件和控制器件。
发明内容
根据本发明,提供了如在独立权利要求中限定的方法和装置。
根据一个方面,提供了形成LED封装的方法,包括:
- 形成集成电路LED的阵列作为第一半导体衬底的部分;
- 形成开关晶体管的阵列作为第二半导体衬底的部分,包括形成在第二半导体衬底的相对的面之间延伸的通孔;
- 将第一和第二半导体衬底接合在一起,其中第一半导体衬底的每一个LED定位在第二半导体衬底的对应的开关晶体管上方,从而做出LED和开关晶体管之间的电连接;
- 对所接合的第一和第二半导体衬底进行划片以形成各个LED封装或者LED封装的组,
其中每个LED封装在第二半导体衬底的与第一面相对的面上具有三个封装端子,包括两个电力线端子和一个控制端子,并且其中控制端子连接至开关晶体管的栅极。
该方法提供作为LED封装的部分、并且直接在LED下方的开关晶体管。这允许紧凑的设计。晶片级接合发生在LED衬底和晶体管衬底之间,使得仅要求一个划片步骤来形成封装,并且在两个衬底之间仅需要一次对准过程。
形成开关晶体管的阵列包括形成在第二半导体衬底的相对面之间延伸的通孔。这样,第二衬底的一侧具有连接至LED(使用过孔)以及(直接地)连接至开关晶体管的所有所要求的封装端子。
开关晶体管可被用作控制器件,以控制各个LED。这可例如被用于调光控制或者LED阵列的照射图案的控制。
根据另一方面,提供了LED封装,包括:
- 被形成为第一半导体衬底并且在一面上具有LED连接端子的集成电路LED;
- 被形成为第二半导体衬底的开关晶体管,其中第一半导体衬底的所述一面和第二半导体衬底的第一面接合在一起,其中第一半导体衬底的LED定位在开关晶体管上方,并且在LED和对应的开关晶体管之间具有电连接,
其中封装在第二半导体衬底的与第一面相对的面上具有三个封装端子,包括两个电力线端子(56a、56b)和一个控制端子,并且第二衬底具有提供封装端子和LED连接端子之间的连接的至少一个通孔,并且其中控制端子连接至开关晶体管的栅极。
该封装具有使得能够实现到LED和相关联的开关晶体管的连接的单个连接面。通过将LED堆叠在其相关联的开关晶体管上方,该布置是空间高效的。
使得能够实现到至少一个LED端子的连接。例如,如果LED与开关晶体管串联,则封装端子可做出到一个LED端子和一个晶体管端子(即串联连接的端部)的连接。然而,第二衬底可具有提供相应的封装端子和两个LED连接端子之间的连接的至少两个通孔。因而,使得能够实现到两个LED端子的连接。
晶体管可被用于控制LED的操作。例如,晶体管可与LED并联。这样,其可提供旁路功能并且因而可以被用来中断通过LED的电流。这使得能够实现用作电阻性驱动器方案的部分,以切断电压源之间的一个LED或串联的多个LED。
封装端子然后可包括到晶体管源极、漏极和栅极的连接。
LED电路可包括安装在印刷电路板上的本发明的至少一个封装,其中印刷电路板具有用于到三个封装端子的连接的迹线(track)。
三个端子使得能够实现LED串的控制。栅极端子提供开关功能,开关功能是通过在器件的底部处的相关联的封装端子被激活的。
附图说明
现在将参照附图详细描述本发明的示例,其中:
图1示出了安装在底座上的已知LED封装;
图2示出了为串中的每个LED提供开关的已知电路;
图3示出了实施图2的电路的已知方式;
图4示出了本发明的电路;
图5示出了在图4的电路中使用的一个LED封装;
图6示出了在划片之前于晶片级接合之后的一串LED封装的侧视图;
图7a以透视阴影视图示出了一个封装的分解视图并且图7b示出了作为线条图的相同视图;
图8示出了在晶片级接合之前并且在划片之前,并且从上方的分离的器件阵列;和
图9示出了在晶片级接合之前并且在划片之前,并且从下方的分离的器件阵列。
所有的图都是示意性的,不一定是按比例的,并且为了阐明本发明,一般仅示出必要的部分,其中其它的部分可以被省略或者仅仅被暗示。
具体实施方式
本发明提供LED封装和制造方法,其中封装具有接合在一起的LED衬底和电路衬底,其中LED在集成电路上方,并且在LED和对应的集成电路之间具有电连接。该封装仅在带有通孔的一个面上具有封装端子,所述通孔提供一个衬底上的封装端子之间的连接以及其它衬底的LED连接。因而,即使封装具有两个衬底,它也具有用于以简单的方式在诸如PCB的载体上方进行安装的单个连接面。
单个连接面使得能够实现到LED以及到相关联的电路的电连接。通过在其相关联的电路上方堆叠LED,该布置是空间高效的。
图1示出了已知的LED封装。LED 10被形成为分立的封装,其例如通过焊球被安装在硅底座12上。到LED封装的连接是通过焊球做出的,并且从底座的外部连接是由引线接合(wirebond)14做出的。如图1中示意性地示出的,底座12可以实施一对ESD保护二极管。因而,ESD保护是将附加的组件与每个LED相关联的一个原因。
将附加的组件与每个LED相关联的另一原因是提供开关功能性。图2示出了已知的电路,其为LED串(LED1至LED4)中的每个LED提供并联开关M1至M4。通过接通开关,旁路通路被提供使得单独的LED被关断。
图3示出了实施图2的电路的已知方式。多个分立的LED封装30被安装在PCB 32上的迹线的上方。两条迹线31连接至两条电力线。各个LED封装30之间的附加迹线提供LED封装之间的串联连接。另外的迹线连接至也安装在PCB上的晶体管34,并且晶体管具有形成连接至它们的栅极的控制线36的PCB迹线。图3还以分解的形式示出了LED封装中的一个。该布置占据大量的空间。它还要求LED封装以及晶体管的安装。
图4示出了本发明的电路。该电路再次具有安装在PCB 42上的LED封装40,具有连接至电力线的PCB迹线42以用于LED的串联布置。LED封装40将LED和相关联的晶体管集成到单个封装中,其中LED覆盖晶体管。该封装仅在一个面(也就是,背对PCB 42的面)上具有封装端子。存在三个封装端子、两个电力线端子和用于连接至封装内的晶体管栅极的控制端子。控制端子连接至PCB迹线46。这提供了更加紧凑的布置并且具有减少的安装要求。图4还以分解的形式示出了LED封装中的一个以及平面视图。
图5更加详细地示出了在图4的电路中使用的一个LED封装40。每个LED封装包括形成为第一半导体衬底50并且在一个面上具有LED连接端子52a、52b的集成电路LED。这些端子连接至LED的n-和p-结。LED可以是pn二极管、或者pin二极管或者任何其它的已知二极管配置。它可以是竖直的或者横向的。
集成电路(在该示例中,开关晶体管)被形成为第二半导体衬底54。第一半导体衬底50的承载端子52a、52b的面与第二半导体衬底54的第一面接合在一起。为了清楚起见,这两个衬底在图5中被分离地示出。
第二衬底54的接合面承载用于到端子52a、52b的连接的接触垫55a、55b。
当被连接时,第一半导体衬底50的LED定位在集成电路上方,并且具有LED和对应的集成电路之间的电连接。
封装在第二半导体衬底54的相对面上具有封装端子56a、56b、56c。第二衬底54具有通孔58a、58b,通孔58a、58b提供封装端子56a、56b和用于到LED连接端子52a、52b的连接的接触垫55a、55b中的两个之间的连接。第三封装端子56c连接至晶体管的栅极,其以常规的方式形成在半导体衬底内。
这样,单组的封装端子使得能够实现到LED以及到晶体管的连接。如果对于LED封装的特定使用而言,不需要封装的晶体管,则不需要做出到晶体管栅极的连接,并且封装可以被用作正常的两端子LED封装。
图6示出了一串LED封装的截面视图,并且示出了于划片之前在晶片级接合之后的彼此接触的两个衬底。
图7a示出了一个封装的分解的透视图。使用与图5中的相同的附图标记。第二衬底54的晶体管结构被一般性地示出在70处,其连接在接触垫55a、55b之间。图7a是透视阴影视图并且图7b示出了作为线条图的相同视图。
在示出的示例中,栅极形成在第二衬底的第一面中。过孔被形成,以使得能够实现从第二衬底的相对侧上的封装端子到栅极的连接。
注意,晶体管结构可能在第二半导体衬底54的底表面上,并且在该情形中,将不需要用于栅极的过孔。
该布置可以更容易地被制造。特别地,在划片之前,两个衬底之间的晶片级接合是可能的。
如图8中所示,两个衬底50、54可以被形成为全阵列。然后,执行两个衬底之间的晶片接合。可能的互连方法包括微凸块或者金纳米海绵(gold nanosponge)。图8示出了从上方的视图,并且示出了在顶部衬底50的顶部处的划片线和在底部衬底54的顶部处的接触垫。图9示出了从下方的视图,并且示出了在顶部衬底50的底部处的LED接触垫和在底部衬底54的底部处的封装端子。
为了避免由于热膨胀导致的应力失配,晶片级接合应当避免高温过程。利用适当的衬底设计,可以使用通常针对单个管芯附接方法使用的超声接合。替代性地,可以应用冷互连方法,例如导电粘合。
只有在晶片级接合之后,各个LED、或形成各个封装的LED组才被分离。使用硅通孔技术的晶片级连接被已知用于3D封装解决方案。如针对第二衬底54所示的,这些允许将接触带到器件的底部。
在以上的示例中,并联开关被添加至每个LED。当然,串联开关也可以相同的方式被添加。在该情形中,可能不需要到两个LED端子的外部连接。而是,则需要到串联电路的每个端以及到晶体管栅极的连接。因而,三个封装端子则可包括晶体管源极或者漏极(未连接至LED的那个)、晶体管栅极以及LED连接端子中的仅一个。
当然,可以在第二衬底中提供更加复杂的电路。例如,ESD二极管以及晶体管可以被集成到封装中。另外,在每个封装中可以实施更加复杂的晶体管控制电路,例如为了局部调光控制。
一般地,本发明可被用来形成LED封装。特别感兴趣的是用于要求各个LED的控制的LED阵列的封装。特别地,在汽车应用中,用于提供光方向的动态控制的动态LED矩阵阵列是已知的。
晶体管与每个LED的使用使得串联的多个LED能够被单独地控制。本发明提供开关到LED封装中的集成,所述开关直接在LED的下方。这允许紧凑的驱动器设计并且简化了LED串的控制。
另外,组件可适合于从市电电压驱动的多LED源,在市电电压中根据市电电压的相位控制跨LED的正向电压。在220V市电电压网络中,实际的电压在+325和-325V之间周期性地振荡。如果LED串包含具有3V左右的平均正向电压的100个LED,则市电电压可直接被施加至串,而没有过驱动LED的风险(实践中,这样的电路通常将包含整流器和保护性电阻器)。如果所有的LED总是保持成串,则各个LED处的电压在市电循环时在用于光生成的接通电压以下。已知的是,与减小市电电压同步,增加数量的LED可以被切断以允许余下的LED高效地提供光的生成。
用来形成集成电路LED和集成电路晶体管的过程没有被详细描述,因为它们是常规的。实际上,可以使用任何的二极管技术和任何的晶体管技术。另外,不同的衬底可以使用不同的材料以及制造过程,因为它们是独立形成的。
本领域技术人员在实践要求保护的发明时,通过绘图、公开内容以及所附权利要求的研究,可以理解和实现所公开的实施例的其它变型。在权利要求中,词语“包括”不排除其它的元件或步骤,并且不定冠词“一”或“一个”不排除多个。某些措施被记载在相互不同的从属权利要求中这一纯粹事实不指示这些措施的组合不能被用于获益。权利要求中的任何参考标记不应当被解释为限制范围。
Claims (12)
1.一种形成LED封装的方法,包括:
- 形成集成电路LED(40)的阵列作为第一半导体衬底(50)的部分;
- 形成开关晶体管的阵列作为第二半导体衬底(54)的部分,包括形成在所述第二半导体衬底的相对的面之间延伸的通孔(58a、58b);
- 将第一和第二半导体衬底(50、54)接合在一起,其中所述第一半导体衬底(50)的每一个LED(40)定位在所述第二半导体衬底的对应的开关晶体管上方,从而做出所述LED和对应的开关晶体管之间的电连接;
- 对所接合的第一和第二半导体衬底(50、54)进行划片以形成各个LED封装或者LED封装的组,
其中每个LED封装在所述第二半导体衬底(54)的与第一面相对的面上具有三个封装端子(56a、56b、56c),包括两个电力线端子(56a、56b)和一个控制端子(56c),并且其中所述控制端子(56c)连接至所述开关晶体管的栅极,所述第一面是所述第二半导体衬底的面,所述第一半导体衬底和所述第二半导体衬底在所述第一面处接合在一起。
2.一种LED封装,包括:
- 被形成为第一半导体衬底(50)并且在一面上具有两个LED连接端子(52a、52b)的集成电路LED(40);
- 被形成为第二半导体衬底(54)的开关晶体管,其中所述第一半导体衬底(50)的所述一面和所述第二半导体衬底(54)的第一面接合在一起,其中所述第一半导体衬底的所述LED(40)定位在所述开关晶体管上方,并且在LED和对应的开关晶体管之间具有多个电连接,
其中所述封装在所述第二半导体衬底(54)的与第一面相对的面上具有三个封装端子(56a、56b、56c),包括两个电力线端子(56a、56b)和一个控制端子(56c),并且所述第二半导体衬底具有提供封装端子和LED连接端子(52a、52b)之间的连接的至少一个通孔(58a、58b),并且其中所述控制端子(56c)连接至所述开关晶体管的栅极。
3.如权利要求2中所要求保护的LED封装,其中并且所述第二半导体衬底(54)具有提供相应的封装端子(56a、56b)和两个LED连接端子(52a、52b)之间的连接的至少两个通孔(58a、58b)。
4.如权利要求2中所要求保护的LED封装,还包括将所述开关晶体管的栅极连接至所述控制端子的过孔。
5.如权利要求2中所要求保护的LED封装,其中所述开关晶体管与所述LED并联。
6.如权利要求5中所要求保护的LED封装,其中所述封装端子包括到所述开关晶体管源极、漏极和栅极的连接。
7.如权利要求2中所要求保护的LED封装,其中所述开关晶体管与所述LED串联。
8.如权利要求7中所要求保护的LED封装,其中所述封装端子包括到所述开关晶体管源极或者漏极、所述开关晶体管栅极以及所述LED连接端子中的一个的连接。
9.一种LED电路,包括安装在印刷电路板上的如权利要求6中所要求保护的至少一个LED封装,其中所述印刷电路板具有用于到三个封装端子的连接的迹线。
10.如权利要求9中所要求保护的LED电路,包括串联的多个LED封装。
11.如权利要求10中所要求保护的LED电路,从市电电压被驱动。
12.一种LED电路,包括安装在印刷电路板上的如权利要求8中所要求保护的至少一个LED封装,其中所述印刷电路板具有用于到三个封装端子的连接的迹线。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261680331P | 2012-08-07 | 2012-08-07 | |
US61/680331 | 2012-08-07 | ||
PCT/IB2013/056353 WO2014024108A1 (en) | 2012-08-07 | 2013-08-02 | Led package and manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104508811A CN104508811A (zh) | 2015-04-08 |
CN104508811B true CN104508811B (zh) | 2017-09-22 |
Family
ID=49165811
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201380041899.5A Active CN104508811B (zh) | 2012-08-07 | 2013-08-02 | Led封装和制造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9461027B2 (zh) |
EP (1) | EP2883243B1 (zh) |
JP (1) | JP6325541B2 (zh) |
KR (1) | KR102054337B1 (zh) |
CN (1) | CN104508811B (zh) |
TW (1) | TWI594467B (zh) |
WO (1) | WO2014024108A1 (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102014105734A1 (de) * | 2014-04-23 | 2015-10-29 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils |
DE102015104185A1 (de) * | 2015-03-20 | 2016-09-22 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zu seiner Herstellung |
FR3041148A1 (fr) * | 2015-09-14 | 2017-03-17 | Valeo Vision | Source lumineuse led comprenant un circuit electronique |
USD782988S1 (en) * | 2015-11-02 | 2017-04-04 | Epistar Corporation | Light-emitting module |
FR3044467B1 (fr) * | 2015-11-26 | 2018-08-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Dalle lumineuse et procede de fabrication d'une telle dalle lumineuse |
US10290777B2 (en) | 2016-07-26 | 2019-05-14 | Cree, Inc. | Light emitting diodes, components and related methods |
DE102016124646A1 (de) * | 2016-12-16 | 2018-06-21 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements |
CN106711135A (zh) * | 2017-01-09 | 2017-05-24 | 丽智电子(昆山)有限公司 | 一种模组化的光电二极管封装器件 |
DE102017123290A1 (de) | 2017-10-06 | 2019-04-11 | Osram Opto Semiconductors Gmbh | Lichtemittierendes Bauteil, Anzeigevorrichtung und Verfahren zur Herstellung einer Anzeigevorrichtung |
US11749790B2 (en) | 2017-12-20 | 2023-09-05 | Lumileds Llc | Segmented LED with embedded transistors |
CN113764565A (zh) | 2018-02-01 | 2021-12-07 | 新唐科技日本株式会社 | 半导体装置 |
US11024785B2 (en) * | 2018-05-25 | 2021-06-01 | Creeled, Inc. | Light-emitting diode packages |
US11335833B2 (en) | 2018-08-31 | 2022-05-17 | Creeled, Inc. | Light-emitting diodes, light-emitting diode arrays and related devices |
USD902448S1 (en) | 2018-08-31 | 2020-11-17 | Cree, Inc. | Light emitting diode package |
US11233183B2 (en) | 2018-08-31 | 2022-01-25 | Creeled, Inc. | Light-emitting diodes, light-emitting diode arrays and related devices |
US10985134B2 (en) * | 2018-11-09 | 2021-04-20 | Nanya Technology Corporation | Method and system of manufacturing stacked wafers |
US11101411B2 (en) | 2019-06-26 | 2021-08-24 | Creeled, Inc. | Solid-state light emitting devices including light emitting diodes in package structures |
KR102199183B1 (ko) | 2020-02-27 | 2021-01-06 | (주) 성진일렉트론 | 고출력 led 패키지 및 그 제조방법 |
JP7510820B2 (ja) | 2020-08-31 | 2024-07-04 | シャープ福山レーザー株式会社 | 画像表示素子 |
WO2022109436A1 (en) * | 2020-11-23 | 2022-05-27 | Sense Photonics, Inc. | Multi-wafer integrated vcsel-electronics module |
EP4021149A1 (en) | 2020-12-22 | 2022-06-29 | Textron Systems Corporation | Light appartus with parallel-arranged leds and per-led drivers |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1851948A (zh) * | 2006-05-29 | 2006-10-25 | 金芃 | 通孔垂直结构的半导体芯片或器件 |
CN102097554A (zh) * | 2010-12-21 | 2011-06-15 | 天津工业大学 | 一种GaN基单芯片白光发光二极管及其制备方法 |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3985327B2 (ja) * | 1998-02-27 | 2007-10-03 | 松下電器産業株式会社 | 半導体発光装置 |
JP4126749B2 (ja) * | 1998-04-22 | 2008-07-30 | ソニー株式会社 | 半導体装置の製造方法 |
JP2000031541A (ja) * | 1998-07-09 | 2000-01-28 | Okaya Electric Ind Co Ltd | Led表示素子 |
US6633322B2 (en) | 2000-05-29 | 2003-10-14 | Kyocera Corporation | Light emitting element array, optical printer head using the same, and method for driving optical printer head |
JP2002026263A (ja) * | 2000-07-05 | 2002-01-25 | Sanken Electric Co Ltd | 保護回路、保護回路素子及び発光デバイス |
US6933707B2 (en) | 2002-06-27 | 2005-08-23 | Luxidein Limited | FET current regulation of LEDs |
JP5060017B2 (ja) * | 2004-08-12 | 2012-10-31 | セイコーエプソン株式会社 | プロジェクタ |
KR100506743B1 (ko) * | 2004-09-17 | 2005-08-08 | 삼성전기주식회사 | 트랜지스터를 구비한 플립칩 구조 발광장치용 서브 마운트 |
TW200623387A (en) * | 2004-12-16 | 2006-07-01 | Guo-Enn Chang | A static discharge prevention device for flip-chip semiconductor of encapsulating compound and method of its formation |
US7692207B2 (en) | 2005-01-21 | 2010-04-06 | Luminus Devices, Inc. | Packaging designs for LEDs |
KR101198374B1 (ko) * | 2006-02-23 | 2012-11-07 | 삼성디스플레이 주식회사 | 발광 다이오드 기판 및 그 제조 방법과 그를 이용한 액정표시 장치 |
JP5394617B2 (ja) * | 2006-06-16 | 2014-01-22 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法及び基板 |
CN100446288C (zh) * | 2006-08-01 | 2008-12-24 | 金芃 | 通孔垂直结构的半导体芯片及其制造方法 |
JP4967548B2 (ja) * | 2006-09-06 | 2012-07-04 | 株式会社ニコン | 発光装置 |
TWI420691B (zh) * | 2006-11-20 | 2013-12-21 | 尼康股份有限公司 | Led裝置及其製造方法 |
JP2008262993A (ja) * | 2007-04-10 | 2008-10-30 | Nikon Corp | 表示装置 |
US8110835B2 (en) | 2007-04-19 | 2012-02-07 | Luminus Devices, Inc. | Switching device integrated with light emitting device |
JP2010050165A (ja) * | 2008-08-19 | 2010-03-04 | Sumitomo Chemical Co Ltd | 半導体装置、半導体装置の製造方法、トランジスタ基板、発光装置、および、表示装置 |
JP2010114216A (ja) * | 2008-11-05 | 2010-05-20 | Sharp Corp | Led照明装置 |
US8400064B2 (en) * | 2009-09-09 | 2013-03-19 | Koninklijke Philips Electronics N.V. | Zener diode protection network in submount for LEDs connected in series |
US8598797B2 (en) | 2010-05-18 | 2013-12-03 | Luxera, Inc. | LED driver for driving LED lighting device at high frequency |
TWI478319B (zh) * | 2010-07-20 | 2015-03-21 | Epistar Corp | 整合式發光裝置及其製造方法 |
JPWO2012086517A1 (ja) * | 2010-12-20 | 2014-05-22 | ローム株式会社 | 発光素子ユニットおよび発光素子パッケージ |
DE102011016308A1 (de) * | 2011-04-07 | 2012-10-11 | Osram Opto Semiconductors Gmbh | Anzeigevorrichtung |
EP2883421B1 (en) * | 2012-08-07 | 2019-10-02 | Lumileds Holding B.V. | Led circuit |
-
2013
- 2013-08-02 WO PCT/IB2013/056353 patent/WO2014024108A1/en active Application Filing
- 2013-08-02 EP EP13762282.5A patent/EP2883243B1/en active Active
- 2013-08-02 CN CN201380041899.5A patent/CN104508811B/zh active Active
- 2013-08-02 US US14/419,539 patent/US9461027B2/en active Active
- 2013-08-02 JP JP2015525986A patent/JP6325541B2/ja active Active
- 2013-08-02 KR KR1020157005926A patent/KR102054337B1/ko active IP Right Grant
- 2013-08-06 TW TW102128151A patent/TWI594467B/zh active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1851948A (zh) * | 2006-05-29 | 2006-10-25 | 金芃 | 通孔垂直结构的半导体芯片或器件 |
CN102097554A (zh) * | 2010-12-21 | 2011-06-15 | 天津工业大学 | 一种GaN基单芯片白光发光二极管及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
US9461027B2 (en) | 2016-10-04 |
TWI594467B (zh) | 2017-08-01 |
JP6325541B2 (ja) | 2018-05-16 |
US20150214201A1 (en) | 2015-07-30 |
KR20150041082A (ko) | 2015-04-15 |
EP2883243B1 (en) | 2020-10-07 |
EP2883243A1 (en) | 2015-06-17 |
WO2014024108A1 (en) | 2014-02-13 |
CN104508811A (zh) | 2015-04-08 |
JP2015524623A (ja) | 2015-08-24 |
TW201414023A (zh) | 2014-04-01 |
KR102054337B1 (ko) | 2020-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104508811B (zh) | Led封装和制造方法 | |
CN104521324B (zh) | Led电路 | |
US8129917B2 (en) | Light emitting device for AC operation | |
CN102403309B (zh) | 发光器件 | |
TW201143023A (en) | Light emitting diode package, lighting device and light emitting diode package substrate | |
TWI484656B (zh) | 晶片配置,連接配置,發光二極體和晶片配置的製造方法 | |
TW201203534A (en) | An optoelectronic device | |
CN103972184B (zh) | 芯片布置和芯片封装 | |
KR101508006B1 (ko) | Led 하이브리드 파워 패키지 모듈 | |
CN105990495A (zh) | 发光单元及半导体发光装置 | |
CN104183584A (zh) | 一种led阵列光源结构 | |
KR101519110B1 (ko) | 발광다이오드 패키지 및 그 제조방법 | |
CN103367338A (zh) | 芯片装置和形成其的方法、芯片封装和形成其的方法 | |
CN105609620B (zh) | 一种led光引擎封装结构的制备方法 | |
CN104103680B (zh) | 芯片和芯片装置 | |
CN103633231B (zh) | 半导体发光装置 | |
TWI281271B (en) | Manufacturing method for integrated LED and the structure thereof | |
US8680541B2 (en) | LED structure and the LED package thereof | |
CN205959972U (zh) | 一种多类型led芯片组合封装模组 | |
CN204011473U (zh) | 一种led的封装结构 | |
TWI576975B (zh) | 半導體積體電路裝置 | |
CN104254203A (zh) | 电路布置以及用于制造所述电路布置的方法 | |
CN113871523A (zh) | 一种无焊线发光二极管的封装结构及其封装方法 | |
JPH06120565A (ja) | 発光ダイオード光源 | |
CN107516656A (zh) | 一种多类型led芯片组合封装模组 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
EXSB | Decision made by sipo to initiate substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20180326 Address after: Holland Schiphol Patentee after: LUMILEDS HOLDING B.V. Address before: Holland Ian Deho Finn Patentee before: Koninkl Philips Electronics NV |
|
TR01 | Transfer of patent right |