TW201414023A - 發光二極體封裝及製造方法 - Google Patents
發光二極體封裝及製造方法 Download PDFInfo
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- TW201414023A TW201414023A TW102128151A TW102128151A TW201414023A TW 201414023 A TW201414023 A TW 201414023A TW 102128151 A TW102128151 A TW 102128151A TW 102128151 A TW102128151 A TW 102128151A TW 201414023 A TW201414023 A TW 201414023A
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- Prior art keywords
- led
- package
- integrated circuit
- semiconductor substrate
- connection
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- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 239000004065 semiconductor Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 14
- 238000003491 array Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- ALFHIHDQSYXSGP-UHFFFAOYSA-N 1,2-dichloro-3-(2,4-dichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC=C1C1=CC=CC(Cl)=C1Cl ALFHIHDQSYXSGP-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- IHIDFKLAWYPTKB-UHFFFAOYSA-N 1,3-dichloro-2-(4-chlorophenyl)benzene Chemical compound C1=CC(Cl)=CC=C1C1=C(Cl)C=CC=C1Cl IHIDFKLAWYPTKB-UHFFFAOYSA-N 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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Abstract
本發明揭示一種LED封裝(40)及製造方法,其中該封裝具有接合在一起之一LED基板(50)及一電路基板(54),其中LED處於積體電路上方且具有LED與對應積體電路之間之電連接。該封裝僅在一面上具有封裝端子(56a、56b),其中穿孔(58a、58b)提供該LED基板與該電路基板之間之連接。
Description
本發明係關於LED封裝及製造此等封裝之方法。
已知各種LED封裝。舉例而言,已知可直接焊接在一合適基板上之晶圓級晶片尺寸LED封裝。此一封裝通常具有至二極體之p-n接面之兩個接觸件。舉例而言,LED封裝可安裝至承載LED之控制電路(例如靜電放電(ESD)二極體或控制電晶體)之一基板。
藉由實例,一LED晶粒可安裝在一矽基板上,其中基板含有一嵌入式ESD保護二極體。在基板之頂部上之接觸件與LED晶粒端子電連接,且基板在相同頂面上安裝LED晶粒之區域外部具有進一步外部接觸件。此需要(例如)使用一球柵陣列將各LED晶粒個別地放置在基板上方。
亦已知,除ESD保護外,藉由使LED與控制電晶體相關聯,可驅動及控制LED串。舉例而言,藉由將個別FET電晶體並聯連接至各LED,可個別地控制多個串聯LED。藉由閉合一電晶體開關,一對應LED短路且將關斷。
仍需要一種用於LED及相關聯控制裝置(諸如一電晶體或ESD保護二極體或更複雜控制電路)之具有成本效益及緊密封裝解決方案。
根據本發明,提供如獨立技術方案所定義之方法及設備。
- 根據一態樣,提供一種形成一LED封裝之方法,其包括:- 形成積體電路LED之一陣列作為一第一半導體基板之部分;- 形成積體電路組件LED之一陣列作為一第二半導體基板之部分;- 將該第一半導體基板及該第二半導體基板接合在一起,使得該第一半導體基板之各LED定位於該第二半導體基板之一(若干)對應積體電路組件上方,藉此製成LED與(若干)對應積體電路組件之間之電連接;- 切割經接合之第一半導體基板及第二半導體基板以形成個別LED封裝或LED封裝之群組。
此方法直接在LED下方提供一電路作為LED封裝之部分。此允許一緊密設計。晶圓級接合發生在LED基板與電路基板之間,使得僅需一切割步驟以形成封裝且在兩個基板之間僅需一對準程序。
形成積體電路組件之陣列可包括形成在第二半導體基板之相對面之間延伸之穿孔。以此方式,第二基板之一側具有用以連接至LED(使用通孔)及(直接)連接至(若干)積體電路組件之全部所需封裝端子。
形成積體電路組件之陣列可包括形成電晶體之一陣列。此等可用作控制裝置以控制個別LED。舉例而言,此可用於調光控制或LED之一陣列之照明型樣之控制。
形成積體電路組件之陣列可包括形成二極體之一陣列,接著可將該二極體陣列用於ESD保護。
根據另一態樣,提供一種LED封裝,其包括:- 一積體電路LED,其形成為一第一半導體基板且在一面上具有LED連接端子;- 一積體電路,其形成為一第二半導體基板,其中將該第一半導
體基板之該一面及該第二半導體基板之一第一面接合在一起,使得該第一半導體基板之LED定位於該積體電路上方且具有LED與對應積體電路之間之電連接,其中該封裝在該第二半導體基板之與第一面相對之面上具有封裝端子且第二基板具有提供一封裝端子與一LED連接端子之間之連接之至少一穿孔。
此封裝具有實現至一LED及相關聯電路之連接之一單一連接面。藉由將LED堆疊在其相關聯電路上方,可使配置具空間效益。
實現至至少一LED端子之連接。舉例而言,若LED與積體電路串聯,則封裝端子可製成至一LED端子及一積體電路端子(即,串聯連接之端點)之連接。然而,第二基板可具有提供各自封裝端子與兩個LED連接端子之間之連接之至少兩個穿孔。因此,實現至兩個LED端子之連接。
積體電路可包括一ESD保護二極體。然而,在一較佳實例中,該積體電路包括一電晶體。此可用於控制LED之操作。舉例而言,電晶體可與LED並聯。以此方式,可提供一旁通功能且因此可用以中斷通過LED之電流。此可用作電阻性驅動器方案之部分以關斷在一電壓源之間之一或多個串聯LED。
封裝端子接著可包括至電晶體源極、汲極及閘極之連接。
一LED電路可包括安裝在一印刷電路板上之本發明之至少一封裝,其中該印刷電路板具有用於連接至三個封裝端子之軌跡。
該三個端子實現LED串之控制。閘極端子提供一切換功能,該切換功能係藉由裝置底部處之相關聯封裝端子啟動。
10‧‧‧發光二極體(LED)
12‧‧‧矽子基板
14‧‧‧線接合
30‧‧‧發光二極體(LED)封裝
31‧‧‧軌跡
32‧‧‧印刷電路板(PCB)
34‧‧‧電晶體
36‧‧‧控制線
40‧‧‧發光二極體(LED)封裝
41‧‧‧印刷電路板(PCB)軌跡
42‧‧‧印刷電路板(PCB)
46‧‧‧印刷電路板(PCB)軌跡
50‧‧‧第一半導體基板
52a‧‧‧發光二極體(LED)連接端子
52b‧‧‧發光二極體(LED)連接端子
54‧‧‧第二半導體基板/第二基板
55a‧‧‧接觸襯墊
55b‧‧‧接觸襯墊
56a‧‧‧封裝端子
56b‧‧‧封裝端子
56c‧‧‧封裝端子/第三封裝端子
58a‧‧‧穿孔
58b‧‧‧穿孔
M1‧‧‧開關
M2‧‧‧開關
M3‧‧‧開關
M4‧‧‧開關
現將參考附圖詳細描述本發明之一實例,其中:圖1展示安裝在一子基板上之一已知LED封裝;
圖2展示對一串之各LED提供一開關之一已知電路;圖3展示實施圖2之電路之一已知方式;圖4展示本發明之一電路;圖5展示在圖4之電路中所使用之一LED封裝;圖6展示在切割之前晶圓級接合之後一LED封裝串之一側視圖;圖7a以透視陰影視圖展示一封裝之一分解圖且圖7b將相同視圖展示為一線圖;圖8展示在晶圓級接合及切割之前自上方觀看之個別裝置陣列;及圖9展示在晶圓級接合及切割之前自下方觀看之個別裝置陣列。
所有圖係示意性的,而不必按比例繪製,且通常僅展示必要部分以闡明本發明,其中可省略或僅建議其他部分。
本發明提供一種LED封裝及製造方法,其中該封裝具有接合在一起之一LED基板及一電路基板,其中LED處於積體電路上方且具有LED與對應積體電路之間之電連接。該封裝僅在一面上具有封裝端子,其中穿孔提供一基板上之封裝端子與其他基板之LED連接之間之連接。因此,即使封裝具有兩個基板,該封裝仍具有以簡單方式安裝在一載體(諸如一印刷電路板(PCB))上方之一單一連接面。
單一連接面可電連接至LED及相關聯電路。藉由將LED堆疊在其相關聯電路上方,可使配置具空間效益。
圖1展示一已知LED封裝。LED 10形成為例如藉由焊料球安裝在一矽子基板12上之一離散封裝。透過該等焊料球製成至LED封裝之連接且藉由線接合14製成來自子基板之外部連接。如在圖1中示意性展示,子基板12可實施一對ESD保護二極體。因此,ESD保護係使額外組件與各LED相關聯之一原因。
使額外組件與各LED相關聯之另一原因係提供切換功能性。圖2展示對一LED串(LED1至LED4)之各LED提供一並聯開關M1至M4之一已知電路。藉由開啟一開關,提供一旁通路徑以關閉個別LED。
圖3展示實施圖2之電路之一已知方式。若干離散LED封裝30安裝於PCB 32上之軌跡上方。兩個軌跡31連接至兩個電力線。個別LED封裝30之間之額外軌跡提供該等LED封裝之間之串聯連接。進一步軌跡連接至亦安裝在PCB上之電晶體34且該等電晶體具有形成連接至其等閘極之控制線36之PCB軌跡。圖3以分解形式亦展示LED封裝之一者。此配置佔據大量空間。此亦需要安裝LED封裝以及電晶體。
圖4展示本發明之一電路。該電路又具有安裝在一PCB 42上之LED封裝40,其中PCB軌跡42連接至用於LED之串聯配置之電力線。LED封裝40將LED及相關聯電晶體整合至一單一封裝中,其中LED上覆於電晶體。該封裝僅在一面(即抵靠PCB 42之面)上具有封裝端子。在封裝內存在用於連接至電晶體閘極之三個封裝端子、兩個電力線端子及一控制端子。控制端子連接至一PCB軌跡46。此提供具有降低之安裝要求之一更緊密配置。圖4以分解形式亦展示LED封裝之一者以及一平面圖。
圖5更詳細展示圖4之電路中所使用之一LED封裝40。各LED封裝包括形成為一第一半導體基板50且在一面上具有LED連接端子52a、52b之一積體電路LED。此等端子連接至LED之n接面及p接面。該LED可係一pn二極體或一接針二極體或任何其他已知二極體組態。其可係垂直或橫向。
形成一積體電路(在此實例中係切換電晶體)作為一第二半導體基板54。將第一半導體基板50之承載該等端子52a、52b之面及第二半導體基板54之一第一面接合在一起。為清楚起見,圖5中展示兩個分離基板。
第二基板54之接合面承載用於連接至該等端子52a、52b之接觸襯墊55a、55b。
在經連接時,第一半導體基板50之LED定位於積體電路上方,且具有LED與對應積體電路之間之電連接。
該封裝在第二半導體基板54之相對面上具有封裝端子56a、56b、56c。第二基板54具有提供封裝端子56a、56b之兩者與用於連接至LED連接端子52a、52b之接觸襯墊55a、55b之間之連接之穿孔58a、58b。一第三封裝端子56c連接至電晶體之閘極,該第三封裝端子56c以習知方式形成在半導體基板內。
以此方式,封裝端子之單一集合實現至LED以及電晶體之連接。若LED封裝之特殊用法無需封裝之電晶體,則無需製成至電晶體閘極之連接且封裝可用作一普通兩端子LED封裝。
圖6展示一LED封裝串之一橫截面視圖且展示在晶圓級接合之後切割之前彼此接觸之兩個基板。
圖7a展示一封裝之一分解透視圖。使用與圖5中相同之參考數字。第二基板54之電晶體結構整體展示為70,連接在接觸襯墊55a、55b之間。圖7a係一透視陰影視圖且圖7b將相同視圖展示為一線圖。
在所展示之實例中,閘極形成在第二基板之第一面中。一通孔經形成以實現自封裝端子(其等在第二基板之相對側上)至閘極之連接。
應注意,電晶體結構可在第二半導體基板54之底部表面上且在此情況中將無需用於閘極之通孔。
可更容易地製造配置。特定言之,在切割前,兩個基板之間之晶圓級接合係可行的。
如圖8中所示,兩個基板50、54可形成為全陣列。接著,執行兩個基板之間之晶圓接合。可行互連方法包含微凸塊或金奈米海綿。圖
8展示自上方觀看之一視圖,且展示頂部基板50之頂部處之切割線及底部基板54之頂部處之接觸襯墊。圖9展示自下方觀看之一視圖,且展示頂部基板50之底部處之LED接觸襯墊及底部基板54之底部處之封裝端子。
為避免由於熱膨脹而應力失配,晶圓級接合應避免高溫程序。在合適基板設計之情況下,可使用通常用於單一晶粒附著方法之超音波接合。或者,可應用冷互連方法,諸如導電膠合。
僅在晶圓級接合之後,分離個別LED或形成個別封裝之其他LED群組。已知用於3D封裝解決方案之使用矽穿孔技術之晶圓級連接。如針對第二基板54所展示,此等允許至一裝置之底部之接觸。
在上述實例中,將一並聯開關添加至各LED。當然,亦可以相同方式添加串聯開關。在此情況中,可無需至兩個LED端子之外部連接。代替性地,則需要至串聯電路之各端點以及電晶體閘極之連接。因此,三個封裝端子則可包括電晶體源極或汲極(未連接至LED者)、電晶體閘極及LED連接端子之僅一者。
電路係展示為一單一電晶體,但其可代替性地為一ESD二極體。當然,可在第二基板中提供更複雜電路。舉例而言,一ESD二極體可整合至封裝以及電晶體中。此外,可在各封裝中實施一更複雜電晶體控制電路,例如用於局部調光控制。
本發明大體上可用於形成LED封裝。用於需要控制個別LED之LED陣列之封裝尤其受關注。特定言之,在汽車應用中,已知用於提供光方向之動態控制之一動態LED矩陣陣列。
使用具有各LED之一電晶體使得多個串聯LED能夠個別地控制。本發明提供將一開關整合至LED封裝中LED正下方。此允許一緊密驅動器設計且簡化LED串之控制。
此外,該等組件可適用於自電源電壓驅動之多LED源,其中根據
電源電壓之相位控制跨LED之正向電壓。在一220V電源電壓網路中,實際電壓在+325V與-325V之間週期性地振盪。若一LED串含有具有約3V之一平均正向電壓之100個LED,則電源電壓可直接施加於該串而無過驅動LED之風險(實務上,此一電路將通常含有一整流器及一保護電阻器)。若所有LED一直保持在該串中,則個別LED處之電壓在電源循環時低於用於光產生之接通電壓。已知同步於減小電源電壓,可關斷增大數目個LED以允許剩餘LED有效率地提供光產生。
未詳細描述用於形成積體電路LED及積體電路電晶體之程序,此係因為該等程序係例行程序。實際上,可使用任何二極體技術及任何電晶體技術。此外,該等不同基板可使用不同材料及製造程序,此係因為該等基板係獨立形成。
自該等圖式、本發明及隨附申請專利範圍之一研究,熟習此項技術者在實踐本發明時可瞭解及實現所揭示實施例之其他變動。在申請專利範圍中,字詞「包括」並不排除其他元件或步驟,且不定冠詞「一」或「一個」並不排除複數個。某些措施在相互不同的附屬請求項中敘述,但僅就此事實,並不表示不能利用此等措施之組合以獲得好處。不應將申請專利範圍中之任意參考符號理解為限制範疇。
40‧‧‧發光二極體(LED)封裝
50‧‧‧第一半導體基板
52a‧‧‧發光二極體(LED)連接端子
52b‧‧‧發光二極體(LED)連接端子
54‧‧‧第二半導體基板
55a‧‧‧接觸襯墊
55b‧‧‧接觸襯墊
56a‧‧‧封裝端子
56b‧‧‧封裝端子
56c‧‧‧封裝端子/第三封裝端子
58a‧‧‧穿孔
58b‧‧‧穿孔
Claims (14)
- 一種形成一LED封裝之方法,其包括:形成積體電路LED(40)之一陣列作為一第一半導體基板(50)之部分;形成積體電路組件之一陣列作為一第二半導體基板(54)之部分;將該等第一及第二半導體基板(50、54)接合在一起,使得該第一半導體基板(50)之各LED(40)定位於該第二半導體基板之一或若干對應積體電路組件上方,藉此製成該LED與對應積體電路組件或若干對應積體電路組件之間之電連接;切割該等經接合之第一及第二半導體基板(50、54)以形成個別LED封裝或LED封裝之群組。
- 如請求項1之方法,其中形成積體電路組件之該陣列包括形成在該第二半導體基板之相對面之間延伸之穿孔(58a、58b)。
- 如請求項1或2之方法,其中形成積體電路組件之該陣列包括形成電晶體之一陣列。
- 如請求項1或2之方法,其中形成積體電路組件之該陣列包括形成二極體之一陣列。
- 一種LED封裝,其包括:一積體電路LED(40),其形成為一第一半導體基板(50)且在一面上具有LED連接端子(52a、52b);一積體電路,其形成為一第二半導體基板(54),其中將該第一半導體基板(50)之該一面及該第二半導體基板(54)之一第一面接合在一起,使得該第一半導體基板之該LED(40)定位於該積體電路上方且具有該LED與對應積體電路之間之電連接, 其中該封裝在該第二半導體基板(54)之與第一面相對之面上具有封裝端子(56a、56b、56c)且該第二基板具有提供一封裝端子與一LED連接端子之間之連接之至少一穿孔(58a、58b)。
- 如請求項5之封裝,其中該第二基板(54)具有提供各自封裝端子(56a、56b)與該兩個LED連接端子(52a、52b)之間之連接之至少兩個穿孔(58a、58b)。
- 如請求項5之封裝,其中該積體電路包括一ESD保護二極體。
- 如請求項5之封裝,其中該積體電路包括一電晶體。
- 如請求項8之封裝,其中該電晶體與該LED並聯。
- 如請求項9之封裝,其中該等封裝端子包括至該電晶體源極、汲極及閘極之連接。
- 如請求項8之封裝,其中該電晶體與該LED串聯。
- 如請求項11之封裝,其中該等封裝端子包括至該電晶體源極或汲極、該電晶體閘極及該等LED連接端子之一者之連接。
- 一種LED電路,其包括安裝於一印刷電路板上之至少一如請求項10之封裝,其中該印刷電路板具有用於連接至三個封裝端子之軌跡。
- 一種LED電路,其包括安裝於一印刷電路板上之至少一如請求項12之封裝,其中該印刷電路板具有用於連接至三個封裝端子之軌跡。
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