CN104126220A - 保形低温密闭性电介质扩散屏障 - Google Patents

保形低温密闭性电介质扩散屏障 Download PDF

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CN104126220A
CN104126220A CN201180076399.6A CN201180076399A CN104126220A CN 104126220 A CN104126220 A CN 104126220A CN 201180076399 A CN201180076399 A CN 201180076399A CN 104126220 A CN104126220 A CN 104126220A
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dielectric
diffusion barrier
layer
microelectronic component
dielectric material
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CN104126220B (zh
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S·金
俞辉在
S·科萨拉朱
T·格拉斯曼
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Intel Corp
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Abstract

本发明提供了适用作3D外形上方的电介质扩散屏障的保形密闭性电介质膜。在实施例中，电介质扩散屏障包括可通过原子层沉积ALD技术来沉积的诸如金属氧化物之类的电介质层，对于较薄的连续密闭性扩散屏障而言，通过原子层沉积ALD技术沉积的电介质层的保形度和密度大于通过PECVD工艺沉积的传统的基于二氧化硅的膜中可实现的保形度和密度。在其它实施例中，扩散屏障是例如双层的包括高k电介质层和低k或中等k电介质层的多层膜，以减小扩散屏障的介电常数。在其它实施例中，通过在保持较高的膜保形度和密度的同时调节硅酸盐的硅含量来将高k电介质层中的硅酸盐(例如金属硅酸盐)形成为减小扩散屏障的k值。

Description

保形低温密闭性电介质扩散屏障
技术领域
本发明的实施例总体上涉及半导体器件，更具体地，涉及保形电介质扩散屏障。
背景技术
诸如包含金属氧化物半导体晶体管(MOSFET)的集成电路等之类的微电子器件通过减小相邻特征之间的节距并且结合三维晶体管结构(例如，finFET(鳍式场效应晶体管))而不断缩小。随着晶体管的密度和非平面性增加以及互连金属化的增加，增大互连电容并且进行电隔离更加困难。最近十年的互连工艺越来越多地包含“低k”膜(例如，低于～3.2的膜)作为层间电介质(ILD)的选材，从而部分进一步实现了气隙形成，由此有意引入了相邻金属线之间的ILD内的空隙。另外，由于基本3D结构而导致外形会引起需要被保形电介质层密封/覆盖的空隙和/或缺陷。
等离子体增强化学气相沉积(PECVD)工艺通常用于低k互连应用中的电介质沉积，但没有提供高保形度/阶梯覆盖率。例如，PECVD低k膜通常具有小于55％的保形度(例如，仅仅对于沉积/蚀刻/沉积型顺序有接近75％的保形度)，其中，电介质在垂直(例如，侧壁)表面上沉积的厚度小于电介质在水平(例如，顶)表面上沉积的厚度的55％。CVD或低压CVD(LPCVD)技术提供了更高的保形度，但需要比低k互连应用通常允许的温度较高的温度。
常常期望的是，用电介质层提供密闭性密封，例如防止金属(例如，Cu)从金属互连线向外扩散进入周围的ILD材料，以及防止湿气和湿化学品从周围的ILD(或者从气隙形成工艺中的空隙)向内扩散进入3D结构(例如，金属线、晶体管等)中。由于难以在3D外形上实现完美覆盖率和膜致密度，导致因此需要电介质扩散屏障是最小厚度。
因此，用以减小电介质扩散屏障最小厚度的材料和技术是有利的。
附图说明
以举例方式而非限制方式说明了本发明的实施例，可以在结合附图进行考虑时参照下面的具体实施方式来更充分地理解本发明的实施例，其中：
图1是示出根据实施例的形成电介质扩散屏障的方法的流程图；
图2A、图2B、图2C、图2D、图2E、如2F和图2G示出了通过根据图1中示出的方法实施例构造的IC的横截面的侧视图；
图3A至图3B示出了根据本发明的实施例的电介质扩散屏障实施例的实验评价的线状图；以及
图4是可以结合根据图1和图2A至图2G所示的方法构造的IC的移动计算平台的功能框图。
具体实施方式
在下面的描述中，阐述了众多细节，然而，本领域的技术人员应当清楚，可在没有这些具体细节的情况下实践本发明。在一些情形下，公知的方法和装置是以框图形式而非以细节示出的，以避免混淆本发明。在整个本说明书中提及“实施例”意指结合实施例描述的具体的特征、结构、功能或特性包括在本发明的至少一个实施例中。因此，在整个本说明书中的多处出现短语“在实施例中”未必是指本发明的同一实施例。此外，在一个或多个实施例中，可按任何合适方式组合具体的特征、结构、功能或特性。例如，第一实施例和第二实施例可以在这两个实施例互不排他的情况下任意组合。
在本文中可使用术语“耦合”和“连接”连同它们的衍生词来描述组件之间的结构关系。应该理解，这些术语不旨在是彼此的同义词。确切地，在具体实施例中，“连接”可用于指示两个或更多个元件彼此直接物理或电接触。“耦合”可用于指示两个或更多个元件彼此直接或间接(其间有其它居间元件)物理或电接触，和/或两个或更多个元件彼此协作或相互作用(例如，如同因果关系一样)。
本文所用的术语“上方”、“下方”、“在…之间”和“上”是指一个材料层相对于其它层的相对位置。如此，例如，设置在另一个层上方或下方的一个层可直接接触另一个层或者可具有一个或多个居间层。此外，设置在两个层之间的一个层可直接接触这两个层或者可具有一个或多个居间层。与此相对，第二层“上”的第一层直接接触第二层。
本文描述的是适用于3D外形上的电介质扩散屏障的保形密闭性电介质膜。在实施例中，电介质扩散屏障是通过原子层沉积(ALD)技术沉积的电介质层，相比于能够具有不超过75％保形度的、(例如)通过PECVD或通过重复性的沉积/溅射等离子体增强化学气相沉积(PECVD)工艺沉积的传统基于二氧化硅/氮化物/碳化物的膜中可以实现的保形度，ALD针对较薄连续扩散屏障实现的保形度是至少95％。因为ALD电介质层可具有比这种PECVD膜相对更高的介电常数，所以可反直觉地在对电容敏感的结构中采用这种材料，然而，已发现某些“高k”电介质层材料的优异阶梯覆盖率和较大质量/原子密度能够得到厚度减小的密闭性扩散屏障。通常，此高质量和/或高原子密度意味着无(或非常低的)孔隙率，其中，屏障材料中的空隙的间隔是使得难以使原子扩散穿过屏障材料(即，更曲折的扩散路径)这样的小尺寸。
因此，针对扩散屏障，可以优选地进行仅仅具有中等好的阶梯覆盖率和密闭性的中等k膜与具有更好的阶梯覆盖率和密闭性的更高k膜之间的折衷。例如，在某些应用中，扩散屏障的厚度的这种减小通过增大了极低电介质可用的体积(例如，气隙的体积)而实现对结构(例如，互连ILD层)的电容的净减小。
在进一步的实施例中，扩散屏障的介电常数有利地减小，由此，屏障形成为包括相对高k ALD层和低k或中间k电介质层(例如，双层)的多层膜。在其它实施例中，相对高k ALD层中的硅酸盐被形成为利用ALD电介质的保形度和密度，但通过调节硅酸盐中的硅含量来降低扩散屏障的k值。
图1是示出根据实施例的用于形成电介质扩散屏障的方法100的流程图，在该实施例中，ILD中的互连金属化包含在同一金属层(例如，金属线)的相邻金属结构之间的气隙。电介质扩散屏障设置在金属线的气隙侧壁之间，用于保护互连金属化。虽然示例性的互连实施例用作可用的说明，但要注意，示例性互连背景下描述的电介质扩散屏障材料和沉积技术可应用于其中在苛刻3D外形上需要致密的保形密闭性电介质扩散屏障的许多其它背景下。例如，本领域的技术人员可容易地实现本文提供的教导，以形成设置在finFET上的扩散屏障、浅沟槽隔离区域的衬垫、光电子集成电路中的波导的钝化层等。本文提供的教导也可应用于诸如以双镶嵌结构形成非常薄的密闭性Cu盖帽层之类的一些2D应用。
方法100先开始操作110，形成低k ILD结构。图2A示出根据方法100的实施例构造的通过诸如微处理器或其它逻辑器件的集成电路(IC)的横截面的侧视图。在图2A中，IC的晶体管设置在衬底201中。衬底201可包括任何传统的半导体衬底(例如，硅、Ge、SiGe、SiC、GaAs、InP、GaN等)(无论是主体格式还是SOI格式)以及聚合物衬底(例如，TFT应用中)。设置在衬底201中的晶体管可以是任何传统的设计，例如但不限于平面或非平面MOSFET、平面或非平面高电子迁移率晶体管(HEMT)等。
在衬底201上方设置包括低k电介质层210的低k ILD结构，例如通过本领域已知的任何双镶嵌工艺在低k电介质层210中嵌入第一金属互连级205。在示例性实施例中，低k电介质层210是根据孔隙率其电介质常数的范围是2.5-3.2的碳掺杂的氧化物(SiOC:H)。当然，也可利用其它已知的低k ILD材料，事实上，在低k电介质层210的某些方面被牺牲(如本文其它地方讨论的)的示例性实施例中，还可以使用传统的中等k电介质材料(诸如，SiO2、PSG、BPSG、SiOF等)层取代低k电介质层210。在实施例中，各金属互连线205包括诸如钽(Ta)屏障层或TiN屏障层之类的屏障层和诸如铜(Cu)或钨(W)之类的填充金属。
继续进行方法100，在操作130中，在低k ILD中环绕金属互连部蚀刻出沟槽。通常，出于在金属互连线之间的间隔中引入空隙的缘故，操作130必须致使平面镶嵌层成为非平面的。正是这样引入了严格外形，该外形示例性地促使形成本文中描述的高度保形电介质扩散屏障。作为形成这种沟槽的一个示例，图2B示出通过在低k ILD结构上方沉积了硬掩模层220A之后的图2A中示出的集成电路(IC)的横截面的侧视图。硬掩模层220A可以是本领域已知的适于这种目的的任何材料，例如但不限于低k SiN:H、SiC:H、SiOC:H、SiCN:H或SiOCN:H(因为通常通过PECVD沉积硬掩模层220A，所以大量的氢被包含到膜中)。硬掩模层220A的厚度范围可以是约2-50nm并且材料的介电常数(k)的范围可以是4-7。在示例性实施例中，厚度约为8nm并且k约为4.8。值得注意，除了辅助进行图案化之外，硬掩模层220A还用于在构造期间保护金属互连部的顶表面免于被氧化和腐蚀。在示例性实施例中，硬掩模层220A是非牺牲性的，原位保留以使得金属互连部的(Cu)表面钝化并且因此应该具有好的附着性以使机械故障和电迁移故障最少。
继续进行操作130的示例性实现方式。图2C示出沉积附加的掩模层来形成多层掩模并且将多层掩模图案化。在硬掩模层220A上方设置第二硬掩模层220B，诸如(但不限于)非晶碳(α-C:H)、TiN或TaN。在第二硬掩模层220B上方的是任何传统的光致抗蚀剂220C和有机抗反射涂层(ARC)、和/或电介质ARC(DARC)220D，诸如(但不限于)像二氧化硅、氮化硅、掺杂碳的氧化物等的含硅材料。进行图案化，使得在低k电介质层210上方在两条相邻金属互连线(例如，205A和205B)之间的间隔中形成开口225。
图2D完成了操作130的示例性实现方式，其中，在设置于相邻金属互连线205A、205B之间的低k电介质210中蚀刻出了沟槽230。可利用诸如(但不限于)氟化化学品(CF4、C2F6、CF3H等)之类的任何基于等离子体的蚀刻剂来蚀刻出沟槽230，沟槽230从低k电介质层210的顶表面至少部分地延伸穿过(部分牺牲的)低k ILD层210，并且可完全延伸穿过低k电介质层210以暴露出衬底201。当然要理解，还可通过诸如(但不限于)离子铣削和激光消融的任何其它已知技术形成沟槽230。然后，使用本领域已知的干等离子体蚀刻和湿化学品清洗的任何组合(通常，通过在氧等离子体或氢等离子体之后进行湿清洗)，去除光致抗蚀剂220C、第二硬掩模层220B(例如TiN)和其它图案化材料。在完成操作130之后，如图2D中所示，低k ILD结构现在包括严格3D外形，其中，金属互连线(例如，Cu)环绕其中已被去除了部分低k电介质层210的嵌入金属互连线205内的沟槽(通孔)向上延伸。在实施例中，沟槽230在示例性实施例中具有至少5:1且大于7:1的高宽比。值得注意地，尽管在示例性实施例中硬掩模层220A保持为非牺牲层，但硬掩模层220A可能由于在蚀刻沟槽230期间进行的拐角倒圆而无法保持完好或者可能通过后续处理而被完全去除。
返回图1，方法100继续进行保形地沉积密闭性电介质扩散屏障。在示例性互连实施例中，图2E中的图示表明，电介质扩散屏障240在沟槽230中形成连续衬垫，跨越相邻金属互连线205A、205B之间的间隔并且同时覆盖硬掩模层220A。
在实施例中，利用ALD工艺来沉积密闭性电介质扩散屏障240的至少一部分。尽管ALD通常是本领域已知的，但在应用中受到因可接受前体的可用性造成的实际约束的限制，所述可接受前体能够进行自限制反应以形成期望组分的膜。因此，虽然某些前体的普遍可用性使得ALD能够变成形成栅电介质层的普及技术，但对于在典型互连隔离能力中采用的电介质材料而言，并非如此。为此原因，将等离子增强ALD(PEALD)(准ALD技术)作为沉积各式各样材料的方式进行研究，但通过这种技术制作的膜被发现仅在厚度大于约16nm时是均匀密闭性的，因此对于电介质扩散屏障而言，准ALD技术并不是特别有利。对于厚度小于5nm的密闭性屏障，只可以用PECVD/PEALD技术，在该技术中，因为在沉积处理或溅射处理期间通过离子轰击造成的膜的致密性，所以膜沉积在完全平坦的表面上。然而，因为这种离子轰击具有高度方向性，所以沉积在离子遮蔽表面(例如，接近垂直表面)上的膜具有较小的密度并且不是密闭性的。在本文描述的示例性实施例中，采用真实的ALD工艺形成厚度小于10nm(更具体地小于8nm，最具体地小于6nm)的密闭性的电介质扩散屏障。因为ALD工艺的高保形度(例如，95％或更大)，可以在严格3D外形(extreme 3Dtopography)上建立具有这些非常小的膜厚度的连续无针孔膜。
在实施例中，在沉积电介质扩散屏障240之前，通过PECVD来沉积电介质材料，以避免可能当直接暴露于ALD前体时而受到不利影响的金属互连线(例如，Cu)的任何所暴露的表面被直接暴露。如果硬掩模220A完全原位并且某个量的低k ILD保留在互连线侧壁上，则互连线的顶表面和衬垫会受到保护。然而，由于瑕疵，导致部分低k ILD可能没有保留在侧壁上并且顶部互连表面会暴露于对硬掩模220进行的拐角剪切、局部蚀刻或完全去除。另外，低k ILD是倾注屏障并且不管怎样互连衬垫(Ta/TaN)都仍有被氧化的可能性。适于此目的的示例性电介质材料包括但不限于SiN:H、SiCN:H、SiC:H、SiCO:H(例如，具有本文别处针对硬掩模层220A描述的介电常数范围)并且可通过PECVD来沉积至优选地小于2nm的厚度，但替代实施例包括将低k互连钝化膜沉积至更大的厚度(例如，4nm至16nm)。
在实施例中，密闭性电介质扩散屏障240的至少一部分是相比于基于硅的PECVD膜具有相对高的介电常数(例如，大于6)的ALD电介质材料。本领域已知的许多这种膜是可用ALD技术形成的并且通常可采用这些膜中的任何膜作为电介质扩散屏障240或作为电介质扩散屏障240的一部分。在示例性实施例中，高k电介质材料是全都具有大大超过10的介电常数的金属氧化物，诸如(但不限于)Al2O3、MgO2和HfO2。在替代实施例中可利用同时与ALD技术相容的诸如，TiO2、TaO2和ZrO2之类的其它过渡金属氧化物。
通过采用真实ALD技术，在操作140期间依次执行自限制反应。例如，可通过顺序地脉动三甲基(TMA)和H2O蒸气，沉积6-10nm的Al2O3作为电介质扩散屏障240，每个前体参与自限制反应，反复地形成非常保形的膜。在比LPCVD工艺中保形地沉积电介质所需的温度低的温度下，这些顺序的自限制反应为电介质扩散赋予了有利的高保形度。另外，有利地，铝原子是与邻近的氧原子形成大的紧密键合，以形成在厚度低于8nm且甚至低于6nm(例如，3-4nm)时能够具有密闭性的致密膜。虽然已通过实验验证了Al2O3的示例性实施例，但预期MgO2和HfO2具有类似的性能，还可预期本领域中已知的其它高k膜具有类似的性能以具有近似的原子密度。因此，在示例性实施例中，利用ALD来实现位于严格3D外形上方甚至厚度在5-10nm的范围内的连续电介质膜，在ALD技术中所采用的物质是形成能够以最小厚度提供密闭性的致密膜的物质，所述最小厚度是在当前外形上方形成物理连续膜所需的厚度。
虽然采用ALD电介质层的实施例当然可包括不止一种类型的电介质材料(例如，不同高k材料的双层)，但在示例性实施例中，ALD电介质层与介电常数比ALD材料的介电常数低的不同电介质材料层结合。在一个这样的实施例中，电介质扩散屏障240包括至少一种金属氧化物(诸如，Al2O3、MgO2和HfO2)和介电常数比金属氧化物的介电常数低但比周围的低k电介质层(例如，低k ILD210)的介电常数高的中等k材料。在示例性实施例中，中等k材料是SiON(C):H。在此实施例中，通过首先通过PECVD沉积SiO(C):H膜然后用包括氮源(例如，NH3、N2中的一种或多种)的等离子体溅射蚀刻该SiO(C):H膜来形成SiON(C):H层，所述等离子体溅射掉非保形沉积材料的部分并且将其重新分配到外形侧壁(例如，沟槽230的侧壁)上。虽然溅射蚀刻使SiOC:H膜致密并且包含形成SiON(C):H的氮，但这种膜自身在离子遮蔽表面上将不是密闭性的，除非超过15nm(例如，16nm和更大厚度)。然而，在ALD膜增强了密闭性并且这个中等k材料的介电常数在4.4-5.5的范围内的情况下，电介质扩散屏障240可具有减小的总电容。
在实施例中，SiON(C):H和ALD电介质形成双层，其中SiON(C):H形成第一层或者ALD电介质形成第一层。在示例性实施例中，双层电介质扩散屏障240包括SiON(C):H的第一层和设置在第一层上的作为第二层的ALD电介质。双层电介质扩散屏障240的示例性厚度在5nm和10nm之间，其中，SiON(C):H在3nm和6nm之间(例如，略大于电介质扩散屏障240的总厚度的一半)。在首先沉积电介质层(例如，SiOC:H)以在形成ALD电介质层之前使金属互连线钝化的一个实施例中，可通过执行基于氮的溅射蚀刻工艺来以钝化电介质层的一部分转换成更致密、更保形的SiON(C):H膜来将钝化电介质层的沉积物转变成电介质扩散屏障240的第一层。
在其它实施例中，电介质扩散屏障240是三层膜叠置体，在该三层膜叠置体中，ALD电介质材料设置在PECVD沉积膜(例如，如双层实施例的情况中一样的SiON(C):H的基体层和SiON(C):H的盖帽层)之间，这样可改善后续操作中沉积的上覆层中的附着和蚀刻分布。
在另一个实施例中，电介质扩散屏障240包括金属氧化物的硅合金。通过ALD形成示例性实施例中的金属氧化物的硅合金(与通过离散沉积的膜叠置体的固态扩散而形成的合金形成对照)。在一个这样的实施例中，至少一种金属氧化物与硅结合地沉积，形成保形金属硅酸盐膜。在这种实施例中，电介质扩散屏障240内所包含的硅的量被选择为范围在1％至90％(原子数)以实现电介质扩散屏障240的介电常数如期望地减小。例如，在金属氧化物是Al2O3的一个实施例中，引入硅来生成Al1-ySiyOx电介质膜。在一个示范性Al1-ySiyOx实施例中，硅含量是至少50％(原子数)以将合金的介电常数减小至低于7，同时在厚度小于15nm(优选地，小于10nm)时仍然提供密闭性密封。例如，在操作140期间，可在变化TMA和SiH4的占空比以实现期望硅含量的情况下执行TMA/H2O/SiH4/H2O的ALD顺序。在替代实施例中，可通过包含其它示例性金属氧化物(例如，MgO2、HfO2等)的类似ALD工艺制作其它金属硅酸盐。在替代实施例中，采用除了硅之外的其它合金物质来减小电介质扩散屏障240的介电常数。例如，可利用B2O3、BeO2、Li2O、Na2O中的任一种或多种。
如同金属氧化物层一样，电介质扩散屏障240中利用的合金化电介质除了包括ALD金属硅酸盐层之外还可包括底PECVD层和/或顶PECVD层。例如，金属硅酸盐层(Al1-ySiyOx)可设置在SiN:H、SiC:H、SiOC:H或SiCN:H膜上或者被SiN:H、SiC:H、SiOC:H或SiCN:H膜覆盖。作为另一个示例，金属硅酸盐层(Al1-ySiyOx)设置在SiN:H、SiC:H、SiOC:H或SiCN:H中的任一个的盖帽层层和基底层之间。
返回图1，方法100继续进行操作150，其中，非保形地沉积低k或中等k(例如，SiO2、PSG、BPSG、SiOF、聚合物等)ILD。在示例性互连实施例中，在操作150中进行这种非保形沉积，从而将在外形特征之间保留的间隔内生成气隙，以相对于图2A中示出的ILD结构减小互连电容。如图2F中所示，由于低k ILD250的非保形性，导致在沟槽230未被电介质扩散屏障240占据的区域中相邻的金属互连线205A、205B之间形成气隙255。因此，应该清楚，电介质扩散屏障240的厚度减小1个单位(例如，8nm)可使气隙255的宽度增大2个单位(例如，16nm)，因此导致电容的净改善(即，减小)，即使在电介质扩散屏障240内可一定程度地引入高k材料。
仍然参照图2F，在实施例中，低k ILD 250是介电常数在2.5-3.1的范围内的SiOC:H。在某些其它实施例中，低k ILD250是介电常数低于约2.5的多孔膜。如本领域中已知的，可采用化学-机械平面化(CMP)工艺来将低k ILD250的表面平面化。
返回图1，方法100继续进行操作160，在操作160中，用本领域中已知的传统处理和制造技术完成器件。例如，如图2G中所示，在低k ILD250中设置另外一层的金属互连部260。如所示出的，金属互连部260通过被金属(Cu)填充的通孔结合金属互连部205，所述通孔穿过电介质扩散屏障240和任何保留下来的硬掩模层220。然后，可在第二级金属互连部中形成另外的气隙，基本上如在操作110-150的内容中在本文中别处描述地一样。
图3A至图3B示出根据本发明的实施例的用于对电介质扩散屏障实施例进行实验评价的线状图。收集膜叠置体的应力测量值，所述膜叠置体包括厚吸湿氧化物上方的电介质扩散屏障处理，这样表示了通过晶圆翘曲度测得的与湿气含量相关的应力变化。图3A示出用作湿气扩散屏障(密闭性屏障)的6nm和更厚的Al2O3的ALD层的平坦线趋势。对于小于6nm的厚度，晶圆翘曲度随时间而变化，这表明湿气正在渗透Al2O3层。图3B是SiON(C):H/AlOx双层电介质扩散屏障的线状图。如可看出的，6nm的SiON(C):H层/2nm的AlOx层表现出极小的吸湿度。这表明形成保形屏障所需的高k Al2O3的厚度减小了超过60％，因此可有利地减小电容，同时仍然提供极薄的密闭性屏障(例如，8nm)。作为参考，需要至少14nm的SiON(C)来提供近似的结果。参照硅合金化的金属氧化物扩散屏障(例如，金属硅酸盐)的实施例，尽管在图线中没有明确描绘，但要注意，因为已发现氧含量是氮含量两倍的SiON层以保持与SiN组分等同的密闭性，所以预期的是，其中金属物质的高达50％被Si取代的金属硅酸盐(例如，铝硅酸盐、Al1-ySiyOx、镁硅酸盐(Mg1-ySiyOx)等)膜也将保持对应金属氧化物的密闭性。
图4示出根据本发明的一个实现方式的计算装置1000。计算装置1000容纳板1002。板1002可包括多个组件，包括(但不限于)处理器1004和至少一个通信芯片1006。处理器1004与板1002物理地电结合。在一些实现方式中，至少一个通信芯片1006也与板1002物理地电结合。在其它实现方式中，通信芯片1006是处理器1004的部分。
根据计算装置1000的应用，计算装置1000可包括可或不可与板1002物理地电结合的其它组件。这些其它组件包括(但不限于)易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪存存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、罗盘、加速计、陀螺仪、扬声器、相机和大容量存储装置(诸如，硬盘驱动器、压缩盘(CD)、数字通用盘(DVD)等)。
通信芯片1006能够进行无线通信，传递进出计算装置1000的数据。可使用术语“无线”及其衍生词来描述可通过使用穿过非固态介质的经调制电磁辐射进行数据通信的电路、装置、系统、方法、技术、通信信道等。所述术语不是意味着相关装置不包含任何布线，尽管在一些实施例中相关装置可不包含任何布线。通信芯片1006可实现多种无线标准或协议中的任一种，包括(但不限于)Wi-Fi(IEEE802.11系列)、WiMAX(IEEE802.16系列)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、Bluetooth(蓝牙)、其衍生物、以及被指定为3G、4G、5G和更高一代的任何其它无线协议。计算装置1000可包括多个通信芯片1006。例如，第一通信芯片1006可专用于诸如Wi-Fi和Bluetooth的较短距离无线通信并且第二通信芯片1006可专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO和其它的较长距离无线通信。
计算装置1000的处理器1004包括被封装在处理器1004内的集成电路晶粒。在本发明的一些实现方式中，处理器的集成电路晶粒包括一个或多个装置，诸如，如本文别处描述的其中设置有电介质扩散屏障的金属互连部。术语“处理器”可指处理来自寄存器和/或存储器的电子数据的任何装置或装置的一部分，用于将电子数据转变成可被存储在寄存器和/或存储器中的其它电子数据。
通信芯片1006还包括被封装在通信芯片1006内的集成电路晶粒。根据本发明的另一个实现方式，通信芯片的集成电路晶粒包括一个或多个器件，诸如，如本文别处描述的其中设置有电介质扩散屏障的金属互连部。
在其它实现方式中，被容纳在计算装置1000内的另一个组件可包含集成电路晶粒，所述集成电路晶粒包括一个或多个器件，诸如，如本文别处描述的其中设置有电介质扩散屏障的金属互连部。
在各种实现方式中，计算装置1000可以是膝上型计算机、网本、笔记本、超级本、智能电话、平板、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器或数字录像机。在其它实现方式中，计算装置1000可以是处理数据的任何其它电子装置。
以上的描述是示例性的，并非限制性的。例如，虽然附图中的流程图示出了通过本发明的某些实施例执行的特定次序的操作，但应该理解，并非要求这种次序(例如，替代实施例可按不同次序执行操作，组合某些操作，交叠某些操作等)。此外，在阅读和理解了以上描述后，许多其它实施例对于本领域的技术人员而言是显而易见的。尽管已经参照具体示例性实施例描述了本发明，但应当认识到，本发明不限于描述的实施例，而可以在所附权利要求书的精神和范围内进行修改和变化的情况下实践本发明。因此，应该参照所附权利要求书连同该权利要求书的等同形式的全部范围来确定本发明的范围。

Claims (20)

1.一种微电子器件，所述微电子器件包括：
设置在衬底上方的一对相邻的金属互连线，所述一对互连线分隔开一间隔；
低k层间电介质(ILD)材料，所述低k层间电介质材料设置在所述金属互连线之间的所述间隔中；
气隙，所述气隙设置在所述ILD材料内；以及
连续电介质扩散屏障，所述连续电介质扩散屏障跨越所述间隔并设置在所述气隙与所述金属互连线中的每条金属互连线的侧壁之间，其中，所述电介质扩散屏障包括金属物质和氧。
2.根据权利要求1所述的微电子器件，其中，所述电介质扩散屏障是进一步包括硅的金属硅酸盐。
3.根据权利要求2所述的微电子器件，其中，所述金属硅酸盐是铝硅酸盐(Al1-ySiyOx)或镁硅酸盐(Mg1-ySiyOx)。
4.根据权利要求1所述的微电子器件，其中，所述电介质扩散屏障包括介电常数至少为10的高k电介质材料层。
5.根据权利要求4所述的微电子器件，其中，所述高k电介质材料层的厚度小于8nm。
6.根据权利要求4所述的微电子器件，其中，所述高k电介质材料层包括Al2O3、MgO2和HfO2中的至少一种。
7.根据权利要求6所述的微电子器件，其中，所述高k电介质材料层实质上由Al2O3、MgO2和HfO2中的一种组成。
8.根据权利要求4所述的微电子器件，其中，所述电介质扩散屏障是多层膜叠置体，所述多层膜叠置体进一步包括：
中等k电介质材料层，所述中等k电介质材料层的介电常数低于所述高k电介质材料的介电常数且高于所述低k电介质材料的介电常数。
9.根据权利要求8所述的微电子器件，其中，所述电介质扩散屏障的厚度小于10nm。
10.根据权利要求8所述的微电子器件，其中，所述中等k电介质材料包括碳掺杂的氮氧化硅(SiON(C):H)并具有小于4nm的厚度。
11.一种制造微电子器件的方法，所述方法包括：
在衬底上方形成一对相邻的金属互连线，所述一对互连线分隔开一间隔；
在低k层间电介质(ILD)材料内形成气隙，所述低k层间电介质(ILD)材料设置在所述金属互连线之间的所述间隔中；以及
形成连续电介质扩散屏障，所述连续电介质扩散屏障跨越所述间隔并且设置在所述气隙与所述金属互连线中的每条金属互连线的侧壁之间，其中，形成所述扩散屏障包括利用原子层沉积(ALD)工艺来沉积电介质层。
12.根据权利要求11所述的方法，其中，沉积所述电介质层包括沉积高k电介质材料层，所述高k电介质材料层的介电常数在8和10之间。
13.根据权利要求12所述的方法，其中，所述高k电介质材料层本质上由Al2O3、MgO2和HfO2中的一种组成。
14.根据权利要求11所述的方法，进一步包括通过在执行所述高k电介质材料的所述ALD之前执行SiCN:H、SiC:H或SiOC:H膜的PECVD沉积来使所述一对金属互连线的暴露出的表面钝化。
15.根据权利要求12所述的方法，其中，形成所述电介质扩散屏障进一步包括将所述高k电介质材料与硅合金化，以形成介电常数低于7的金属硅酸盐。
16.根据权利要求15所述的方法，其中，将所述高k电介质材料与硅合金化进一步包括：利用ALD工艺来周期性沉积Al2O3层和SiO2层以形成铝硅酸盐(AlySi1-yOx)，或者利用ALD工艺来周期性沉积MgO2层和SiO2层以形成镁硅酸盐(MgySi1-yOx)。
17.根据权利要求11所述的方法，其中，形成所述电介质扩散屏障进一步包括：通过PECVD来沉积中等k电介质材料层，所述中等k电介质材料层的介电常数低于所述高k电介质材料的介电常数且高于所述低k电介质材料的介电常数。
18.根据权利要求17所述的方法，其中，所述电介质扩散屏障被沉积至小于10nm的厚度，并且其中，所述中等k电介质材料包括碳掺杂的氮氧化硅。
19.根据权利要求11所述的方法，其中，形成跨越所述间隔的所述连续电介质扩散屏障进一步包括：
在设置于所述一对金属互连线之间的第一层低k ILD中蚀刻出沟槽；以及
利用所述电介质扩散屏障装衬所述沟槽，
其中，形成所述气隙进一步包括利用非保形工艺来沉积第二ILD层。
20.根据权利要求11所述的方法，进一步包括：蚀刻出穿过所述电介质扩散屏障的设置在所述互连金属线中的一条互连金属线上方的区域的开口，以及通过所述开口形成第二级金属互连过孔。
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