CN104022085B - 一种基板 - Google Patents

一种基板 Download PDF

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CN104022085B
CN104022085B CN201310066146.1A CN201310066146A CN104022085B CN 104022085 B CN104022085 B CN 104022085B CN 201310066146 A CN201310066146 A CN 201310066146A CN 104022085 B CN104022085 B CN 104022085B
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solder resist
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CN104022085A (zh
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李怡增
谢佑灵
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Advanced Micro Devices Shanghai Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0237High frequency adaptations
    • H05K1/024Dielectric details, e.g. changing the dielectric material around a transmission line
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036Multilayers with layers of different types
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0058Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0206Materials
    • H05K2201/0209Inorganic, non-metallic particles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/0959Plated through-holes or plated blind vias filled with insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

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Abstract

本发明涉及一种基板,包括增层和设置在该增层上的阻焊层,该阻焊层具有背向该增层的上表面,该阻焊层在其上表面上具有多个凹槽。该阻焊层的上表面上的凹槽能更好地消除或减轻由该基板的材料的热膨胀系数的不匹配所引起的在大的阻焊区域所累积的应力,因而能够阻止和减小基板的翘曲。

Description

一种基板
技术领域
本发明总体涉及半导体技术,包括倒装芯片技术。具体地,本发明涉及一种基板,具体是涉及基板的阻焊层上的应力减轻图案。
背景技术
在芯片封装技术领域,芯片通常被安装在基板上,基板通常包括增层和设置在增层上的阻焊层,现有的基板的增层上的阻焊层的图案为连续的平板形式。图1显示了一种现有的基板100,其中增层102上的阻焊层101的图案为连续的平板。然而这种类型的阻焊层图案有多种缺陷。例如,基板与安装在其上的芯片之间的热膨胀系数(CTE)的不匹配会引起高的应力,而且这种连续的平板形图案的阻焊层不利于减小累积在大的阻焊层区域的应力,以缓和由该基板的材料热膨胀系数的不匹配所引起的应力,这会导致该基板更容易产生翘曲。此外,现有技术中的这种图案的阻焊层不利于降低由芯片和基板之间的热膨胀系数的不匹配所可能引发的芯片破裂风险。
因此,希望提供一种具有改善的阻焊层图案的基板,以消除或缓和现有技术中的上述缺陷。
发明内容
为了克服现有技术中的上述缺陷,本发明提供了一种基板,其具有改善的阻焊层图案,从而具有更好的性能。
具体地,本发明的一些示例性实施方式提供了一种基板,包括增层和设置在该增层上的阻焊层,该阻焊层具有背向该增层的上表面,该阻焊层在其上表面具有多个凹槽。
在一些实施方式中,该多个凹槽之间相互平行。
在一些进一步的实施方式中,该多个相互平行的凹槽具有多个延伸方向。
在一些进一步的实施方式中,该多个凹槽包括第一凹槽组和第二凹槽组,其中该第一凹槽组包括多个相互平行的第一凹槽,该第二凹槽组包括多个相互平行的第二凹槽,其中该多个相互平行的第一凹槽与该多个相互平行的第二凹槽相交。
在一些进一步的实施方式中,该多个相互平行的第一凹槽与该多个相互平行的第二凹槽之间的交角可以是0°至90°之间的任何角度。优选为90°。
在一些进一步的实施方式中,所述多个凹槽由多个阻焊剂路径限定,其中每两个相邻的凹槽之间的阻焊剂路径是连续的。
在一些进一步的实施方式中,所述多个凹槽由多个阻焊剂路径限定,其中每两个相邻的凹槽之间的阻焊剂路径是不连续的。
在一些进一步的实施方式中,所述不连续的阻焊剂路径包括多个相互隔开的圆柱形阻焊剂凸点。
在一些进一步的实施方式中,所述不连续的阻焊剂路径包括多个相互隔开的棱柱形阻焊剂凸点。
在一些进一步的实施方式中,所述不连续的阻焊剂路径包括多个相互隔开的立方体形阻焊剂凸点。
在一些进一步的实施方式中,所述不连续的阻焊剂路径包括多个相互隔开的圆柱形、立方体形和/或棱柱形阻焊剂凸点。
通过提供本发明的上述基板,克服了上述提到的在现有的基板的缺陷。
附图说明
附图以示例的方式图示了本发明,其并不构成对本发明的限制。在附图中相同的数字表示相同的部件,其中:
图1为现有的基板中的阻焊层图案的侧视示意图;
图2为根据一种示例性实施方式的基板的俯视示意图;
图3为图2所示的基板的侧视示意图;
图4为根据另一种示例性实施方式的基板的俯视示意图;
图5为根据另一种示例性实施方式的基板的俯视示意图;
图6为图2-5中所示的阻焊剂路径的示例性实施方式的部分放大示意图;
图7为图2-5中所示的阻焊剂路径的另一种示例性实施方式的部分放大示意图;
图8为图2-5中所示的阻焊剂路径的另一种示例性实施方式的部分放大示意图;
图9为图2-5中所示的阻焊剂路径的另一种示例性实施方式的部分放大示意图;
图10为图2-5中所示的阻焊剂路径的另一种示例性实施方式的部分放大示意图。
具体实施方式
下面将参照附图中所示的一些实施例具体描述本发明的一些示例性实施方式。在下文的描述中,描述了一些具体的细节以提供对本发明的更深的理解。然而,对于本领域的技术人员来说显而易见的是,即使不具有这些具体细节中的一些,本发明也可被实施。另一方面,一些公知的工艺步骤和/或结构没有被详细描述以避免不必要地使本发明变得难以理解。此外,在实施例的详细描述中,方向术语,例如“顶部”、“底部”、“前”、“后”、“侧部”、“左”、“右”、“向前”“向后”等是参考附图中的方向而使用的。由于本发明的实施例中的部件能够以多个不同的方向而被放置,因此,所述方向术语的使用是为了说明而不是为了限制本发明。
参见图2-3,分别显示了一种示例性实施方式的基板200的俯视示意图和侧视示意图。如图2-3所示,基板200包括增层202和阻焊层203。该基板200的C4区域201用于安装芯片。该阻焊层203设置在增层202上并具有背向该增层202的上表面。该阻焊层203在其上表面具有多个凹槽204。所述多个凹槽204由多条阻焊剂路径205限定,也就是说,在每两个相邻的凹槽204之间具有一条阻焊剂路径205。在图2-3中,该多个凹槽204是相互平行的;然而,这不是必须的,该多个凹槽204也可以是不平行的。此外,该多个凹槽204的延伸方向可以是任意的。例如,图4显示了具有不同于图3所示的延伸方向的多个相互平行的凹槽404的实施例。
参见图5,其示出了另一实施方式的基板500的俯视示意图。如图5所示的基板500,其具有设置在阻焊层的上表面上的两个凹槽组,即第一凹槽组501和第二凹槽组502。该第一凹槽组501包括多个相互平行的第一凹槽503。该第二凹槽组502包括多个相互平行的第二凹槽504。该多个相互平行的第一凹槽503与该多个相互平行的第二凹槽504相交。图5所示的该多个相互平行的第一凹槽503与该多个相互平行的第二凹槽504相交的交角为90°。但是,该交角也可以是0°至90°之间的任何角度。
参见图6-10,其示出了图2-5所示的阻焊剂路径的示例性实施例的局部放大视图。在图6中,阻焊剂路径605是连续的。在图7-10中,阻焊剂路径705、805、905和1005是不连续的。具体地,图7所示的阻焊剂路径705包括多个相互间隔的圆柱形阻焊剂凸点709。图8所示的阻焊剂路径805包括多个相互间隔的立方体形阻焊剂凸点809。图9所示的阻焊剂路径905和图10所示的阻焊剂路径1005分别包括多个相互间隔的棱柱形阻焊剂凸点909和1009,其中图9所示的棱柱形阻焊剂凸点909的边数是4,图10所示的棱柱形阻焊剂凸点1009的边数是5。当然,该棱柱形阻焊剂凸点909或1009也可以由其它的边数。
在如上所述的基板中,由于阻焊层的上表面具有多个凹槽,这能够更好地消除或减轻由该基板的材料的热膨胀系数的不匹配所引起的在大的阻焊区域所累积的应力,因而能够阻止和减小基板的翘曲。此外,本发明的基板还能够减小由芯片和基板的热膨胀系数的不匹配所引起的芯片破裂的风险。
对于本领域的技术人员来说显而易见的是,可以在不背离本发明的精神和权利要求的范围的情况下对本发明作不同的修改和变型。因此,如果对本发明的修改和变型落入了权利要求和它们的等同物的范围内,那么应当认为本发明覆盖了对本发明所描述的不同实施例的修改和变型。

Claims (6)

1.一种基板,包括增层和设置在该增层上的阻焊层,该阻焊层具有背向该增层的上表面,该阻焊层在其上表面上具有多个凹槽,其中所述凹槽由多条阻焊剂路径限定在所述增层上,其中所述多个凹槽由多条阻焊剂路径限定,其中位于每两个相邻凹槽之间的阻焊剂路径是不连续的,并且所述不连续的阻焊剂路径包括多个相互隔开的圆柱形、立方体形和/或棱柱形阻焊剂凸点。
2.根据权利要求1所述的基板,其中所述多个凹槽相互平行。
3.根据权利要求2所述的基板,其中所述多个平行的凹槽可在任何方向上延伸。
4.根据权利要求1所述的基板,其中所述多个凹槽包括第一凹槽组和第二凹槽组,该第一凹槽组包括多个相互平行的第一凹槽,该第二凹槽组包括多个相互平行的第二凹槽,其中所述多个相互平行的第一凹槽与所述多个相互平行的第二凹槽相交。
5.根据权利要求4所述的基板,其中所述多个相互平行的第一凹槽与所述多个相互平行的第二凹槽相交的交角为0°至90°。
6.根据权利要求5所述的基板,其中所述交角为90°。
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CN105657975B (zh) * 2014-12-03 2019-04-05 北大方正集团有限公司 电路板的制作方法和电路板
CN105347292A (zh) * 2015-11-13 2016-02-24 华天科技(昆山)电子有限公司 可缓解盖板应力的mems封装结构及其封装方法
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CN110600416A (zh) * 2018-06-12 2019-12-20 上海新微技术研发中心有限公司 一种薄片基板的加工方法
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