CN103972206A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN103972206A
CN103972206A CN201410043235.9A CN201410043235A CN103972206A CN 103972206 A CN103972206 A CN 103972206A CN 201410043235 A CN201410043235 A CN 201410043235A CN 103972206 A CN103972206 A CN 103972206A
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weld pad
film
semiconductor device
peripheral
wiring
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上村启介
小山内润
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Seiko Instruments Inc
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Abstract

本发明提供防止向内部电路的水分浸入的半导体装置。该半导体装置包括在焊垫下层形成的衬底多晶硅膜(10),衬底多晶硅膜(10)上方通过层间绝缘膜(21)而设置的焊垫(1),以包围焊垫(1)的外侧的方式配置的外围布线(3),其中外围布线(3)与衬底多晶硅膜(10)通过连续的外围接触件来连接,由此阻断从焊垫通向内部电路的水分。

Description

半导体装置
技术领域
本发明涉及半导体装置,尤其涉及具有焊垫的半导体装置。
背景技术
半导体装置为了保证长期可靠性,必须通过各种可靠性应力测试。例如,一般进行在85oC、85%的条件下进行的高温高湿偏压测试、在125oC、85%、2个大气压的条件下进行的压力锅偏压测试等将高温高湿以及偏压组合的测试。这些测试鉴于在市场中的使用环境由JEDEC标准等来决定,是为了使在市场中不发生问题而考虑出的测试。这些测试是用于保证在市场中的长期可靠性的基本指标,为了不让市场中的不良状况发生,这些测试也是需要的。
在这些高温高湿测试中,存在通过封装树脂的水分从垫等的开口部分向芯片内部浸入,通过引起电化学的反应而引起布线的氧化,由于体积膨胀或界面剥离而发生可靠性问题的情况。为了防止这些,通过在焊垫的周围部位中将垫上的氮化钛膜去除为环状或者槽状的部分来防止水分的浸入的发明已被公开。(例如,参考专利文献1)
现有技术文献
专利文献
专利文献1:日本特开2010-251537号公报。
发明内容
发明要解决的问题
要解决的问题,如下所示:
如上所述,在高温高湿测试中,存在通过封装树脂的水分从垫等的开口部分向芯片内部浸入,通过引起电化学的反应而引起布线的氧化,由于体积膨胀或界面剥离而发生可靠性问题的情况。作为这些问题的对策,考虑了通过封装树脂的创意、垫结构的创意来防止水分向芯片浸入的对策。但是,这些对策有并不完善的情况。虽然水分不通过氮化膜、铝布线等,但是水分传入氧化膜中和氧化膜与铝布线膜的界面等而向芯片内部浸入。作为这种现象的对策需求通过某些手段来阻断这些进入途径。
解决问题的方案
本发明的半导体装置鉴于上述问题,采用以下方案:
首先,提供一种包括焊垫的半导体装置,其特征在于,包括:半导体基板上的氧化膜;所述氧化膜上的导电性非透水膜;在所述导电性非透水膜上方通过层间绝缘膜而设置的焊垫;连接所述焊垫和内部电路的金属布线;在所述焊垫周围隔开而配置的外围布线;以及沿所述外围布线配置的,电连接所述外围布线和所述导电性非透水膜的接触件。
另外,所述半导体装置的特征在于:所述金属布线与所述外围布线交叉,所述焊垫与所述导电性非透水膜电连接,所述焊垫与所述外围布线等电位。
另外,所述半导体装置的特征在于:所述外围布线在平面视图中为C字型形状,所述金属布线通过所述C字型的缝隙连接到内部电路,所述焊垫和所述外围布线不等电位。
另外,所述半导体装置的特征在于:所述导电性非透水膜是多晶硅膜或者金属膜。
另外,所述半导体装置的特征在于:所述接触件由与内部电路中使用的钨塞同直径的部件连续连接而配置。
进一步,提供一种包括焊垫的半导体装置,其特征在于,包括:
半导体基板上的氧化膜;包围所述氧化膜,并设置在所述半导体基板表面的外围杂质扩散层;在所述氧化膜和所述外围杂质扩散层上方通过层间绝缘膜而设置的焊垫;连接所述焊垫和内部电路的金属布线;在所述焊垫周围隔开而配置的外围布线;以及沿所述外围布线配置的,电连接所述外围布线和所述外围杂质扩散层的接触件。
另外,所述半导体装置的特征在于:所述金属布线与所述外围布线交叉,所述焊垫与所述外围杂质扩散层电连接,所述焊垫与所述外围布线等电位。
另外,所述半导体装置的特征在于:所述外围布线在平面视图中为C字型形状,所述金属布线通过所述C字型的缝隙连接到内部电路,所述焊垫和所述外围布线不等电位。
另外,所述半导体装置的特征在于:所述接触件由与内部电路中使用的钨塞同直径的部件连续连接而配置。
发明的效果
通过上述方案,能够阻断半导体装置可靠性测试时的水分浸入,能够实现可靠性高的半导体装置。
附图说明
图1是示出本发明涉及的半导体装置的第1实施例的平面图和截面图;
图2是示出本发明涉及的半导体装置的第2实施例的平面图和截面图;
图3是示出本发明涉及的半导体装置的第3实施例的平面图和截面图;
图4是示出本发明涉及的半导体装置的第4实施例的平面图和截面图;
图5是示出本发明涉及的半导体装置的第5实施例的平面图和截面图;
图6是示出本发明涉及的半导体装置的第6实施例的平面图和截面图。
具体实施方式
以下基于附图说明本发明的实施方式。
实施例1
用图1说明本发明的第1实施例。图1(a)是平面图,图1(b)是图1(a)的A-A中的截面图。
如图1所示,在半导体基板上的氧化膜30上将导电性且非透水性的衬底多晶硅膜(或者多晶硅化物(ポリサイド)膜)10设置在确定的位置。这里,氧化膜30可以是LOCOS氧化膜,如果没有电气方面的问题也可以是像栅极氧化膜那样的薄氧化膜。在衬底多晶硅膜10上,通过覆盖衬底多晶硅膜10的上表面和侧面的层间绝缘膜21,配置由与衬底多晶硅膜10相比更小的金属膜构成的焊垫1。如图1(a)的平面图所示,焊垫1整个配置在衬底多晶硅膜10的内侧。焊垫1连接有由同层的金属膜构成的金属布线2,该金属布线2为延伸而连接到内部电路的结构。这里,金属布线2利用铝布线或铜布线,根据需要可为层叠金属阻挡膜、层叠防反射膜的结构。
焊垫1的周围,进一步在衬底多晶硅膜10的上方形成由与焊垫1隔开的同层的金属膜构成的外围布线3,该外围布线3与从焊垫1延伸的金属布线2交叉。因此,该情况下焊垫1与外围布线3为等电位。外围布线3通过其正下方以沿外围布线一周的方式形成的外围接触件20,与下方的衬底状多晶硅膜10电连接。外围接触件20可以是在连续的外围槽中埋入外围布线3的一部分的结构,也可以是由钨塞构成的结构。在钨塞的情况下,由于需要以具有与内部电路中所使用的形状相同的形状的小直径塞来进行统一,所以可能无法采用在连续的槽中埋入钨的结构。该情况下,邻接的小直径塞彼此在其侧面相接,分割外围接触件20的内外层间绝缘膜地配置。此外,也可以是在与小直径塞的直径相比宽度更加窄的外围槽中埋入钨的结构。这是通过与小直径塞相比为更加窄的宽度而使钨完全填充的结构。另外,虽然未进行图示,但是以焊垫1的一部分进行开口的方式将其它部分以氮化硅膜进行覆盖。
通过成为如以上的结构,到达焊垫附近的水分由于非透水性的外围布线3、外围接触件20以及衬底多晶硅膜10而无法向焊垫区域之外即内部回路浸入,能够进行对于内部电路的水分的阻断。由此,能够成为高可靠性的半导体装置。
实施例2
用图2说明本发明的第2实施例。图2(a)是平面图,图2(b)是图2(a)的A-A中的截面图。
与第1实施例的不同是,外围布线3和外围接触件20构成的外围结构与焊垫没有进行电连接这一点。
本发明的半导体装置在截面视图中,在半导体基板上的氧化膜30上设置导电性且非透水性的衬底多晶硅膜(或者多晶硅化物(polycide)膜)10。这里,氧化膜30可以是LOCOS氧化膜,如果没有电气方面的问题也可以是像栅极氧化膜那样的薄氧化膜。通过覆盖衬底多晶硅膜10的上表面和侧面的层间绝缘膜21,设置由金属膜构成的焊垫1。焊垫1连接有由同层的金属膜构成的金属布线2,该金属布线2为连接到内部电路的结构。这里,金属布线2利用铝布线、铜布线,根据需要可为层叠金属阻挡膜、层叠防反射膜的结构。焊垫1的周围,形成与焊垫1隔开的同层金属膜构成的不平整的C字型外围布线3。从焊垫1延伸的金属布线2与外围布线3隔开,金属布线2通过外围布线3的C字的缝隙连接到内部电路。该情况下,焊垫1与外围布线3可为不等电位,外围布线3可以是电源电位,也可以是接地电位。也可以是根据情况电气地进行浮动,即浮动电位,也可以固定在某些电位。
外围布线3通过其正下方形成的外围接触件20,与下方的衬底状多晶硅膜10电连接。外围接触件20可以是在连续的外围槽中埋入外围布线3的一部分的结构,也可以是由钨塞构成的结构。在钨塞的情况下,由于需要以与内部电路中所使用的形状相同的小直径塞来进行统一,所以可能无法采用在连续的槽中埋入钨的结构。该情况下,邻接的小直径塞彼此在其侧面相接,分割外围接触件20的内外层间绝缘膜地配置。此外,也可以是在与小直径塞的直径相比宽度更加窄的外围槽中埋入钨的结构。这是通过与小直径塞相比为更加窄的宽度而使钨完全填充的结构。另外,虽然未进行图示,但是以焊垫1的一部分进行开口的方式以氮化硅膜进行覆盖。
在成为如以上的结构的情况下,因为外围布线的一部分被切断,所以与实施例1相比差一点,但还是成为到达焊垫附近的水分由于非透水性的外围布线3、外围接触件20以及衬底多晶硅膜10而难以向焊垫区域之外即内部回路浸入的结构,能够进行对于内部电路的水分的阻断。由此,能够成为高可靠性的半导体装置。
实施例3
用图3说明第3实施例。图3(a)是平面图,图3(b)是图3(a)的A-A中的截面图。
与第1实施例的不同是,代替衬底多晶硅膜10使用导电性且非透水性的衬底金属膜50这一点。通过使用金属膜而更加牢固地阻断水分,是与实施例1的结构相比可靠性更高的结构,在多层布线结构的半导体装置中即为本实施例的结构。
实施例4
用图4说明第4实施例。图4(a)是平面图,图4(b)是图4(a)的A-A中的截面图。
与第2实施例的不同是,代替衬底多晶硅膜10使用导电性且非透水性的衬底金属膜50这一点。通过使用金属膜而更加牢固地阻断水分,是与实施例2的结构相比可靠性更高的结构,在多层布线结构的半导体装置中即为本实施例的结构。此外,本实施例的半导体装置中能够任意变更外围布线的电位。
实施例5
用图5说明第5实施例。图5(a)是平面图,图5(b)是图5(a)的A-A中的截面图。
与第1实施例的不同是,代替衬底多晶硅膜10,配置有在半导体基板上形成的外围杂质扩散层40及其内围的LOCOS氧化膜30这一点。外围杂质扩散层40和外围布线3由外围接触件20来连接,外围接触件20将层间绝缘膜21分割为内外。焊垫1通过外围布线3与外围杂质扩散层40电连接。这里由于使外围杂质扩散层40的导电类型与周围的阱或者半导体基板的导电类型不同,而使焊垫通过反向连接的二极管与电源电平(VDD)或者接地电平(VSS)连接。如果使外围杂质扩散层40的导电类型与周围的阱或者半导体基板的导电类型相同,则焊垫的电位能够固定在电源电平(VDD)或者接地电平(VSS)。该结构能够用于与基板或者阱等电位的焊垫。
实施例6
用图6说明第6实施例。图6(a)是平面图,图6(b)是图6(a)的A-A中的截面图。
与第2实施例的不同是,代替衬底多晶硅膜10,配置有在半导体基板上形成的外围杂质扩散层40及其内围的LOCOS氧化膜30这一点。将外围杂质扩散层40和外围布线3与外围接触件20连接。虽然连接到杂质扩散层,但是与实施例5不同,并非从焊垫直接布线到基板扩散层,因此能够对焊垫1施加任意的电位或者使焊垫1输出任意的电位。当然,外围布线3的电位受到制约,或者与基板或阱等电位,或者通过反向连接的二极管与基板或者阱的电位连接。
附图标记
1 焊垫
2 金属布线
3 外围布线
10 衬底多晶硅膜(或者多晶硅化物膜)
20 外围接触件
21 层间绝缘膜
30 氧化膜
40 外围杂质扩散层
50 衬底金属膜。

Claims (9)

1.一种半导体装置,其特征在于包括:
半导体基板;
设置在所述半导体基板上的氧化膜;
设置在所述氧化膜上的导电性非透水膜;
在所述导电性非透水膜的上方通过层间绝缘膜而设置的,与所述导电性非透水膜相比更小的焊垫;
连接所述焊垫和内部电路的金属布线;
在所述焊垫的周围、所述导电性非透水膜的上方从所述焊垫隔开而配置的外围布线;以及
沿所述外围布线的一周而配置,将所述外围布线和所述导电性非透水膜电连接,将所述层间绝缘膜分割为内外的接触件。
2.根据权利要求1所述的半导体装置,其特征在于:
所述金属布线与所述外围布线交叉,所述焊垫与所述导电性非透水膜电连接,所述焊垫与所述外围布线等电位。
3.根据权利要求1所述的半导体装置,其特征在于:
所述外围布线在平面视图中为C字型形状,所述金属布线通过所述C字型的缝隙连接到内部电路,所述焊垫与所述外围布线不等电位。
4.根据权利要求1-3中任何一项所述的半导体装置,其特征在于:
所述导电性非透水膜是多晶硅膜或者金属膜。
5.根据权利要求1-4中任何一项所述的半导体装置,其特征在于:
所述接触件连续地配置,以使与内部电路中使用的钨塞为同直径的部件相互在侧面相接。
6.一种半导体装置,其特征在于包括:
半导体基板;
所述半导体基板上的氧化膜;
包围所述氧化膜,并设置在所述半导体基板表面的外围杂质扩散层;
在所述氧化膜的上方通过层间绝缘膜而设置的,与所述氧化膜相比更小的焊垫;
连接所述焊垫和内部电路的金属布线;
在所述焊垫周围、所述外围杂质扩散层之上从所述焊垫隔开而配置的外围布线;以及
沿所述外围布线的一周而配置,将所述外围布线和所述外围杂质扩散层电连接,将所述层间绝缘膜分割为内外的接触件。
7.根据权利要求6所述的半导体装置,其特征在于:
所述金属布线与所述外围布线交叉,所述焊垫与所述外围杂质扩散层电连接,所述焊垫与所述外围布线等电位。
8.根据权利要求6所述的半导体装置,其特征在于:
所述外围布线在平面视图中为C字型形状,所述金属布线通过所述C字型的缝隙连接到内部电路,所述焊垫与所述外围布线不等电位。
9.根据权利要求6-8中任何一项所述的半导体装置,其特征在于:
所述接触件由与内部电路中使用的钨塞为同直径的部件连续连接而配置。
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