CN100536120C - 半导体芯片及其制造方法 - Google Patents

半导体芯片及其制造方法 Download PDF

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CN100536120C
CN100536120C CNB2007101373095A CN200710137309A CN100536120C CN 100536120 C CN100536120 C CN 100536120C CN B2007101373095 A CNB2007101373095 A CN B2007101373095A CN 200710137309 A CN200710137309 A CN 200710137309A CN 100536120 C CN100536120 C CN 100536120C
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wiring layer
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金唇翰
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DB HiTek Co Ltd
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Dongbu Electronics Co Ltd
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Abstract

本发明公开一种半导体芯片及其制造方法，其可包括导电焊盘，用以将半导体器件连接到外部电路。至少一个半导体器件可以形成在半导体衬底上。至少一层金属布线层可以形成在至少一个半导体器件上方。多层金属布线层可以为半导体芯片上的半导体器件提供电连接。至少一层金属布线层可以具有在其中心开口的一部分。至少一层层间介电层可以形成在半导体器件与导电焊盘之间。至少其中一层层间介电层填充金属布线层的开口部。由此，相对于较大负载可以将结构的整体性最大化，从而防止层间介电层破裂和器件失效。

Description

半导体芯片及其制造方法
技术领域
本发明涉及一种半导体芯片及其制造方法。
背景技术
半导体芯片中可以形成有多个半导体器件。多个半导体器件可以通过芯片上表面上形成的导电焊盘(芯片焊盘)电连接至外部电路。图1示出包括导电焊盘200的半导体芯片100，该导电焊盘200通过接合线300连接至外部电路(例如引线框)。
半导体衬底上可以形成多个半导体电路器件(例如MOS晶体管)，并且可以形成多个金属布线层以提供对于这些电路器件的电连接。可以形成多个层间介电层，以将单元电路器件与金属布线层相互隔离。各单元电路器件与金属布线层可以通过穿通层间介电层的多个接触塞而相互电连接。
半导体芯片上表面上的芯片焊盘可以电连接至外部电路。芯片焊盘也可以通过穿通层间介电层的接触塞而电连接至金属布线层(例如最上层布线层)。因此，形成在半导体衬底上的多个半导体器件可以通过接触塞、至少一层金属布线层和芯片焊盘而连接至外部电路。
图2a和2b示出芯片焊盘以及芯片焊盘下方的多个金属布线层和多个层间介电层。图2a示出多个接触塞C3，所述接触塞C3电连接至其下方的金属布线层。图2b示出半导体芯片的横截面，该半导体芯片包括形成在半导体衬底上的半导体器件。如图2a所示，多个接触塞C3可以以菱形和/或方形的形式直接排列在芯片焊盘200下方。
如图2b所示，接触塞C3可以连接至金属布线层M2。金属布线层M2可以通过接触塞C2连接至第一金属布线层M1。芯片焊盘200、金属布线层M1和金属布线层M2可以通过层间介电层D1和层间介电层D2而相互隔离。
第一金属布线层M1可以通过多晶硅一金属电介质(PMD)与半导体器件隔离。第一金属布线层M1可以通过接触塞C1连接至晶体管的栅极202或源/漏扩散区204。
通过将半导体芯片经芯片焊盘200电连接至外部器件，可以测试半导体芯片的可靠性和性能。外部器件可以在形成容纳最终半导体产品的封装之前，通过引线接合连接至芯片焊盘200。在测试期间，可以通过探针将较大负载加在芯片焊盘上。氧化物膜可以用作半导体器件与金属布线层之间的绝缘层。但是，从材料角度来看氧化物可能比较脆弱，因而可能破裂。
测试期间芯片焊盘上的过度负载引起的破裂可能引起层间介电层破裂，由此可能导致器件失效。破裂可能形成于芯片焊盘下方的上层层间介电层。但是，破裂可能延伸至上层层间介电层下方的层间介电层。
发明内容
本发明实施例可以提高层间介电层的结构强度，由此对于加在半导体芯片的芯片焊盘上的较大外部负载可以具有适应性。
本发明提供一种半导体芯片，包括：半导体衬底；至少一层层间介电层，形成在该半导体衬底上方；导电焊盘，形成在所述至少一层层间介电层上方，其中该导电焊盘具有周边部和中心部，并且所述至少一层层间介电层在该中心部下方比在该周边部下方厚；至少一层第一布线层和至少一层第二布线层，位于该导电焊盘与该半导体衬底之间；至少一个第一接触塞，将所述第一布线层与该导电焊盘电连接；以及至少一个第二接触塞，将所述第一布线层与所述第二布线层电连接；其中所述至少一个第一接触塞的轴线与所述至少一个第二接触塞的轴线不共线。
根据本发明，所述至少一层第一布线层仅形成在该周边部下方。
根据本发明，在至少一层第一布线层与所述导电焊盘之间形成有所述至少一层层间介电层。
根据本发明，在所述至少一层第一布线层与该半导体衬底之间形成有所述至少一层层间介电层。
根据本发明，所述至少一个第一接触塞和所述至少一个第二接触塞形成在所述至少一层层间介电层中。
根据本发明，所述至少一层第二布线层形成在该中心部和该周边部下方。
根据本发明，该中心部的表面积介于该导电焊盘表面积的约25％与约50％之间。
根据本发明，该半导体芯片包括在CMOS图像传感器中。
本发明还提供一种半导体芯片的制造方法，包括：在半导体衬底上方形成至少一层层间介电层；在所述至少一层层间介电层上方形成导电焊盘，其中该导电焊盘具有周边部和中心部，并且所述至少一层层间介电层在该中心部下方比在该周边部下方厚；在该导电焊盘与该半导体衬底之间形成至少一层第一布线层和至少一层第二布线层；形成至少一个第一接触塞，将该第一布线层与该导电焊盘电连接；以及形成至少一个第二接触塞，将该第一布线层与该第二布线层电连接；其中所述至少一个第一接触塞的轴线与所述至少一个第二接触塞的轴线不共线。
根据本发明，所述至少一层第一布线层仅形成在该周边部下方。
根据本发明，在所述至少一层第一布线层与所述导电焊盘之间形成所述至少一层层间介电层。
根据本发明，在所述至少一层第一布线层与该半导体衬底之间形成所述至少一层层间介电层。
根据本发明，在所述至少一层层间介电层中形成所述至少一个第一接触塞和所述至少一个第二接触塞。
根据本发明，在该中心部和该周边部下方形成所述至少一层第二布线层。
根据本发明，该中心部的表面积介于该导电焊盘表面积的约25％与约50％之间。
根据本发明，该导电焊盘包括在CMOS图像传感器中。
在实施例中，半导体芯片可以包括下列的至少其中之一：形成在半导体衬底上的半导体器件；电连接至外部电路的至少一层金属布线层，其中该至少一层金属布线层在中心开口；形成在半导体器件上方的至少一层层间介电层，其中该至少一层层间介电层填充至少一层金属布线层的开口部；形成在至少一层层间介电层上方的导电焊盘，其可以电连接至外部电路。
在实施例中，在导电焊盘与至少一层金属布线层之间和/或在两层或更多层金属布线层之间可以形成导电通路。根据实施例，导电通路在不同的通路层之间可以交错布置。
根据本发明的实施例，形成在焊盘中心部下方的层间介电层较厚，由此相对于较大负载可以将结构的整体性最大化，从而防止层间介电层破裂和器件失效。
附图说明
图1示出半导体芯片上方形成的芯片焊盘中引线接合的透视图。
图2a示出芯片焊盘结构的俯视图。
图2b示出芯片焊盘结构的横截面图。
图3a示出根据实施例的芯片焊盘的俯视图，沿该芯片焊盘的周边形成有接触塞。
图3b示出根据实施例的导电焊盘、导电通路和金属布线层的横截面图。
图3c示出根据实施例的芯片焊盘的下部结构的横截面图。
具体实施方式
在实施例中，半导体芯片可以包括导电焊盘，以将半导体器件连接到外部电路。在半导体衬底上方可以形成至少一个半导体器件。在至少一个半导体器件上可以形成至少一层金属布线层。多个金属布线层可以为半导体芯片上方的半导体器件提供电连接。至少一层金属布线层可以具有在其中心开口的一部分。在半导体器件与导电焊盘之间可以形成至少一层层间介电层。至少其中一层层间介电层填充金属布线层的开口部。
在实施例中，如果半导体器件是CMOS图像器件的一部分，则半导体器件可以包括光电二极管和/或MOS晶体管。在至少一个半导体器件上方可以形成多晶硅一金属电介质(PMD)层间介电层。可以依次堆叠至少一层金属布线层和至少一层层间介电层。
如图3a所示，根据实施例，导电芯片焊盘200可以具有中心部220和周边部240。如图3b所示，在芯片焊盘200下方可以有金属布线层M2。根据实施例，金属布线层M2可以形成在芯片焊盘200的周边部240下方，但在芯片焊盘200的中心部220下方开口。在实施例中，芯片焊盘200与金属布线层M2之间有至少一层层间介电层D12。在实施例中，至少一层介电层D12填充金属布线层M2的开口区域。在金属布线层M1下方可以有半导体衬底SUB。
根据实施例，金属布线层M1可以形成在金属布线层M2下方。在实施例中，金属布线层M1可以不具有开口区域。根据实施例，在金属布线层M1与金属布线层M2之间可以形成至少一层介电层D12。接触塞C3可以将金属布线层M2与芯片焊盘200电连接。接触塞C2可以将金属布线层M1与金属布线层M2电连接。在实施例中，接触塞C2和接触塞C3可以交错布置。换句话说，在实施例中，接触塞C3的中心线L3与接触塞C2的中心线L2可以不共线。接触塞C2和接触塞C3可以形成为穿过至少一层层间介电层D12(例如穿过通路孔)。
在实施例中，芯片焊盘200与金属布线层M1之间的至少一层层间介电层D12的较厚部可将结构的整体性最大化，并且可使芯片焊盘能够承受测试期间加在芯片焊盘200上的较大负载。换句话说，在实施例中，通过使金属布线层M2在中心开口，至少一层层间介电层D12在芯片焊盘200的中心部220下方可以较厚。在实施例中，接触塞C2和接触塞C3的交错布置可将结构的整体性最大化，并且可使芯片焊盘能够承受测试期间加在芯片焊盘200上的较大负载。虽然图3b仅示出一层金属布线层在中心开口(例如金属布线层M2)，但是根据实施例，多层金属布线层可以在彼此上面形成且具有开口，以增加至少一层层间介电层的厚度。如图3c所示，根据实施例，下层金属布线层(即第二金属布线层M2)也可在中心开口。虽然图3b示出接触塞C2和接触塞C3交错布置，但是根据实施例，接触塞C2和接触塞C3可以排列成行。
在实施例中，接触塞(例如接触塞C2和接触塞C3)可以仅形成在芯片焊盘200的周边部240下方。接触塞C3可以分为两个区域(即，在中心部220下方分离开)，在这两个区域之间具有至少一层层间介电层D12。同样，接触塞C2可以分为两个区域(即，在中心部220下方分离开)，在这两个区域之间具有至少一层层间介电层D12。金属布线层M2可以分为两个区域(即，在中心部220下方分离开)，在这两个区域之间具有至少一层层间介电层D12。
在引线接合和/或测试操作期间，负载可以主要集中在焊盘中心部220上。如图3b所示，根据实施例，形成在焊盘中心部220下方的层间介电层D12较厚(由于金属布线层M2内的中心开口)，由此相对于较大负载可以将结构的整体性最大化。在实施例中，由于至少一层层间介电层D12可以较厚，所以能够防止至少一层层间介电层D12破裂，从而防止器件失效。
如图3c所示，全部多层金属布线层(例如金属布线层M1和M2)形成在焊盘周边部240下方，而在焊盘中心部220下方开口。因此，根据实施例，至少一层层间介电层D4可以形成为较厚，由此相对于较大外部负载可以增强结构的整体性。
在实施例中，图3b所示的至少一层层间介电层D12的结构以及图3c所示的至少一层层间介电层D4的结构允许对于加在导电焊盘200上的外部负载进行缓冲。在实施例中，焊盘中心部220的表面积可以介于导电焊盘200表面积的约25％与约50％之间。在实施例中，焊盘中心部220的一侧长度可以介于导电焊盘200的一侧长度的约50％与约70％之间。本领域普通技术人员了解，可以利用焊盘中心部220相对于导电焊盘200的其它相关比例。如果焊盘中心部220的面积太小，缓冲效果可能不是最佳的。如果焊盘中心部220的面积太大，在上层层间介电层的化学机械抛光工艺中可能出现凹陷现象(dishing phenomenon)。
在实施例中，由于负载基本上集中于导电焊盘200的焊盘中心部220，所以能够使至少一层层间介电层(例如D12和/或D4)破裂的可能性最小化。在实施例中，为了增强焊盘周边部240的结构强度，接触塞(例如C2和C3)的中心线(例如L2和L3)可以不共线，而可以是交错布置的。例如，根据实施例，图3b示出接触塞C3的中心线L3和接触塞C2的中心线沿着不同线布置。在实施例中，层间介电层中由于形成接触塞而产生的损耗区域可以相互交叉，而不相互交叠。
虽然已将实施例描述如上，但是应当理解，本领域技术人员可以设计出多种其它修改和实施例，它们会落入本说明书公开的原理的精神和范围内。在说明书、附图及随附权利要求书的范围内，可以进行各种变化和修改。

Claims (16)

1、一种半导体芯片，包括：
半导体衬底；
至少一层层间介电层，形成在该半导体衬底上方；
导电焊盘，形成在所述至少一层层间介电层上方，其中该导电焊盘具有周边部和中心部，并且所述至少一层层间介电层在该中心部下方比在该周边部下方厚；
至少一层第一布线层和至少一层第二布线层，位于该导电焊盘与该半导体衬底之间；
至少一个第一接触塞，将所述第一布线层与该导电焊盘电连接；以及
至少一个第二接触塞，将所述第一布线层与所述第二布线层电连接；
其中所述至少一个第一接触塞的轴线与所述至少一个第二接触塞的轴线不共线。
2、如权利要求1所述的半导体芯片，其中所述至少一层第一布线层仅形成在该周边部下方。
3、如权利要求2所述的半导体芯片，其中在所述至少一层第一布线层与所述导电焊盘之间形成有所述至少一层层间介电层。
4、如权利要求3所述的半导体芯片，其中在所述至少一层第一布线层与该半导体衬底之间形成有所述至少一层层间介电层。
5、如权利要求1所述的半导体芯片，其中所述至少一个第一接触塞和所述至少一个第二接触塞形成在所述至少一层层间介电层中。
6、如权利要求2所述的半导体芯片，其中所述至少一层第二布线层形成在该中心部和该周边部下方。
7、如权利要求1所述的半导体芯片，其中该中心部的表面积介于该导电焊盘表面积的25％与50％之间。
8、如权利要求1所述的半导体芯片，其中该半导体芯片包括在CMOS图像传感器中。
9、一种半导体芯片的制造方法，包括：
在半导体衬底上方形成至少一层层间介电层；
在所述至少一层层间介电层上方形成导电焊盘，其中该导电焊盘具有周边部和中心部，并且所述至少一层层间介电层在该中心部下方比在该周边部下方厚；
在该导电焊盘与该半导体衬底之间形成至少一层第一布线层和至少一层第二布线层；
形成至少一个第一接触塞，将该第一布线层与该导电焊盘电连接；以及
形成至少一个第二接触塞，将该第一布线层与该第二布线层电连接；
其中所述至少一个第一接触塞的轴线与所述至少一个第二接触塞的轴线不共线。
10、如权利要求9所述的方法，其中所述至少一层第一布线层仅形成在该周边部下方。
11、如权利要求10所述的方法，其中在所述至少一层第一布线层与所述导电焊盘之间形成所述至少一层层间介电层。
12、如权利要求11所述的方法，其中在所述至少一层第一布线层与该半导体衬底之间形成所述至少一层层间介电层。
13、如权利要求9所述的方法，其中在所述至少一层层间介电层中形成所述至少一个第一接触塞和所述至少一个第二接触塞。
14、如权利要求10所述的方法，其中在该中心部和该周边部下方形成所述至少一层第二布线层。
15、如权利要求9所述的方法，其中该中心部的表面积介于该导电焊盘表面积的25％与50％之间。
16、如权利要求9所述的方法，其中该导电焊盘包括在CMOS图像传感器中。
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