CN103918074B - 微型表面安装装置封装 - Google Patents

微型表面安装装置封装 Download PDF

Info

Publication number
CN103918074B
CN103918074B CN201280054601.XA CN201280054601A CN103918074B CN 103918074 B CN103918074 B CN 103918074B CN 201280054601 A CN201280054601 A CN 201280054601A CN 103918074 B CN103918074 B CN 103918074B
Authority
CN
China
Prior art keywords
carrier
encapsulant
die
grinding
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201280054601.XA
Other languages
English (en)
Chinese (zh)
Other versions
CN103918074A (zh
Inventor
阿宁迪亚·波达尔
冯涛
威尔·K·王
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN103918074A publication Critical patent/CN103918074A/zh
Application granted granted Critical
Publication of CN103918074B publication Critical patent/CN103918074B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/695—Organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/241—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
    • H10W44/248—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)
CN201280054601.XA 2011-11-22 2012-11-21 微型表面安装装置封装 Active CN103918074B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/303,053 US8450151B1 (en) 2011-11-22 2011-11-22 Micro surface mount device packaging
US13/303,053 2011-11-22
PCT/US2012/066272 WO2013078323A1 (en) 2011-11-22 2012-11-21 Micro surface mount device packaging

Publications (2)

Publication Number Publication Date
CN103918074A CN103918074A (zh) 2014-07-09
CN103918074B true CN103918074B (zh) 2017-06-09

Family

ID=48426012

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280054601.XA Active CN103918074B (zh) 2011-11-22 2012-11-21 微型表面安装装置封装

Country Status (4)

Country Link
US (1) US8450151B1 (enExample)
JP (1) JP6576038B2 (enExample)
CN (1) CN103918074B (enExample)
WO (1) WO2013078323A1 (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
KR101970291B1 (ko) * 2012-08-03 2019-04-18 삼성전자주식회사 반도체 패키지의 제조 방법
US9269675B2 (en) * 2013-10-18 2016-02-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9390993B2 (en) * 2014-08-15 2016-07-12 Broadcom Corporation Semiconductor border protection sealant
US10079156B2 (en) 2014-11-07 2018-09-18 Advanced Semiconductor Engineering, Inc. Semiconductor package including dielectric layers defining via holes extending to component pads
US9721799B2 (en) * 2014-11-07 2017-08-01 Advanced Semiconductor Engineering, Inc. Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof
CN106601628A (zh) * 2016-12-30 2017-04-26 通富微电子股份有限公司 一种芯片的封装方法及芯片封装结构
WO2018135706A1 (ko) * 2017-01-17 2018-07-26 주식회사 네패스 반도체 패키지의 제조 방법
WO2018135708A1 (ko) * 2017-01-17 2018-07-26 주식회사 네패스 반도체 패키지의 제조 방법
WO2018135707A1 (ko) * 2017-01-17 2018-07-26 주식회사 네패스 반도체 패키지 제조용 트레이
KR101901988B1 (ko) * 2017-01-17 2018-09-27 주식회사 네패스 반도체 패키지의 제조 방법
WO2018135705A1 (ko) * 2017-01-17 2018-07-26 주식회사 네패스 반도체 패키지의 제조 방법
EP3389085B1 (en) * 2017-04-12 2019-11-06 Nxp B.V. Method of making a plurality of packaged semiconductor devices
US11488931B2 (en) 2018-02-23 2022-11-01 Chengdu Eswin Sip Technology Co., Ltd. Encapsulated fan-in semiconductor package with heat spreader and method of manufacturing the same
WO2020170002A1 (en) * 2019-02-23 2020-08-27 Chengdu Eswin Sip Technology Co., Ltd. Encapsulated fan-in semiconductor package with heat spreader and method of manufacturing the same
US12230539B2 (en) 2018-08-01 2025-02-18 Texas Instruments Incorporated Wafer chip scale packaging with ball attach before repassivation
US10541220B1 (en) 2018-08-02 2020-01-21 Texas Instruments Incorporated Printed repassivation for wafer chip scale packaging
US11183460B2 (en) 2018-09-17 2021-11-23 Texas Instruments Incorporated Embedded die packaging with integrated ceramic substrate
US10650957B1 (en) 2018-10-31 2020-05-12 Texas Instruments Incorporated Additive deposition low temperature curable magnetic interconnecting layer for power components integration
US11031332B2 (en) 2019-01-31 2021-06-08 Texas Instruments Incorporated Package panel processing with integrated ceramic isolation
US10879155B2 (en) 2019-05-09 2020-12-29 Texas Instruments Incorporated Electronic device with double-sided cooling
CN114514605A (zh) * 2019-11-22 2022-05-17 华为技术有限公司 芯片封装、电子设备及芯片封装制备方法
KR102635853B1 (ko) * 2020-04-29 2024-02-13 주식회사 네패스라웨 반도체 패키지 및 이의 제조방법
KR102684002B1 (ko) * 2020-12-14 2024-07-11 주식회사 네패스 반도체 패키지 제조방법 및 이에 이용되는 가이드 프레임
CN113064333A (zh) * 2021-03-19 2021-07-02 北京智创芯源科技有限公司 一种微小晶片的光刻方法、晶片载片及光刻工装

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020004288A1 (en) * 2000-04-28 2002-01-10 Kazuo Nishiyama Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof
US20050181540A1 (en) * 2002-03-06 2005-08-18 Farnworth Warren M. Semiconductor component and system having thinned, encapsulated dice
US20060273451A1 (en) * 2005-06-01 2006-12-07 Tdk Corporation Semiconductor IC and its manufacturing method, and module with embedded semiconductor IC and its manufacturing method
CN101924039A (zh) * 2009-06-15 2010-12-22 日月光半导体制造股份有限公司 半导体封装件及其制造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2738568B2 (ja) * 1989-09-06 1998-04-08 新光電気工業株式会社 半導体チップモジュール
US5384691A (en) 1993-01-08 1995-01-24 General Electric Company High density interconnect multi-chip modules including embedded distributed power supply elements
US6054772A (en) 1998-04-29 2000-04-25 National Semiconductor Corporation Chip sized package
JP4526651B2 (ja) * 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
US6825108B2 (en) * 2002-02-01 2004-11-30 Broadcom Corporation Ball grid array package fabrication with IC die support structures
JP2003298005A (ja) * 2002-02-04 2003-10-17 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2003297977A (ja) * 2002-03-28 2003-10-17 Sanyu Rec Co Ltd 電子部品の製造方法
US6803303B1 (en) * 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
US6936929B1 (en) 2003-03-17 2005-08-30 National Semiconductor Corporation Multichip packages with exposed dice
US8030138B1 (en) 2006-07-10 2011-10-04 National Semiconductor Corporation Methods and systems of packaging integrated circuits
JP2008300560A (ja) * 2007-05-30 2008-12-11 Sony Corp 半導体装置及びその製造方法
US8018050B2 (en) 2007-11-01 2011-09-13 National Semiconductor Corporation Integrated circuit package with integrated heat sink
US7749809B2 (en) 2007-12-17 2010-07-06 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US20090212428A1 (en) * 2008-02-22 2009-08-27 Advanced Chip Engineering Technology Inc. Re-distribution conductive line structure and the method of forming the same
JP5075890B2 (ja) 2008-09-03 2012-11-21 株式会社東芝 半導体装置及び半導体装置の製造方法
JP2010219489A (ja) * 2009-02-20 2010-09-30 Toshiba Corp 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020004288A1 (en) * 2000-04-28 2002-01-10 Kazuo Nishiyama Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof
US20050181540A1 (en) * 2002-03-06 2005-08-18 Farnworth Warren M. Semiconductor component and system having thinned, encapsulated dice
US20060273451A1 (en) * 2005-06-01 2006-12-07 Tdk Corporation Semiconductor IC and its manufacturing method, and module with embedded semiconductor IC and its manufacturing method
CN101924039A (zh) * 2009-06-15 2010-12-22 日月光半导体制造股份有限公司 半导体封装件及其制造方法

Also Published As

Publication number Publication date
US20130127043A1 (en) 2013-05-23
CN103918074A (zh) 2014-07-09
US8450151B1 (en) 2013-05-28
JP6576038B2 (ja) 2019-09-18
WO2013078323A1 (en) 2013-05-30
JP2015504608A (ja) 2015-02-12

Similar Documents

Publication Publication Date Title
CN103918074B (zh) 微型表面安装装置封装
TWI832448B (zh) 半導體裝置及其製造方法
US20130127044A1 (en) Micro surface mount device packaging
TWI751530B (zh) 半導體裝置之製造方法
US8916421B2 (en) Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits
TWI585939B (zh) 晶圓級堆疊晶片封裝及製造其之方法
CN107808856B (zh) 半导体封装结构及其制造方法
CN102244012B (zh) 半导体器件及其制造方法
US8552540B2 (en) Wafer level package with thermal pad for higher power dissipation
CN111403368B (zh) 半导体封装体
CN107134438A (zh) 半导体器件和在半导体管芯周围形成绝缘层的方法
US20100148357A1 (en) Method of packaging integrated circuit dies with thermal dissipation capability
US20130154091A1 (en) Semiconductor device packaging using encapsulated conductive balls for package-on-package back side coupling
TW202249195A (zh) 半導體封裝以及製造其之方法
US20100261313A1 (en) Semiconductor package and method of packaging semiconductor devices
CN105655305A (zh) 半导体封装及其制备方法
WO2010058646A1 (ja) 半導体パッケージおよびその製造方法
CN102543772A (zh) 结合晶片级不同尺寸半导体管芯的方法和半导体器件
JP2008277570A (ja) 半導体装置及びその製造方法
KR101045557B1 (ko) 반도체 패키지 및 그 제조 방법
CN107611100A (zh) 整合扇出型封装及其制造方法
CN209691749U (zh) 多芯片模块封装件
CN213782012U (zh) 半导体封装结构
US8586450B2 (en) Process for fabricating semiconductor devices and a semiconductor device comprising a chip with through-vias
TWI879337B (zh) 封裝劑定義的平面網格陣列（ｌｇａ）封裝及其製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant