CN103855221B - 半导体器件和制造半导体器件的方法 - Google Patents

半导体器件和制造半导体器件的方法 Download PDF

Info

Publication number
CN103855221B
CN103855221B CN201310634761.8A CN201310634761A CN103855221B CN 103855221 B CN103855221 B CN 103855221B CN 201310634761 A CN201310634761 A CN 201310634761A CN 103855221 B CN103855221 B CN 103855221B
Authority
CN
China
Prior art keywords
region
ridge
semiconductor devices
adjacent
field plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310634761.8A
Other languages
English (en)
Other versions
CN103855221A (zh
Inventor
A.迈泽
T.施勒泽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN103855221A publication Critical patent/CN103855221A/zh
Application granted granted Critical
Publication of CN103855221B publication Critical patent/CN103855221B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66696—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及半导体器件和制造半导体器件的方法。一种半导体器件包括在具有第一主表面的半导体衬底中形成的晶体管。该晶体管包括源极区域、漏极区域、沟道区域、漂移区和邻近于沟道区域的栅电极。栅电极被配置为控制在沟道区域中形成的沟道的传导性，沟道区域和漂移区在源极区域和漏极区域之间被沿着第一方向置放，第一方向平行于第一主表面。沟道区域具有沿着第一方向延伸的第一突脊的形状，并且晶体管包括邻近于漂移区布置的第一场板。

Description

半导体器件和制造半导体器件的方法
技术领域
本说明书涉及一种半导体器件和一种制造半导体器件的方法。
背景技术
通常在汽车和工业电子设备中采用的MOS功率晶体管或者MOS功率器件当被接通时应该具有低的接通电阻（Ron）。在断开状态中，它们应该具有高的击穿电压特性并且承受源极-漏极电压。例如，当被切断时，MOS功率晶体管应该承受几十到几百伏特的漏极到源极电压Vds。作为进一步的实例，MOS功率晶体管以低电压降Vds在大约2到20V的栅极-源极电压下传导可以高达几百安培的非常大的电流。
根据通常采用的技术，使用包括漏极延展区域或者基于所谓的降低表面电场（resurf）概念的横向MOS晶体管。根据该降低表面电场概念，在断开状态中，电荷被置放在漂移区域之下的掺杂部分移除。可替代地，可以作为置放在漂移区域之上并且被从漂移区域绝缘的电极实现这个掺杂部分。为了进一步降低Rdson和寄生电容，正在找寻用于实现晶体管的、新的概念。
发明内容
根据一个实施例，一种在半导体衬底中形成的半导体器件包括第一主表面和晶体管。该晶体管包括源极区域、漏极区域、沟道区域、漂移区和邻近于沟道区域的栅电极，栅电极被配置为控制在沟道区域中形成的沟道的传导性。沟道区域和漂移区在源极区域和漏极区域之间被沿着第一方向置放，该第一方向平行于第一主表面。沟道区域具有沿着第一方向延伸的第一突脊的形状。该晶体管进一步包括邻近于漂移区布置的第一场板。
根据进一步的实施例，一种在半导体衬底中形成的半导体器件包括第一主表面和晶体管。该晶体管包括源极区域、漏极区域、沟道区域、漂移区和邻近于沟道区域的栅电极，栅电极被配置为控制在沟道区域中形成的沟道的传导性。沟道区域和漂移区在源极区域和漏极区域之间被沿着第一方向置放，该第一方向平行于第一主表面。沟道区域具有沿着第一方向延伸的第一突脊的形状，该第一突脊具有第一宽度d1，使得：d1≤2xld，其中ld表示在第一突脊和栅电介质之间的界面处形成的耗尽区的长度，栅电介质被置放在第一突脊和栅电极之间。
根据进一步的实施例，描述了一种在半导体衬底中制造半导体器件的方法，该半导体衬底包括第一主表面和晶体管。根据该方法，形成该晶体管包括形成源极区域、漏极区域、沟道区域、漂移区和邻近于沟道区域的栅电极，其中沟道区域和漂移区被形成为在源极区域和漏极区域之间沿着第一方向置放，该第一方向平行于第一主表面。形成沟道区域包括在半导体衬底中形成第一突脊，第一突脊沿着第一方向延伸，第一突脊具有第一宽度d1，使得：d1≤2xld，其中ld表示在第一突脊和栅电介质之间的界面处形成的耗尽区的长度，栅电介质被置放在第一突脊和栅电极之间。
附图说明
附图被包括用于提供对于本发明的实施例的进一步的理解并且在本说明书中结合并且构成它的一个部分。附图示意本发明的实施例并且与说明书一起地用于解释原理。将易于理解本发明的其它实施例和预期优点中的很多优点，因为通过参考以下详细说明，它们得到更好的理解。附图的元件并不是必要地相对于彼此成比例。类似的附图标记标注相应的类似的部分。
图1A示出根据一个实施例的半导体器件的一个实例的平面视图；
图1B示出图1A所示半导体器件的截面视图；
图1C示出沿着与沿其截取图1B的截面视图的方向垂直的方向截取的、根据一个实施例的半导体器件的截面视图；
图1D示出沿着与沿其截取图1B的截面视图的方向垂直的方向截取的、该半导体器件的进一步的截面视图；
图2示出根据进一步实施例的半导体器件的平面视图；
图3A到3D示出在执行一种制造方法的加工方法时半导体衬底的截面视图；并且
图4A和4B概略地示出示意根据实施例的、用于制造半导体器件的步骤的流程图。
具体实施方式
在以下详细说明中，对于附图进行参考，附图形成它的一个部分，并且在其中通过示意的方式示意可以在其中实践本发明的具体实施例。在这方面，方向术语诸如“顶”、“底”、“前”、“后”、“首”、“尾”等是参考所描述的图的定向使用的。因为本发明的实施例的部件能够被以多种不同的定向定位，所以方向术语是为了示意的意图使用的而绝非加以限制。应该理解在不偏离由权利要求限定的范围的情况下，可以利用其它的实施例并且可以作出结构或者逻辑变化。
实施例的说明不是限制性的。特别地，在下文中描述的实施例的元件可以被与不同的实施例的元件组合。
在以下说明中使用的术语“晶圆”、“衬底”或者“半导体衬底”可以包括具有半导体表面的任何半导体基结构。晶圆和结构应该理解为包括硅、绝缘体上硅（SOI）、蓝宝石上硅（SOS）、掺杂和非掺杂半导体、被基部半导体基础支撑的硅的外延层、和其它半导体结构。半导体不需要是硅基的。半导体同样能够是硅-锗、锗或者砷化镓。根据本申请的实施例，通常，碳化硅（SiC）或者氮化镓（GaN）是半导体衬底材料的进一步的实例。
如在本说明书中使用的术语“横向”和“水平”旨在描述平行于半导体衬底或者半导体本体的第一表面的定向。这能够例如是晶圆或者管芯的表面。
如在本说明书中使用的术语“竖直”旨在描述垂直于半导体衬底或者半导体本体的第一表面布置的定向。
附图和说明书通过接着掺杂类型“n”或者“p”地示意“-”或者“+”而示意相对掺杂浓度。例如，“n-”意味着低于“n”掺杂区域的掺杂浓度的掺杂浓度，而“n+”掺杂区域具有比“n”掺杂区域更高的掺杂浓度。相同的相对掺杂浓度的掺杂区域并不是必要地具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区域可以具有相同或者不同的绝对掺杂浓度。在附图和说明书中，为了更好地理解起见，经常掺杂部分被指定为是“p”或者“n”掺杂的。如应该清楚地理解地，这个指定绝非旨在是限制性的。掺杂类型能够是任意的，只要所描述的功能性得以实现。此外，在所有的实施例中，掺杂类型都能够被颠倒过来。
如在本说明书中采用地，术语“耦接”和/或“电耦接”并非意在意味着元件必须被直接地耦接到一起——可以在被“耦接”或者“电耦接”的元件之间提供居间的元件。术语“电连接”旨在描述在被电连接到一起的元件之间的低欧姆电连接。
通常，为了图案化材料层，可以使用其中提供适当的光致抗蚀剂材料的光刻方法。使用适当的光掩模，光致抗蚀剂材料被光刻图案化。图案化的光致抗蚀剂层能够在随后的加工步骤期间被用作掩模。例如，如通常地那样，硬掩模层或者由适当的材料诸如氮化硅、多晶硅或者碳制成的层可以被提供在所要图案化的材料层之上。例如使用蚀刻过程，硬掩模层被光刻图案化。采取图案化的硬掩模层作为蚀刻掩模，材料层被图案化。
如在这里所使用地，术语“具有”、“含有”、“包含”、“包括”等是开放式术语，其指示所陈述的元件或者特征的存在但是并不排除另外的元件或者特征。冠词（“a”、“an”和“the”）旨在包括复数以及单数，除非上下文清楚地另有指示。
图1A示出根据一个实施例的半导体器件的平面视图，并且图1B示出在I和I'之间截取的半导体器件的截面视图。
图1所示半导体器件包括源极区域201、漏极区域205、沟道区域220和漂移区260。源极区域201、漏极区域205和漂移区260可以掺杂有第一导电类型的掺杂剂，例如n型掺杂剂。源极和漏极区域201、205的掺杂浓度可以高于漂移区260的掺杂浓度。沟道区域220被布置在源极区域201和漂移区260之间。沟道区域220掺杂有第二导电类型的掺杂剂，例如，被p掺杂。漂移区260可以被布置在沟道区域220和漏极区域205之间。源极区域201、沟道区域220、漂移区260和漏极区域205被沿着第一方向置放。
当适当的电压被施加到栅电极210时，在沟道区域220中形成的沟道的传导性将受到栅电压控制。栅电极210利用绝缘栅介电材料211诸如氧化硅被从沟道区域220绝缘。通过控制在沟道区域220中形成的沟道的传导性，从源极区域201经由在沟道区域220中形成的沟道和漂移区260到漏极区域205的电流可以受到控制。
源极区域201被连接到源电极202。漏极区域205被连接到漏电极206。
图1A所示布置实现包括在具有第一主表面110的半导体衬底100中形成的晶体管200的半导体器件1。根据一个实施例，晶体管200可以进一步包括邻近于漂移区260布置的场板250。场板250利用绝缘场介电层251诸如场氧化物被从漂移区260绝缘。当被接通时，在沟道区域220和绝缘栅介电材料211之间的边界处形成反型层。相应地，晶体管200处于经由漂移区260从源极区域201到漏极区域205的传导状态中。当晶体管200被切断时，在沟道区域220和绝缘栅介电材料211之间的边界处不形成任何传导沟道，从而无任何电流流动。此外，在断开状态中，适当的电压可以被施加到场板250。在断开状态中，场板250从漂移区260耗尽电荷载流子从而半导体器件的反向电压特性得以改进。在包括场板的半导体器件中，与不带场板的器件相比，漂移区260的掺杂浓度可以增加而不恶化反向电压特性。由于漂移区260的更高的掺杂浓度，接通电阻Rdson进一步降低，从而导致器件特性得以改进。
图1B示出在I和I'之间的、在图1A中示意的半导体器件1的截面视图。在I和I’之间的方向对应于第一方向。如所示出地，源极区域201从主表面110到衬底100的深度方向中即关于主表面110垂直地延伸。沟道区域220和漂移区260在源极区域201和漏极区域205之间被沿着平行于第一主表面110的第一方向置放。漏极区域205同样地沿着衬底的深度方向从第一主表面110延伸。如由点线示意地，在附图的描绘平面之前和之后的平面中，栅极沟槽212被邻近于沟道区域220置放。以相应的方式，场板沟槽252可以被邻近于漂移区260置放。栅极沟槽212和场板沟槽252沿着衬底的深度方向从第一主表面110延伸。结果，沟道区域220具有第一突脊的形状。由于存在场板沟槽252，漂移区260还具有第二突脊的形状。图1B进一步示出在本体区域220之下和在漂移区260的一个部分之下置放的本体连接注入区域225。本体连接注入区域225将沟道区域220连接到源极触点202从而避免否则能够在这个部分处形成的寄生双极晶体管。而且，本体连接注入区域225在漂移区260之下延伸，从而在晶体管200的断开状态中，漂移区260可以被更加容易地耗尽。
图1C和1D示意在图1A中的II和II'与III和III'之间截取的衬底的截面视图。在II和II'之间和在III和III'之间的方向垂直于第一方向。如在图1C中所示，沟道区域220具有突脊的形状，该突脊具有宽度d1和深度或者高度t1。例如，第一突脊可以具有顶侧220a和两个侧壁220b。侧壁220b可以关于第一主表面110垂直地或者以大于75°的角度延伸。可以邻近于突脊的至少两侧置放栅电极210。
而且，在III和III'之间的截面视图中，漂移区260还具有第二突脊的形状，第二突脊具有宽度d2和深度或者高度t2。例如，第二突脊可以具有顶侧260a和两个侧壁260b。侧壁260b可以关于第一主表面110垂直地或者以大于75°的角度延伸。可以邻近于顶侧260a或者邻近于突脊的至少两侧置放漂移区260。
在每一个突脊之下，置放深本体连接注入区域225，这将在下文中解释。栅介电层211被置放在栅电极210和沟道区域220之间。以类似的方式，场介电层251被置放在场板250和漂移区260之间。
根据一个实施例，沟道区域220的宽度d1是：d1≤2xld，其中dl表示在栅介电层211和沟道区域220之间的界面处形成的耗尽区的长度。例如，耗尽区的宽度可以被确定为：
其中εS表示半导体材料的介电常数（对于硅11.9*ε0），k表示玻耳兹曼常数（1.38066*10-23J/K），T表示温度，ln表示自然对数，NA表示半导体本体的杂质浓度，ni表示本征载流子浓度（在27°C下对于硅1.45*1010），q表示基本电荷（1.6*10-19C）。
通常，假设在晶体管中，在对应于阈值电压的栅电压下耗尽区的长度对应于耗尽区的最大宽度。例如，沿着半导体衬底100的第一主表面110，第一沟槽的宽度可以是大致20-130nm，例如，40-120nm。
而且，长度与宽度的比率可以满足以下关系：s1/d1>2.0，其中s1表示如还在图1A中示意地沿着第一方向测量的突脊的长度。根据进一步的实施例，s1/d1>2.5。如在图1C和1D中所示，沟道区域220的宽度d1可以不同于漂移区260的宽度d2。根据进一步的实施例，漂移区260可以包括如在图1D中所示的不被图案化为形成突脊的平坦表面。
根据其中宽度d1≤2xld的实施例，晶体管200是所谓的“全耗尽”晶体管，其中当栅电极被设定为接通电势时，沟道区域220被完全地耗尽。在这种晶体管中，能够实现最佳亚阈值电压并且短沟道效应可以被高效地抑制，从而导致器件特性得以改进。
在另一方面，在包括场板的晶体管中，期望的是使用具有比宽度d1大得多的宽度d2的漂移区260。由于漂移区d2的、更大的宽度，漂移区260的电阻Rdson可以进一步降低，从而导致器件特性被进一步改进。为了改进在本体区域220中半导体器件的特性并且进一步改进在漂移区260中的器件特性，完成对栅电极和场板250图案化从而提供不同宽度的第一和第二突脊。
如已经进一步参考图1B讨论地，源极和漏极区域201、205沿着衬底的深度方向延伸。相应地，通过适当地设定源极和漏极区域201、205的深度，可以根据要求设定晶体管的电性质。由于栅电极210和场板250邻近于沟道区域220和漂移区260沿着深度方向延伸的特殊的另外特征，沿着沟道区域220的全部深度t1利用栅电极控制在沟道区域220中形成的沟道的传导性是可能的。以相应的方式，场板250沿着第二突脊的深度t2影响漂移区260的行为。因此，源极区域201和漏极区域205的深度确定晶体管200的有效宽度。因此，通过设定源极和漏极区域201、205的深度和宽度，可以确定器件的特性。例如，源极和漏极区域201、205的深度可以大于1µm。
通常，当在接通状态中操作时，邻近于栅介电层211在沟道区域220中形成传导反型层。根据一个实施例，反型层沿着该两个侧壁220b和220a中的至少一个延伸，电流主要地平行于第一主表面110流动。
如在图1C和1D中示意地，栅电极可以被置放在突脊的至少两侧处。根据进一步的实施例，栅电极可以被沿着突脊的两个竖直侧置放，而无任何栅电极被邻近于突脊的水平部分置放。以类似的方式，场板250可以被置放在漂移区260的三侧处。尽管如此，根据一个实施例，场板250仍然可以被邻近于漂移区260的仅仅竖直部分置放。根据图1所示实施例，栅电极210和场板250被相互分离。
根据一个实施例，在漂移区260内的掺杂浓度可以是恒定的。根据进一步的实施例，掺杂浓度可以随着距源极区域201的距离的增加而增加。此外，栅介电层211的厚度可以小于场板介电层251的厚度。场板介电层251的厚度可以是恒定的或者可以随着距源极区域201的距离增加而增加。而且，邻近于突脊的水平表面的场板介电层251的厚度可以不同于邻近于突脊的竖直部分的场板介电层251的厚度。例如，场板介电层251的竖直部分的厚度可以大于场板介电层251的水平部分。图1所示半导体器件可以进一步包括延伸到半导体衬底100的第一主表面110的触点。根据进一步的实施例，该半导体器件可以进一步包括到与半导体衬底100的第一主表面110相对的第二主表面的触点。根据一个实施例，被电耦接到源极区域201的源极触点202可以延伸到第一主表面110并且被电耦接到漏极区域205的漏电极206可以延伸到与第一主表面110相对的第二主表面。
图2示出半导体器件的进一步的实施例。半导体器件100包括晶体管2000，晶体管2000包括连接到源电极2020的源极区域2010。晶体管2000进一步包括连接到漏电极2060的漏极区域2050。晶体管2000进一步包括邻近于沟道区域2200置放并且利用栅介电层2110被从沟道区域2200绝缘的栅电极2100。晶体管2000进一步包括邻近于沟道区域2200置放的漂移区2600。源极区域2010、沟道区域2200、漂移区2600和漏极区域2050沿着第一方向延伸。
晶体管2000进一步包括利用第一场板电介质2510被从漂移区2600绝缘的第一场板2501。而且，晶体管2000进一步包括利用第二场板介电层2520被从漂移区2600绝缘的第二场板2502。根据图2所示实施例，第二场板2502具有不同于第一场板2501的形状和构造的形状和构造。例如，漂移区2600可以具有在第一场板2501之下的第一突脊的形状和在第二场板之下的第二突脊的形状并且第一突脊的宽度不同于第二突脊的宽度。例如，第二突脊的宽度可以大于第一突脊的宽度。而且，第二场板电介质2520的厚度可以不同于第一场板电介质2510的厚度。例如，第二场板电介质2520的厚度可以大于第一场板电介质2510的厚度。相应地，对于第一和第二场板2501、2502，很多参数可以是不同的。第一和第二场板2501、2502可以被保持于不同的电势V1、V2。如应该清楚理解地，根据一个实施例，晶体管2000可以包括多于两个场板。
图3A到3D示意制造根据一个实施例的半导体器件的步骤。
半导体衬底可以通过执行通常已知的浅沟槽隔离过程（STI）和注入步骤而被预处理。例如，可以执行阱注入步骤从而形成阱注入部分120，随后进行用于提供深本体连接注入区域225的进一步注入步骤和用于形成沟道区域220的掺杂步骤。此外，可以执行注入步骤从而限定漂移区260。在图3A所示实施例中，漂移区260是n掺杂的而沟道区域220是p掺杂的。深本体连接注入区域225是重度p掺杂的。如应该清楚理解地，可以应用颠倒的掺杂类型。
图3A示出在图1A所示I和I'之间的截面视图。在接着的步骤中，可选地，使用硬掩模，栅极沟槽212和场板沟槽252被以光刻方式限定和蚀刻。例如，沟槽可以具有大致500到5000nm的深度。在相邻栅极沟槽212之间的距离可以是30到300nm，并且在相邻场板沟槽252之间的距离可以是200到2000nm。栅极沟槽212和场板沟槽252被限定从而将沟道区域220和漂移区260图案化为第一和第二突脊。此后，例如通过低压CVD方法形成场板介电层251。例如，场板氧化物层可以具有30到500nm的厚度。此后，可以执行光刻步骤，从而从不必要的部分蚀刻场氧化物。
图3B示出所产生的结构的一个实例的截面视图。在如在图1A中所示IV和IV之间截取图3B的截面视图。如所示出地，场板沟槽252可以延伸到比栅极沟槽212更深的深度。场介电层251仅仅在场板沟槽252中形成。
此后，可以例如通过热氧化来形成栅介电层211。例如，栅介电层211可以具有5到50nm的厚度。然后，形成了形成栅电极210和场板250的传导材料。例如，可以沉积多晶硅。例如，多晶硅层可以具有50到200nm的厚度。多晶硅材料可以是n掺杂的或者可以是非掺杂的并且可以在沉积之后掺杂。然后，传导材料被图案化从而形成栅电极210和场板250。
图3C示出所产生的结构的一个实例。如所示出地，形成栅电极210从而邻近于沟道区域220并且置放场板250从而邻近于漂移区260。此后，限定接触沟槽从而提供到源极和漏极区域201、205的连接。例如，可选地使用硬掩模层，接触沟槽可以被以光刻方式限定和蚀刻。然后，可以执行例如利用n型掺杂剂的倾斜注入步骤，从而形成源极区域201和漏极区域205。例如，源极区域201和漏极区域205可以延伸到不同的深度。例如，源极区域201和漏极区域205可以延伸到大致500到5000nm的深度。例如，源极区域201和漏极区域205中的任何一个可以延伸到与栅极沟槽212的深度大致相同或者更小的深度。术语“大致相同的深度”旨在意味着由于工艺诱导的变化，源极区域201和漏极区域205中的任何一个的深度可以比栅极沟槽212的深度小大约10%。可选地，可以执行进一步p+的注入步骤以进一步掺杂直接地在沟道区域220之下置放的部分，以形成p+掺杂本体连接注入区域225。可以在限定源极和漏极区域201、205之前或者之后执行这个进一步的p+注入步骤。然后，在接触沟槽中填充用于形成源电极202和漏电极206的传导材料。例如，传导材料可以包括多晶硅或者包括Ti、TiN和钨（W）的叠层。传导材料可以被回蚀刻。可以形成触点并且可以执行通用于晶体管制造的进一步的加工步骤。
根据另一个实施例，能够在以后的加工阶段，例如在所谓的MOL（中段制程（mid-of-line））加工步骤期间执行倾斜注入步骤和接触沟槽加工。
根据进一步的实施例，接触沟槽可以被蚀刻到比在图3D中示意的更深的深度从而提供与半导体器件的第二主表面的接触。
图3D示出所产生的结构的一个实例。
图4A示意根据一个实施例的、制造半导体器件的方法。如在图4A中示意地，该方法可以包括在半导体衬底中形成晶体管，该半导体衬底包括第一主表面，其中形成晶体管包括形成源极区域（S40）、漏极区域（S40）、沟道区域（S10）、漂移区（S20）和邻近于沟道区域的栅电极（S30），其中沟道区域和漂移区被形成为沿着第一方向置放，该第一方向平行于在源极区域和漏极区域之间的第一主表面，其中沟道区域在具有沿着第一方向延伸的第一突脊的形状的衬底部分中形成，第一突脊具有第一宽度d1，使得：d1≤2xld，其中ld表示在栅电极和第一突脊之间的界面处形成的耗尽区的长度。可选地，该方法可以进一步包括形成场板（S35）。根据实施例，单加工方法的顺序性可以改变并且能够根据一般的工艺要求确定。
图4B示意根据进一步的实施例的、一种制造半导体器件的方法。根据该实施例，一种制造半导体器件的方法包括在半导体衬底中形成晶体管，该半导体衬底包括第一主表面，其中形成晶体管包括形成源极区域（S40）、漏极区域（S40）、沟道区域（S10）、漂移区（S20）和邻近于沟道区域的栅电极（S30），其中沟道区域和漂移区被形成为沿着第一方向置放，第一方向平行于在源极区域和漏极区域之间的第一主表面。形成沟道区域（S10）可以包括在半导体衬底中限定第一突脊，该第一突脊沿着第一方向延伸。限定第一突脊并且形成栅电极（S30）可以通过在半导体衬底中形成栅极沟槽（S15）并且形成传导层（S17）从而填充相邻沟槽而完成。
根据进一步的实施例，形成漂移区（S20）可以包括在半导体衬底中限定第二突脊，该第二突脊沿着第一方向延伸。限定第二突脊并且形成场板（S35）可以通过在半导体衬底中形成场板沟槽（S25）并且形成传导层（S27）从而填充相邻沟槽而完成。
通过形成栅极沟槽和可选地场板沟槽并且此后形成传导层从而填充相邻沟槽来形成晶体管指的是所谓的镶嵌（damascene）制造方法。根据这种方法，能够免除图案化传导层从而形成栅电极的、邻近于第一突脊的竖直侧壁的部分。类似地，能够免除图案化传导层从而形成场板的、邻近于第二突脊的竖直侧壁的部分。因此，这种方法进一步简化制造半导体器件的方法。
如已经在前面示意地，本说明书的实施例涉及一种被实现为使得电流能够大致平行于半导体衬底200的第一主表面110流动的、所谓的横向器件的半导体器件。相应地，例如，可以以容易的方式形成源极和漏极区域并且可以邻近于衬底的第一主表面110地加工所有的器件部件。沟道区域220具有突脊的形状，因此实现三维结构。栅电极210被置放在沿着沟道区域220的整个深度延伸的栅极沟槽212中。相应地，可以在全部深度的晶体管上完成在沟道区域220中形成的传导沟道的控制。而且，由于存在场板250，完成了利用场板250在漂移区260中的电荷补偿。根据一个实施例，场板250被置放在沿着衬底的深度方向延伸的场板沟槽252中。相应地，在断开状态中，利用场板250耗尽漂移区260中的电荷载流子可以容易地并且有效地完成。根据其中沟道区域220具有拥有特殊宽度的突脊的形状的实施例，当施加对应于接通状态的栅电压时，晶体管可以被完全地耗尽。由此，实现了具有改进的亚阈值斜率特性的晶体管。此外，有效晶体管宽度增加，从而晶体管的有效面积增加而不增加所要求的空间。
虽然以上已经描述了本发明的实施例，但是显然，可以实现进一步的实施例。例如，进一步的实施例可以包括在权利要求中叙述的特征的任何次级组合或者在以上给出的实例中描述的元件的任何次级组合。相应地，所附权利要求的这个精神和范围不应该限制于在这里包含的实施例的说明。

Claims (22)

1.一种包括在具有第一主表面的半导体衬底中形成的晶体管的半导体器件，所述晶体管包括：
源极区域；
漏极区域；
沟道区域；
漂移区；
邻近于所述沟道区域的栅电极，所述栅电极被配置为控制在所述沟道区域中形成的沟道的传导性，所述沟道区域和所述漂移区在所述源极区域和所述漏极区域之间被沿着第一方向置放，所述第一方向平行于所述第一主表面，所述沟道区域通过在所述半导体衬底中的相邻的第一沟槽被图案化为沿着所述第一方向延伸的第一突脊；和
邻近于所述漂移区布置的第一场板，
其中所述栅电极布置在沿着所述第一方向延伸的栅极沟槽中，并且所述第一场板布置在沿着所述第一方向延伸的场板沟槽中，其中所述栅极沟槽和所述场板沟槽被形成为使得在相邻栅极沟槽之间的节距不同于在相邻场板沟槽之间的节距。
2.根据权利要求1所述的半导体器件，其中所述栅电极被置放在所述第一突脊的至少两侧处。
3.根据权利要求1所述的半导体器件，其中所述第一突脊包括顶侧和两个侧壁。
4.根据权利要求3所述的半导体器件，其中当所述半导体器件在接通状态中操作时，沿着所述侧壁中的至少一个形成传导反型层。
5.根据权利要求1所述的半导体器件，其中所述漂移区的一个部分通过在所述半导体衬底中的相邻的第二沟槽被图案化为沿着所述第一方向延伸的第二突脊。
6.根据权利要求5所述的半导体器件，其中所述第一场板的部分被置放在所述第二突脊的至少两侧处。
7.根据权利要求5所述的半导体器件，其中所述第二突脊具有与所述第一突脊的宽度不同的宽度。
8.根据权利要求1所述的半导体器件，其中所述栅电极和所述第一场板被相互隔离。
9.根据权利要求1所述的半导体器件，进一步包括第二场板，所述第二场板在所述第一场板和所述漏极区域之间被沿着所述第一方向邻近于所述第一主表面布置。
10.根据权利要求9所述的半导体器件，其中所述第二场板被耦接到电势并且所述第一场板被耦接到与耦接到所述第二场板的电势不同的电势。
11.根据权利要求5所述的半导体器件，其中所述漂移区的进一步的部分通过在所述半导体衬底中的相邻的第三沟槽被图案化为沿着所述第一方向延伸的第三突脊，所述半导体器件进一步包括第二场板，所述第二场板在所述第一场板和所述漏极区域之间被邻近于所述第三突脊布置。
12.根据权利要求11所述的半导体器件，其中所述第三突脊具有与所述第二突脊的宽度不同的宽度。
13.根据权利要求1所述的半导体器件，其中所述第一突脊的宽度d是：d≤2ld，其中ld表示在所述第一突脊和所述栅电极之间的界面处形成的耗尽区的长度。
14.根据权利要求1所述的半导体器件，其中所述源极和所述漏极区域被置放在所述半导体衬底内并且大致地延伸到所述栅电极沿着所述半导体衬底的深度方向从所述第一主表面延伸至的深度。
15.一种包括在具有第一主表面的半导体衬底中形成的晶体管的半导体器件，所述晶体管包括：
源极区域；
漏极区域；
沟道区域；
漂移区；
邻近于所述沟道区域的栅电极，所述栅电极被配置为控制在所述沟道区域中形成的沟道的传导性，所述沟道区域和所述漂移区在所述源极区域和所述漏极区域之间被沿着第一方向置放，所述第一方向平行于所述第一主表面，所述沟道区域通过在所述半导体衬底中的相邻的第一沟槽被图案化为沿着所述第一方向延伸的第一突脊；以及
邻近于所述漂移区布置的第一场板，所述第一场板在第一方向上延伸，其中所述漂移区的一个部分通过在所述半导体衬底中的相邻的第二沟槽被图案化为沿着所述第一方向延伸的第二突脊，
其中所述栅电极布置在沿着所述第一方向延伸的栅极沟槽中，并且所述第一场板布置在沿着所述第一方向延伸的场板沟槽中，其中所述栅极沟槽和所述场板沟槽被形成为使得在相邻栅极沟槽之间的节距不同于在相邻场板沟槽之间的节距。
16.根据权利要求15所述的半导体器件，其中所述栅电极被置放在所述第一突脊的至少两侧处。
17.根据权利要求15所述的半导体器件，其中所述第一突脊包括顶侧和两个侧壁。
18.根据权利要求17所述的半导体器件，其中当所述半导体器件在接通状态中操作时，沿着所述侧壁中的至少一个形成传导反型层。
19.根据权利要求15所述的半导体器件，其中所述第一场板的部分被置放在所述第二突脊的至少两侧处。
20.一种在半导体衬底中制造半导体器件的方法，所述半导体衬底包括第一主表面和晶体管，其中形成所述晶体管包括：
形成源极区域、漏极区域、沟道区域、漂移区和邻近于所述沟道区域的栅电极，其中所述沟道区域和所述漂移区被形成为在所述源极区域和所述漏极区域之间沿着第一方向置放，所述第一方向平行于所述第一主表面，其中形成所述沟道区域包括在所述半导体衬底中形成第一突脊，所述第一突脊沿着所述第一方向延伸，所述第一突脊具有第一宽度d1，使得：d1≤2ld，其中ld表示在所述第一突脊和栅电介质之间的界面处形成的耗尽区的长度，所述栅电介质被置放在所述第一突脊和所述栅电极之间，以及
形成邻近于所述漂移区的场板，
其中形成所述栅电极包括在所述半导体衬底中形成栅极沟槽并且形成所述场板包括在所述半导体衬底中形成场板沟槽，其中所述栅极沟槽和所述场板沟槽被形成为使得在相邻栅极沟槽之间的节距不同于在相邻场板沟槽之间的节距，形成所述栅极沟槽并且形成所述场板沟槽是通过联合蚀刻工艺而执行的。
21.根据权利要求20所述的方法，其中形成所述第一突脊并且形成所述栅电极是通过包括在所述半导体衬底中形成栅极沟槽并且形成传导层从而填充相邻沟槽的方法而完成的。
22.根据权利要求20所述的方法，其中形成场板包括在所述半导体衬底中形成场板沟槽并且形成传导层从而填充所述场板沟槽。
CN201310634761.8A 2012-12-03 2013-12-03 半导体器件和制造半导体器件的方法 Active CN103855221B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/692059 2012-12-03
US13/692,059 2012-12-03
US13/692,059 US9799762B2 (en) 2012-12-03 2012-12-03 Semiconductor device and method of manufacturing a semiconductor device

Publications (2)

Publication Number Publication Date
CN103855221A CN103855221A (zh) 2014-06-11
CN103855221B true CN103855221B (zh) 2017-07-11

Family

ID=50726165

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310634761.8A Active CN103855221B (zh) 2012-12-03 2013-12-03 半导体器件和制造半导体器件的方法

Country Status (5)

Country Link
US (1) US9799762B2 (zh)
KR (1) KR101552022B1 (zh)
CN (1) CN103855221B (zh)
DE (1) DE102013113284B4 (zh)
TW (1) TWI539602B (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9735243B2 (en) 2013-11-18 2017-08-15 Infineon Technologies Ag Semiconductor device, integrated circuit and method of forming a semiconductor device
US8847311B2 (en) * 2012-12-31 2014-09-30 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
US9123801B2 (en) 2013-09-16 2015-09-01 Infineon Technologies Ag Semiconductor device, integrated circuit and method of manufacturing a semiconductor device
US9461164B2 (en) 2013-09-16 2016-10-04 Infineon Technologies Ag Semiconductor device and method of manufacturing the same
US9287404B2 (en) 2013-10-02 2016-03-15 Infineon Technologies Austria Ag Semiconductor device and method of manufacturing a semiconductor device with lateral FET cells and field plates
US9306058B2 (en) 2013-10-02 2016-04-05 Infineon Technologies Ag Integrated circuit and method of manufacturing an integrated circuit
US9401399B2 (en) 2013-10-15 2016-07-26 Infineon Technologies Ag Semiconductor device
US9293533B2 (en) * 2014-06-20 2016-03-22 Infineon Technologies Austria Ag Semiconductor switching devices with different local transconductance
DE102014114184B4 (de) * 2014-09-30 2018-07-05 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleitervorrichtung und Halbleitervorrichtung
US9748378B2 (en) * 2015-03-12 2017-08-29 Infineon Technologies Ag Semiconductor device, integrated circuit and method of manufacturing a semiconductor device
DE102015105632B4 (de) 2015-04-14 2016-09-01 Infineon Technologies Ag Halbleitervorrichtung mit einem transistor
DE102015105679B4 (de) * 2015-04-14 2017-11-30 Infineon Technologies Ag Halbleitervorrichtung, integrierte schaltung und verfahren zum herstellen der halbleitervorrichtung
DE102015106683B4 (de) 2015-04-29 2021-11-25 Infineon Technologies Ag Halbleitervorrichtung mit einem feldeffekttransistor und verfahren zum herstellen der halbleitervorrichtung
DE102015109538B3 (de) * 2015-06-15 2016-12-08 Infineon Technologies Ag Transistor mit verbessertem Lawinendurchbruchsverhalten und Verfahren zur Herstellung
DE102015112427B4 (de) * 2015-07-29 2017-04-06 Infineon Technologies Ag Halbleitervorrichtung mit einer allmählich zunehmenden Felddielektrikumsschicht und Verfahren zum Herstellen einer Halbleitervorrichtung
DE102016107714B4 (de) * 2015-08-14 2019-07-18 Infineon Technologies Dresden Gmbh Halbleitervorrichtung mit einer Transistorzelle, die einen Sourcekontakt in einem Graben umfasst, Verfahren zum Herstellen der Halbleitervorrichtung und integrierte Schaltung
DE102015119771A1 (de) * 2015-11-16 2017-05-18 Infineon Technologies Ag Halbleitervorrichtung mit einem ersten Transistor und einem zweiten Transistor
US9799764B2 (en) * 2015-12-31 2017-10-24 Sk Hynix System Ic Inc. Lateral power integrated devices having low on-resistance
DE102016101676B3 (de) 2016-01-29 2017-07-13 Infineon Technologies Ag Elektrische schaltung, die eine halbleitervorrichtung mit einem ersten transistor und einem zweiten transistor und eine steuerschaltung enthält
DE102016101679B4 (de) * 2016-01-29 2019-03-28 Infineon Technologies Austria Ag Halbleitervorrichtung mit einem lateralen Transistor
US10128750B2 (en) 2016-03-04 2018-11-13 Infineon Technologies Ag Switched-mode power converter with an inductive storage element and a cascode circuit
US9985126B2 (en) 2016-03-04 2018-05-29 Infineon Technologies Ag Semiconductor device comprising a first gate electrode and a second gate electrode
DE102016106872A1 (de) 2016-04-13 2017-10-19 Infineon Technologies Ag Verfahren zum herstellen einer integrierten schaltung einschliesslich eines lateralen graben-transistors und eines logikschaltungselements
DE102016113393A1 (de) * 2016-07-20 2018-01-25 Infineon Technologies Ag Halbleitervorrichtung, die ein Transistor-Array und ein Abschlussgebiet enthält, und Verfahren zum Herstellen solch einer Halbleitervorrichtung
US10522677B2 (en) * 2017-09-26 2019-12-31 Nxp Usa, Inc. Field-effect transistor and method therefor
US10600911B2 (en) * 2017-09-26 2020-03-24 Nxp Usa, Inc. Field-effect transistor and method therefor
DE102017122634A1 (de) 2017-09-28 2019-03-28 Infineon Technologies Ag Siliziumcarbid-Halbleitervorrichtung mit Graben-Gatestruktur und vertikalem Pn-Übergang zwischen einem Bodygebiet und einer Driftstruktur
US10163640B1 (en) * 2017-10-31 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Gate isolation plugs structure and method
CN109065635B (zh) * 2018-08-22 2021-05-14 电子科技大学 一种横向二极管器件
US11508842B2 (en) * 2020-07-06 2022-11-22 Texas Instruments Incorporated Fin field effect transistor with field plating

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6353252B1 (en) * 1999-07-29 2002-03-05 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device having trenched film connected to electrodes
US8115253B2 (en) * 2009-09-10 2012-02-14 United Microelectronics Corp. Ultra high voltage MOS transistor device

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828101A (en) 1995-03-30 1998-10-27 Kabushiki Kaisha Toshiba Three-terminal semiconductor device and related semiconductor devices
JP3405681B2 (ja) * 1997-07-31 2003-05-12 株式会社東芝 半導体装置
DE19818300C1 (de) 1998-04-23 1999-07-22 Siemens Ag Lateraler Hochvolt-Seitenwandtransistor
JP3356162B2 (ja) 1999-10-19 2002-12-09 株式会社デンソー 半導体装置及びその製造方法
GB0012138D0 (en) 2000-05-20 2000-07-12 Koninkl Philips Electronics Nv A semiconductor device
JP4528460B2 (ja) 2000-06-30 2010-08-18 株式会社東芝 半導体素子
JP3534084B2 (ja) 2001-04-18 2004-06-07 株式会社デンソー 半導体装置およびその製造方法
US7786533B2 (en) 2001-09-07 2010-08-31 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
JP2003203930A (ja) 2002-01-08 2003-07-18 Nec Compound Semiconductor Devices Ltd ショットキーゲート電界効果型トランジスタ
US6589845B1 (en) * 2002-07-16 2003-07-08 Semiconductor Components Industries Llc Method of forming a semiconductor device and structure therefor
DE10313712B4 (de) * 2003-03-27 2008-04-03 Infineon Technologies Ag Laterales mittels Feldeffekt steuerbares Halbleiterbauelement für HF-Anwendungen
US7714384B2 (en) 2003-09-15 2010-05-11 Seliskar John J Castellated gate MOSFET device capable of fully-depleted operation
US7279744B2 (en) 2003-11-14 2007-10-09 Agere Systems Inc. Control of hot carrier injection in a metal-oxide semiconductor device
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
US7126166B2 (en) * 2004-03-11 2006-10-24 Semiconductor Components Industries, L.L.C. High voltage lateral FET structure with improved on resistance performance
US7573078B2 (en) * 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates
US7132333B2 (en) 2004-09-10 2006-11-07 Infineon Technologies Ag Transistor, memory cell array and method of manufacturing a transistor
DE102004031385B4 (de) 2004-06-29 2010-12-09 Qimonda Ag Verfahren zur Herstellung von Stegfeldeffekttransistoren in einer DRAM-Speicherzellenanordnung, Feldeffekttransistoren mit gekrümmtem Kanal und DRAM-Speicherzellenanordnung
DE102004047772B4 (de) * 2004-09-30 2018-12-13 Infineon Technologies Ag Lateraler Halbleitertransistor
DE102004056772B4 (de) 2004-11-24 2007-01-11 Infineon Technologies Austria Ag Laterale Halbleiterbauelemente mit hoher Spannungsfestigkeit und Verfahren zur Herstellung derselben
US11791385B2 (en) * 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
AT504998A2 (de) 2005-04-06 2008-09-15 Fairchild Semiconductor Trenched-gate-feldeffekttransistoren und verfahren zum bilden derselben
US7382019B2 (en) 2005-04-26 2008-06-03 Fairchild Semiconductor Corporation Trench gate FETs with reduced gate to drain charge
JP4304198B2 (ja) 2006-09-15 2009-07-29 株式会社東芝 半導体装置
JP2008124346A (ja) 2006-11-14 2008-05-29 Toshiba Corp 電力用半導体素子
WO2008086366A2 (en) 2007-01-09 2008-07-17 Maxpower Semiconductor, Inc. Semiconductor device
JP2008227474A (ja) * 2007-02-13 2008-09-25 Toshiba Corp 半導体装置
JP5383009B2 (ja) 2007-07-17 2014-01-08 三菱電機株式会社 半導体装置の設計方法
WO2009012536A1 (en) 2007-07-20 2009-01-29 Interuniversitair Microelektronica Centrum Damascene contacts on iii-v cmos devices
US20090108343A1 (en) 2007-10-31 2009-04-30 Gennadiy Nemtsev Semiconductor component and method of manufacture
TWI368324B (en) 2007-11-06 2012-07-11 Nanya Technology Corp Recessed-gate transistor device and mehtod of making the same
EP2248159A4 (en) 2008-02-14 2011-07-13 Maxpower Semiconductor Inc SEMICONDUCTOR COMPONENT STRUCTURES AND SAME PROCESSES
US7888732B2 (en) 2008-04-11 2011-02-15 Texas Instruments Incorporated Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric
US8193565B2 (en) 2008-04-18 2012-06-05 Fairchild Semiconductor Corporation Multi-level lateral floating coupled capacitor transistor structures
JP5385679B2 (ja) 2008-05-16 2014-01-08 旭化成エレクトロニクス株式会社 横方向半導体デバイスおよびその製造方法
CN101419981A (zh) 2008-12-04 2009-04-29 电子科技大学 一种槽栅soi ligbt器件
US7884394B2 (en) 2009-02-09 2011-02-08 Transphorm Inc. III-nitride devices and circuits
JP2011009595A (ja) 2009-06-29 2011-01-13 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
US8178922B2 (en) 2010-01-14 2012-05-15 Force Mos Technology Co., Ltd. Trench MOSFET with ultra high cell density and manufacture thereof
CN102157493B (zh) 2010-02-11 2013-07-24 上海华虹Nec电子有限公司 金属塞及其制造方法
WO2011111500A1 (ja) 2010-03-09 2011-09-15 富士電機システムズ株式会社 半導体装置
JP5580150B2 (ja) 2010-09-09 2014-08-27 株式会社東芝 半導体装置
CN102412295A (zh) * 2010-09-21 2012-04-11 株式会社东芝 半导体装置及其制造方法
US8536648B2 (en) 2011-02-03 2013-09-17 Infineon Technologies Ag Drain extended field effect transistors and methods of formation thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6353252B1 (en) * 1999-07-29 2002-03-05 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device having trenched film connected to electrodes
US8115253B2 (en) * 2009-09-10 2012-02-14 United Microelectronics Corp. Ultra high voltage MOS transistor device

Also Published As

Publication number Publication date
TWI539602B (zh) 2016-06-21
US9799762B2 (en) 2017-10-24
DE102013113284B4 (de) 2023-03-30
TW201424002A (zh) 2014-06-16
KR101552022B1 (ko) 2015-09-09
DE102013113284A1 (de) 2014-06-05
US20140151798A1 (en) 2014-06-05
KR20140071245A (ko) 2014-06-11
CN103855221A (zh) 2014-06-11

Similar Documents

Publication Publication Date Title
CN103855221B (zh) 半导体器件和制造半导体器件的方法
CN105977290B (zh) 半导体器件、集成电路和制造半导体器件的方法
CN103915499B (zh) 半导体器件和制造半导体器件的方法
CN103579339B (zh) 半导体器件
CN103855222B (zh) 半导体器件和制造半导体器件的方法
CN103794649B (zh) 半导体器件和用于制造半导体器件的方法
CN104752492B (zh) 用于制造半导体器件的方法和半导体器件
KR101511429B1 (ko) 반도체 장치 및 반도체 장치를 제조하는 방법
CN105405868A (zh) 具有包括埋入部分的控制结构的半导体器件及制造方法
CN104465767B (zh) 半导体器件、集成电路及半导体器件的制造方法
US20150145029A1 (en) Semiconductor device having buried gate electrode structures
CN104956489B (zh) 半导体装置、集成电路和形成半导体装置的方法
CN103208424B (zh) 用于制造半导体元件的方法及场效应半导体元件
CN106098774A (zh) 包括场效应晶体管的半导体器件及制造半导体器件的方法
CN104347625B (zh) 集成电路以及制造集成电路的方法
CN106057893A (zh) 半导体器件、集成电路以及用于制造半导体器件的方法
CN104465771B (zh) 具有场电极的晶体管器件
US9685511B2 (en) Semiconductor device and method for manufacturing a semiconductor device
US11705506B2 (en) Lateral trench transistor device
WO2013175880A1 (ja) 炭化珪素半導体装置およびその製造方法
JP2006108217A (ja) 炭化珪素半導体装置
CN104600067B (zh) 集成电路和制造集成电路的方法
CN105470140B (zh) 制造半导体器件的方法和半导体器件
KR101653456B1 (ko) 반도체 디바이스 및 반도체 디바이스를 제작하기 위한 방법
US20200279912A1 (en) Super junction semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant