CN103608925B - 制造薄膜晶体管器件的方法 - Google Patents
制造薄膜晶体管器件的方法 Download PDFInfo
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- CN103608925B CN103608925B CN201280028791.8A CN201280028791A CN103608925B CN 103608925 B CN103608925 B CN 103608925B CN 201280028791 A CN201280028791 A CN 201280028791A CN 103608925 B CN103608925 B CN 103608925B
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
本发明内容的实施例了提供制造薄膜晶体管器件的方法,对形成于薄膜晶体管器件中的有源层的周边侧壁有良好的轮廓控制。在一实施例中,一种制造薄膜晶体管器件的方法包括:提供基板,所述基板具有有源层形成于其上,源极‑漏极金属电极层设置在所述有源层上,其中有源层为金属氧化物层;进行背沟道蚀刻工艺以于源极‑漏极金属电极层中形成沟道;以及在背沟道蚀刻工艺之后进行有源层图案化工艺。
Description
技术领域
本发明的实施例是大体上关于形成应用于薄膜晶体管的器件结构的方法。特别地,本发明关于形成应用于薄膜晶体管的器件结构的方法以及顺序。
背景技术
等离子体显示面板、有源矩阵液晶显示器(AMLCD)或有源矩阵有机发光二极管显示器(AMOLED),以及液晶显示器(LCD)常用来作为平面显示器。LCD通常包含两片相互连接的透明基板,以及夹置于其间的液晶材料层。透明基板可为半导体基板、玻璃、石英、蓝宝石、柔性或透明塑胶薄膜。LCD也可包含发光二极管,用以作为背光源。
随着对于LCD解析度的要求提高,控制大量液晶单元的个别区域(称为像素)已变得相当重要。在现代的显示面板中,可存在超过1,000,000个像素。至少有相同数目的晶体管形成于玻璃基板上,以使得各个像素相对于设置在基板上的其他像素可于开、关状态(energized and de-energized states)间切换。
图1绘示制造常规薄膜晶体管器件的顺序。图2A至2D绘示以图1所示的顺序制造、于不同的制造阶段的常规薄膜晶体管器件。一般而言,薄膜晶体管器件200设置于基板202上,如图2A所示。栅极电极204于基板202上形成并图案化,接着则是栅极绝缘层206。有源层208是形成于栅极绝缘层206上。有源层208通常是选自具有高电子移动率及低温制造工艺要求的透明金属氧化物材料,以允许如塑胶材料之类的柔性基板材料的使用,以于低温进行处理而避免基板的损坏。在有源层208形成之后,蚀刻停止层210形成于有源层208上。接着,源极-漏极金属电极层214是设置于蚀刻停止层210上,形成具有通过图案化的光阻层216暴露于外的区域218的薄膜晶体管元件200,以在接下来的蚀刻与图案化工艺于源极-漏极金属电极层214中形成沟道。
请再参照图1,在器件结构200形成于基板202上之后,于步骤102,基板202接着被运送至金属有源层图案化工具,以进行金属有源层图案化工艺,从器件结构200中移除有源层208的未受保护的区域230,暴露出下方栅极绝缘层206的暴露区域226,如图2B所示。值得注意的是,有源层208的未受保护的区域230可能因先前的工艺而受到损坏或者未受到损坏,如图2A所示的不平坦表面。在金属有源层图案化工艺之后,于步骤104,进行背沟道蚀刻(BCE)工艺,蚀刻源极-漏极金属电极层214以于薄膜晶体管器件200中形成沟道228,直到暴露出下方蚀刻停止层210的上表面220,如图2C所示。在背沟道蚀刻(BCE)工艺中,于蚀刻工艺所使用的攻击性蚀刻剂可能不利地蚀刻和攻击器件200的下方的有源层208,导致有源层208内的损坏和不期望的边缘轮廓222,因此恶化薄膜晶体管器件200的薄膜品质和电性表现。于步骤106,基板202接着被运送至光阻层移除处理工具,以移除光阻层216,如图2D所示。在光阻层移除工艺中,在接下来的工艺以及于步骤108进行的其他钝化与图案化工艺,有源层208的边缘222可能受到更进一步地损坏或攻击以便使器件制造工艺完整,因而不利地恶化有源层208的薄膜品质,并导致器件失效。
因此,需要一种制造具有改良的电性表现与稳定性的薄膜晶体管器件的方法。
发明内容
本发明的实施例提供制造薄膜晶体管器件的方法,对形成于薄膜晶体管器件中的有源层有良好的轮廓控制。在一实施例中,一种制造薄膜晶体管器件的方法包括:提供具有设置在有源层上的源极-漏极金属电极层的基板,其中有源层为金属氧化物层;进行背沟道蚀刻工艺以在源极-漏极金属电极层形成沟道;以及在背沟道蚀刻工艺之后进行有源层图案化工艺。
附图说明
简略综述如上的本发明更特定的描述可参照实施例而取得,该等实施例中的某些实施例示出于附图中。如此,可以获得并详尽地理解本发明以上节录的特征。
图1绘示常规执行的器件结构的制造顺序。
图2A至2D为根据图1所示的常规制造方法的常规薄膜晶体管器件结构的剖面图。
图3绘示根据本发明内容的一实施例的器件结构的制造顺序。
图4A至4D为根据图3所示的顺序的薄膜晶体管器件结构的剖面图。
为便于理解,说明书与说明书附图中尽可能地使用相同的附图标记来表示相同的元件。一实施例中的元件与特征亦可能出现于其他实施例中,以达较佳的实施方式,而相同的描述内容则就此省略。
然而,应当注意到,说明书附图仅仅图解说明了本发明的示例性实施例,因此不应被视为限制本发明的范围,因为本发明可适用于其他等效的实施例。
具体实施方式
本发明内容的实施例提供了制造薄膜晶体管器件的方法,对形成于薄膜晶体管器件中的有源孤立层的周边侧壁有良好的轮廓控制。在一实施例中,对有源层维持良好的轮廓控制的方法可用于薄膜晶体管(TFT)器件、光电二极管、半导体二极管、发光二极管(LED)、有机发光二极管或其他合适的显示应用。相较于先蚀刻有源层、后蚀刻金属电极层,而使得侧壁暴露于金属电极层蚀刻剂的常规技术,对形成于薄膜晶体管器件中的有源层的良好轮廓控制有利地提供了晶体管及二极管器件的有效电性性能,而能同时保护器件结构免于受损。在常规的器件中,无法控制有源层周边侧壁以及蚀刻带来的损坏导致了常规器件的电性性能下降。
图3绘示根据本发明内容一实施例的薄膜晶体管器件的制造顺序。图4A至4D绘示以图3所示的顺序制造、于不同的工艺阶段的薄膜晶体管器件。如图4A所示,薄膜晶体管器件400设置在基板402上,基板402上依序形成栅极电极层404、栅极绝缘层406及有源层408。值得注意的是,基板402上可预先形成薄膜、结构或层的不同组合,以便于在基板402上形成不同的器件结构。在一实施例中,基板402可为玻璃基板、塑胶基板、聚合物基板、金属基板、单片基板、卷绕式基板或其他适于在其上形成薄膜晶体管的合适的透明基板的任一者。在一实施例中,栅极电极层404可由任何合适的金属材料制造而成,例如铟锡氧化物(ITO)、铟锌氧化物(IZO)、铟锌锡氧化物(ITZO)、铝(Al)、钨(W)、铬(Cr)、钽(Ta)、钛(Ti)、钼(Mo)或其组合。栅极绝缘层406可由二氧化硅(SiO2)、四乙氧基硅烷(TEOS)、氮氧化硅(SiON)及氮化硅(SiN)等制造而成。此外,有源层408可由金属氧化物制造而成,金属氧化物例如是铟镓锌氧化物(InGaZnO)、铟镓锌氮氧化物(InGaZnON)、氧化锌(ZnO)、氮氧化锌(ZnON)、锌锡氧化物(ZnSnO)、镉锡氧化物(CdSnO)、镓锡氧化物(GaSnO)、钛锡氧化物(TiSnO)、铜铝氧化物(CuAlO)、锶铜氧化物(SrCuO)、镧铜硫氧化物(LaCuOS)、氮化镓(GaN)、铟镓氮化物(InGaN)、铝镓氮化物(AlGaN)或铟镓铝氮化物(InGaAlN)等。在特定的一实施例中,有源层408由InGaZnO制造而成。值得注意的是,有源层408未受器件400保护的、暴露于外的部分422可能或可能不会因先前的工艺而受到损坏,而具有不平坦表面(如图4A-4C所示)。
接着,蚀刻停止层410形成于有源层408上。蚀刻停止层410可为介电层、含有金属的介电层、金属层或其他合适的材料。在一实施例中,蚀刻停止层410可由选自由含钛(Ti)材料、含钽(Ta)材料、含硅材料、含锌材料、含铪材料及其他合适的介电材料所组成的群组的材料制造而成。在一示范性实施例中,蚀刻停止层410为二氧化钛(TiO2)层或五氧化二钽(Ta2O5)层。源极-漏极金属电极层412可沉积于蚀刻停止层410上。源极-漏极金属电极层412可由能够被图案化以定义出薄膜晶体管器件400的源极及漏极接触点的导电材料制造而成。在一实施例中,源极-漏极金属电极层412以光刻工艺线形图案化。在一实施例中,源极-漏极金属电极层412可由选自由铜(Cu)、金(Au)、银(Ag)、铝(Al)、钨(W)、钼(Mo)、铬(Cr)、钽(Ta)、钛(Ti)、其合金或其组合所组成的群组的材料制造而成。在一示范性实施例中,源极-漏极金属电极层412为钼(Mo)层或钛(Ti)层。图案化的光阻层414形成于源极-漏极金属电极层412上,以形成开口416,开口416暴露出源极-漏极金属电极层412的表面418供蚀刻之用。
请再参照图3,于步骤302,基板402被运送至处理工具以进行背沟道蚀刻(BCE)工艺,蚀刻源极-漏极金属电极层412以于薄膜晶体管器件400中形成沟道426,直到暴露出下方蚀刻停止层410的上表面420,如图4B所示。背沟道蚀刻(BCE)工艺可为任何能够于源极-漏极金属电极层412中形成沟道426的合适蚀刻工艺,包括干蚀刻、湿蚀刻或离子等离子体蚀刻等等。对于源极-漏极金属电极层412进行背沟道蚀刻(BCE)工艺,直到蚀刻停止层410的上表面420通过沟道426暴露出来,以便使背沟道蚀刻(BCE)工艺完整。
在BCE工艺为干蚀刻工艺的一实施例中,源极-漏极金属电极层412为含铬(Cr)金属,而用以对源极-漏极金属电极层412进行干蚀刻的化学物质为含氯(Cl)气体。该含氯气体可包括氯气(Cl2)或三氯化硼(BCl3)等等,但不限于此。在另一实施例中,源极-漏极金属电极层412为含钼(Mo)金属,而用以对源极-漏极金属电极层412进行干蚀刻的化学物质为含氟(F)气体。该含氟气体可包括六氟化硫(SF6)、四氟甲烷(CF4)或二氟乙炔(C2F2)等等,但不限于此。
在BCE工艺为湿蚀刻工艺的实施例中,源极-漏极金属电极层412为含钼(Mo)金属,而用以对源极-漏极金属电极层412进行湿蚀刻的化学物质可包括过氧化氢(H2O2)或过氧化氢/氢氧化钾(H2O2/KOH)等等,但不限于此。
于步骤304,在沟通426形成于源极-漏极金属电极层412、暴露出下方的蚀刻停止层410后,基板402可被进一步地运送至光阻层移除处理工具,以进行灰化工艺,自基板402移除光阻层414,如图4C所示。或者,在一于步骤302进行的背沟道蚀刻(BCE)过程中已除去、实质上完全蚀刻掉光阻层414的实施例中,可以省略步骤304的灰化工艺,以节省制造成本。
于步骤306,基板402接着被运送至金属有源层图案化工具,对于有源层408的未受晶体管器件400结构保护的区域(例如暴露出的部分422)进行金属有源层图案化工艺,暴露出下方栅极绝缘层406的区域424,如图4D所示。在有源层408被蚀刻之后,暴露出下方栅极绝缘层406的区域424,有源层408的边缘430被定义成具有期望的轮廓/图案。不同于在背沟道蚀刻(BCE)工艺之前进行金属有源层蚀刻工艺的常规方法,在沟道426未形成于源极-漏极金属电极层412前,不进行有源层408的蚀刻。藉此,在有源层图案化工艺后被暴露出来的有源层408的边缘430,不会如在常规的制造顺序中所发现的,在背沟道蚀刻(BCE)工艺及/或光阻层移除工艺期间受到攻击性蚀刻剂的等离子体损坏(plasma damage)的攻击。通过在沟道426完全形成于源极-漏极金属电极层412之后(例如在背沟道蚀刻工艺之后)进行有源层蚀刻工艺,可维持对于有源层408的良好控制,从而实质上良好地控制边缘430的情况,而不会使有源层408形成可能使得器件400电性性能下降的损坏。举例而言,器件对于湿度(humidity)的抵抗性提高了约268%。
在一实施例中,有源层蚀刻工艺可为湿蚀刻工艺,通过将基板402浸于其中具有蚀刻溶液的槽(tank)或湿式工作台(wet bench)来进行。在一实施例中,用于对有源层408进行湿蚀刻的化学物质为酸。所用的酸可包括硝酸或硫酸等等,但不限于此。在特定的一实施例中,用于对有源层408进行湿蚀刻的化学物为浓度介于约0.1体积百分比与约5体积百分比之间的含氢氯酸(HCl)的溶液。值得注意的是,有源层图案化工艺也可以通过干蚀刻工艺或任何类型的合适的图案化工艺来进行。
在有源层图案化工艺之后,形成于基板402上的器件400可于步骤308进行更进一步地处理,形成钝化层等等,以便使器件制造工艺完整。值得注意的是,额外的工艺步骤可以根据需求于任一步骤(例如步骤302至步骤308)中进行,以便于在基板上形成器件结构。举例而言,额外的工艺步骤如额外的退火、蚀刻、沉积及清洗,可以依照所需来进行,以帮助达成工艺300中任何步骤间所需的运送条件。
因此,在此所述的方法通过在对于薄膜晶体管器件进行背沟道蚀刻(BCE)工艺后再进行有源层图案化工艺,有利地改善电子元件的电性性能、薄膜层轮廓及稳定性。由于有源层的侧壁不再暴露于用以蚀刻金属电极层的蚀刻剂中,以这样的方式,对于有源层侧壁轮廓的控制能获得改善,具有更好的基板到基板的可再现性(repeatability),且损坏率降低。
综上所述,虽然本发明已以实施例揭露如上,然而,在不背离本发明基本范围的情况下,可以设计本发明的其他实施例和进一步实施例,本发明的保护范围由后附的权利要求所界定。
Claims (18)
1.一种制造薄膜晶体管器件的方法,包括:
提供基板,所述基板具有有源层形成于其上,源极-漏极金属电极层设置在所述有源层之上,其中所述有源层为金属氧化物层;
进行背沟道蚀刻工艺,以在所述源极-漏极金属电极层中形成沟道;
进行灰化工艺,以移除形成在所述源极-漏极金属电极层上的图案化的光阻层;以及
在所述背沟道蚀刻工艺之后,进行有源层图案化工艺,其中用以移除所述图案化的光阻层的所述灰化工艺是在进行所述有源层图案化工艺之前进行。
2.如权利要求1所述的方法,其特征在于,所述基板还包括蚀刻停止层,所述蚀刻停止层设置在所述源极-漏极金属电极层与所述有源层之间。
3.如权利要求2所述的方法,其特征在于,进行所述背沟道蚀刻工艺以便对所述源极-漏极金属电极层进行蚀刻直到暴露出所述蚀刻停止层。
4.如权利要求2所述的方法,其特征在于,所述蚀刻停止层为含硅层、含锌层、含铪层、含钛层或含钽层。
5.如权利要求1所述的方法,其特征在于,所述有源层是由选自由铟镓锌氧化物(InGaZnO)、铟镓锌氮氧化物(InGaZnON)、氧化锌(ZnO)、氮氧化锌(ZnON)、锌锡氧化物(ZnSnO)、镉锡氧化物(CdSnO)、镓锡氧化物(GaSnO)、钛锡氧化物(TiSnO)、铜铝氧化物(CuAlO)、锶铜氧化物(SrCuO)、镧铜硫氧化物(LaCuOS)、氮化镓(GaN)、铟镓氮化物(InGaN)、铝镓氮化物(AlGaN)及铟镓铝氮化物(InGaAlN)所组成的群组的材料制造而成。
6.如权利要求1所述的方法,其特征在于,所述背沟道蚀刻工艺为干蚀刻工艺。
7.如权利要求6所述的方法,其特征在于,所述干蚀刻工艺还包括:
将所述源极-漏极金属电极层暴露于含氯气体,其中所述源极-漏极金属电极层为含铬金属。
8.如权利要求6所述的方法,其特征在于,所述干蚀刻工艺还包括:
将所述源极-漏极金属电极层暴露于含氟气体,其中所述源极-漏极金属电极层为含钼金属。
9.如权利要求1所述的方法,其特征在于,所述背沟道蚀刻工艺为湿蚀刻工艺。
10.如权利要求9所述的方法,其特征在于,所述湿蚀刻工艺还包括:
将所述源极-漏极金属电极层暴露于过氧化氢(H2O2)或过氧化氢/氢氧化钾(H2O2/KOH)。
11.如权利要求10所述的方法,其特征在于,所述源极-漏极金属电极层为含钼金属。
12.如权利要求1所述的方法,其特征在于,所述有源层图案化工艺为干蚀刻工艺。
13.如权利要求1所述的方法,其特征在于,所述有源层图案化工艺为使用酸性溶液的湿蚀刻工艺。
14.如权利要求13所述的方法,其特征在于,所述酸性溶液包括硝酸或硫酸。
15.如权利要求1所述的方法,其特征在于,所述有源层图案化工艺为使用含氢氯酸的溶液的湿蚀刻工艺。
16.如权利要求15所述的方法,其特征在于,所述含氢氯酸的溶液具有介于0.1体积百分比至5体积百分比之间的浓度。
17.如权利要求1所述的方法,其特征在于,所述源极-漏极金属电极是由选自由铜、金、银、铝、钨、钼、铬、钽、钛、其合金或其组合所组成的群组的材料制造而成。
18.如权利要求1所述的方法,其特征在于,进行所述灰化工艺以移除所述图案化的光阻层是在于所述源极-漏极金属电极层中形成所述沟道之后进行。
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US8455310B2 (en) | 2013-06-04 |
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TW201306269A (zh) | 2013-02-01 |
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WO2013009505A2 (en) | 2013-01-17 |
JP6078063B2 (ja) | 2017-02-08 |
TWI431781B (zh) | 2014-03-21 |
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WO2013009505A3 (en) | 2013-03-07 |
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