TWI565080B - 薄膜電晶體的製作方法 - Google Patents

薄膜電晶體的製作方法 Download PDF

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TWI565080B
TWI565080B TW103141854A TW103141854A TWI565080B TW I565080 B TWI565080 B TW I565080B TW 103141854 A TW103141854 A TW 103141854A TW 103141854 A TW103141854 A TW 103141854A TW I565080 B TWI565080 B TW I565080B
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thin film
film transistor
fabricating
plasma
substrate
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TW201622156A (zh
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張鼎張
陳華茂
蔡明諺
謝天宇
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國立中山大學
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Description

薄膜電晶體的製作方法
本發明係關於一薄膜電晶體的製作方法；特別是關於一種具有透明導電膜之薄膜電晶體的製作方法。
由於半導體技術的進步，逐漸發展出薄膜電晶體(thin film transistor，TFT)元件作為電子開關，並廣泛地使用於各式電子器材內，以平面顯示器為例，可利用非晶矽/多晶矽(amorphous/poly silicon)半導體為薄膜電晶體之主動層(active layer)，以便利用薄膜電晶體作為控制畫素之電荷儲存電容(storage capacitor)的充放電開關元件。
習知薄膜電晶體的電極通常為金屬材料製成，其一實施例可參酌中華民國公告第I431781號「製造薄膜電晶體元件的方法」專利案，其中，習知薄膜電晶體中的金屬材料並非透明材質，為了發展全透明顯示器，習知薄膜電晶體的金屬電極必須改為透明導電膜。
惟，將透明導電膜應用於顯示器的薄膜電晶體中，將會面臨透明導電膜與其他材料層間的接觸電阻過大的問題，導致電晶體的導通電流(ION)下降，且會發生電流擁擠效應(Current Crowding Effect，如第1圖之區域D1所示)。
有鑑於此，上述先前技術在實際使用時確有不便之處，亟需進一步改良，以提升其實用性。
本發明係提供一種薄膜電晶體的製作方法，可降低薄膜電晶 體之透明導電膜與其他材料層間的接觸電阻。
本發明揭示一種薄膜電晶體的製作方法，其步驟包含：於一基板上形成一電晶體雛型，該電晶體雛型具有二透明電極，用以作為一薄膜電晶體之一源極及一汲極；及將該電晶體雛型的二透明電極裸露於充滿電漿的環境中，使電漿對該電晶體雛型的二透明電極進行表面處理，用以製成該薄膜電晶體，其中該電漿係為氫電漿。
所述透明電極可由銦錫氧化物製成。
所述氫電漿的偏壓功率可為200至400瓦。
所述氫電漿的操作壓力可為15mTorr。
所述氫電漿的處理時間可為20至100秒。
所述氫電漿的電漿功率可為500至700瓦。
所述氫電漿的電漿流量可為20至30sccm。
所述電晶體雛型可於該基板上可形成一閘極，可於該閘極及該基板上形成一介電層，可於該介電層上形成該二透明電極。
所述電晶體雛型的二透明電極進行表面處理後，於該二透明電極之間可形成一主動層區域，用以製成該薄膜電晶體。
所述電晶體雛型可於該基板上形成該二透明電極。
所述電晶體雛型的二透明電極進行表面處理後，可於該二透明電極之間形成一主動層區域，可於該透明電極、該主動層區域及該基板上形成一介電層，可於該介電層上形成一閘極，用以製成該薄膜電晶體。
所述閘極可由銦錫氧化物製成。
所述介電層可由二氧化矽製成。
所述主動層區域可由氧化鋅製成。
所述薄膜電晶體的結構可為共面或反共面結構。
所述基板可為一可撓式基板、一玻璃基板、一金屬基板或一 塑膠基板。
上揭薄膜電晶體的製作方法，可於該基板上形成該電晶體雛型，該電晶體雛型具有二透明電極，再將該電晶體雛型的二透明電極裸露於充滿電漿的環境中，使電漿對該電晶體雛型的二透明電極進行表面處理，再以經電漿表面處理後的電晶體雛型製成該薄膜電晶體。藉此，可使該透明電極表面金屬化，且更偏向導體特性，降低該透明電極的接觸電阻，可以達成「增加薄膜電晶體的導通電流」及「避免發生電流擁擠現象」等功效。
〔本發明〕
1‧‧‧電晶體雛型
11‧‧‧閘極
12‧‧‧介電層
13a,13b‧‧‧透明電極
14‧‧‧主動層區域
2‧‧‧電晶體雛型
21a,21b‧‧‧透明電極
22‧‧‧主動層區域
23‧‧‧介電層
24‧‧‧閘極
B,B’‧‧‧基板
C1~C6‧‧‧曲線
D2‧‧‧區域
P‧‧‧電漿
S1‧‧‧雛型製備步驟
S2‧‧‧電漿處理步驟
S3‧‧‧成品完備步驟
〔習知〕
D1‧‧‧區域
第1圖：係習知薄膜電晶體發生電流擁擠效應的汲極電性曲線圖。
第2圖：係本發明薄膜電晶體的製作方法實施例之流程示意圖。
第3圖：係本發明薄膜電晶體的製作方法第一實施例的製作過程示意圖。
第4圖：係本發明薄膜電晶體的製作方法第一實施例的汲極電性曲線圖。
第5圖：係薄膜電晶體經過電漿處理與未經電漿處理的閘極電性曲線圖。
第6圖：係本發明薄膜電晶體的製作方法第二實施例的製作過程示意圖。
為讓本發明之上述及其他目的、特徵及優點能更明顯易懂，下文特舉本發明之較佳實施例，並配合所附圖式，作詳細說明如下：本發明全文所述之「電漿」(plasma)，係指一種以自由電子及帶電離子為主要成分的物質狀態，此物質狀態有別於固、液、氣三態， 又稱電漿態，係本發明所屬技術領域中具有通常知識者可以理解。
本發明全文所述之「掀離製程」(lift-off process)，係指依序利用塗佈光阻(coating photoresist)、上光罩(masking)、曝光(exposure)、顯影(development)、蒸鍍金屬(depositing metal)及去光阻(removing photoresist)等技術，留下欲作出的金屬(電路)圖案，通常用於蝕刻(etching)技術難以製程的圖案，係本發明所屬技術領域中具有通常知識者可以理解，作為實施例製程方法，但不受此限。
請參閱第2圖所示，其係本發明薄膜電晶體的製作方法實施例之流程示意圖。其中，該製作方法實施例包含一雛型製備步驟S1、一電漿處理步驟S2及一成品完備步驟S3。其中，本發明薄膜電晶體的製作方法實施例所製作的電晶體結構可為共面(coplanar)或反共面(inverted coplanar)等結構，惟不以此為限。請一併參閱第3圖所示，其係本發明薄膜電晶體的製作方法第一實施例的製作過程示意圖。在此實施例中，該薄膜電晶體係以反共面結構作為實施態樣，說明如下。
該雛型製備步驟S1可於一基板(Substrate)S上形成一電晶體雛型(transistor prototype)1，該電晶體雛型1具有二透明電極13a、13b，用以作為一薄膜電晶體之一源極(Source)及一汲極(Drain)。在此實施例中，該基板B可為可撓式(flexible)、玻璃(glass)、金屬(metal)或塑膠(plastic)等形態的基板，用以形成該電晶體雛型1，該電晶體雛型1的製作方法舉例說明如下，該基板B上可先沉積形成一透明導電膜，如：由銦錫氧化物(ITO)、鋁鋅氧化物(AZO)、銦鋅氧化物(IZO)或者摻鎵氧化鋅(GZO)等透明導電材製成，用以定義出一閘極(Gate)11；接著，於該閘極11及基板B上沉積形成一介電層(Gate Insulator)12，如：由二氧化矽(SiO2)或氮化矽(Si3N4)等絕緣材製成；接著，於該介電層12上沉積形成另一透明導電膜，用以蝕刻(etching)形成該二透明電極13a、13b，作為該源極與 汲極。
請再參閱第2、3圖所示，該電漿處理步驟S2係將該電晶體雛型1的二透明電極13a、13b裸露於充滿電漿(plasma)P的環境中，使電漿P對該電晶體雛型1的透明電極13a、13b進行表面處理，用以製成一反共面結構的薄膜電晶體。在此實施例中，可先將該電晶體雛型1置於一反應腔室(圖未繪示)中，於該反應腔室中通入電漿，如：氫(H)電漿等，電漿流量可為20至30sccm(standard cubic centimeter per minute，在標準狀態〔溫度273K，壓力760torr〕下，每分鐘有1立方公分的氣體流量)，電漿功率可為500至700瓦(W)，電漿處理時間可為20至100秒，偏壓功率可為200至400瓦，操作壓力可為10至30mTorr；其中，當該二透明電極13a、13b中的銦錫氧化物接觸電漿P中的氫時，由於氫會與銦錫氧化物中的錫(Sn)爭奪氧鍵(O bond)而形成氫氧鍵(OH bond)，且會釋放電子，如下所示：H(ads)+Sn2++O2-(in a-IGZO)→H+(in lattice)+Sn2++O2-+e-→OH-(in a-IGZO)+Sn2++e-，使該二透明電極13a、13b表面金屬化，而更偏向導體特性，可改善該二透明電極13a、13b與其他材料層之間的接觸電阻。
請再參閱第2、3圖所示，該成品完備步驟S3係以經電漿P表面處理後的電晶體雛型1製成該薄膜電晶體。在此實施例中，該電晶體雛型1經電漿P表面處理後，可於該電晶體雛型1上的二透明電極13a、13b之間續沉積形成一主動層材料，如：氧化鋅(ZnO)等可作為主動層之材料，接著，利用掀離製程(lift-off process)定義出一主動層區域14，如此，即可完成一反共面結構的薄膜電晶體。
其中，該主動層區域14與二透明電極13a、13b間的接面不易產生蕭基接觸(schottky contact)，且其接面特性接近歐姆接觸(ohmic contact)，由於該主動層區域14與二透明電極13a、13b間的接觸電阻降低， 可增加薄膜電晶體的導通電流，且可避免發生電流擁擠現象，其係所屬技術領域中具有通常知識者可以理解。
請參閱第4圖所示，其係本發明薄膜電晶體的製作方法第一實施例的汲極電性曲線圖。其中，本發明第一實施例製作的薄膜電晶體經過電漿處理後，其汲極電壓對汲極電流的不同特性曲線C1~C4涇渭分明(如第4圖之區域D2所示)，相較於習知薄膜電晶體發生電流擁擠效應的汲極電性曲線(如第1圖之區域D1所示)，證明本發明第一實施例製作的薄膜電晶體確實可避免發生電流擁擠現象。
請參閱第5圖所示，其係薄膜電晶體經過電漿處理與未經電漿處理的閘極電性曲線圖。其中，薄膜電晶體經過電漿處理的閘極電性曲線為C5，而薄膜電晶體未經電漿處理的閘極電性曲線為C6，相較曲線C5與C6可知，本發明第一實施例製作的薄膜電晶體經過電漿處理後，閘極電流明顯提高，證明本發明第一實施例製作的薄膜電晶體確實可以增加薄膜電晶體的導通電流。
請參閱第6圖所示，其係本發明薄膜電晶體的製作方法第二實施例的製作過程示意圖。在此實施例中，該薄膜電晶體係以共面結構作為實施態樣說明，請一併參閱第2圖所示。
該雛型製備步驟S1可於一基板B’上形成一電晶體雛型(transistor prototype)2，該電晶體雛型2具有二透明電極21a、21b，作為用以作為一薄膜電晶體之一源極及一汲極。在此實施例中，該基板B’與第一實施例的基板B型態大致相同，用以形成該電晶體雛型2，該電晶體雛型2的製作方法，說明如下，可於該基板B’上先沉積形成一透明導電膜，如：銦錫氧化物(ITO)等透明導電材，用以蝕刻(etching)形成該二透明電極21a、21b，作為該源極及汲極。
請再參閱第2、6圖所示，該電漿處理步驟S2係將該電晶體 雛型2的二透明電極21a、21b裸露於充滿電漿P的環境中，使電漿P對該電晶體雛型2的透明電極21a、21b進行表面處理，用以製成一共面結構的薄膜電晶體。在此實施例中，可先將該電晶體雛型2置於一反應腔室(圖未繪示)中，於該反應腔室中通入電漿，如：氫(H)電漿等，其電漿流量、電漿功率、電漿處理時間、偏壓功率、操作壓力與第一實施例大致相同，藉此，可使該二透明電極21a、21b表面金屬化而更偏向導體特性，可改善該二透明電極21a、21b與其他材料層之間的接觸電阻。
請再參閱第2、6圖所示，該成品完備步驟S3係以經電漿P表面處理後的電晶體雛型2製成該薄膜電晶體。在此實施例中，該電晶體雛型1經電漿P表面處理後，可於該電晶體雛型1上的二透明電極21a、21b之間續沉積形成一主動層材料，如：氧化鋅(ZnO)，接著，利用掀離製程定義出一主動層區域22；接著，於該透明電極21a、21b、主動層區域22及基板B’上沉積形成一介電層(Gate Insulator)23，如：二氧化矽(SiO2)等絕緣材；接著，於該介電層23上沉積形成另一透明導電膜，用以定義出一閘極(Gate)24，如此，即可完成一共面結構的薄膜電晶體。
其中，該主動層區域22與二透明電極21a、21b間的接面不易產生蕭基接觸，且其接面特性接近歐姆接觸，由於該主動層區域22與二透明電極21a、21b間的接觸電阻降低，可增加薄膜電晶體的導通電流，且可避免發生電流擁擠現象，依此類推，本發明薄膜電晶體的製作方法亦可適用於製作其他結構的薄膜電晶體，其係所屬技術領域中具有通常知識者可以理解。
藉由前揭之技術手段，本發明薄膜電晶體的製作方法上述實施例的主要特點列舉如下：首先，可於該基板上形成該電晶體雛型，該電晶體雛型具有二透明電極，用以作為該薄膜電晶體之源極及汲極；接著，將該電晶體雛型的二透明電極裸露於充滿電漿的環境中，使電漿對該電晶 體雛型的二透明電極進行表面處理；之後，以經電漿表面處理後的電晶體雛型製成該薄膜電晶體。
因此，本案上述實施例可藉由電漿對該透明電極進行表面處理，如：採用氫電漿，電漿流量可為20至30sccm，電漿功率可為500至700W，電漿處理時間可為20至100秒，偏壓功率可為200至400瓦，操作壓力可為15mTorr，使該透明電極表面金屬化，且更偏向導體特性，降低該透明電極的接觸電阻，可以達成「增加薄膜電晶體的導通電流」及「避免發生電流擁擠現象」等功效。
其中，偏壓功率過小則表面處理不具效果，偏壓功率過大則對電極表面造成轟擊，當偏壓功率介於200至400瓦之間，才可有效地改善該透明電極的接觸電阻。因此，本案上述實施例確實可改善習知技術「無法有效降低薄膜電晶體的透明電極接觸電阻過大」問題。
雖然本發明已利用上述較佳實施例揭示，然其並非用以限定本發明，任何熟習此技藝者在不脫離本發明之精神和範圍之內，相對上述實施例進行各種更動與修改仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
S1‧‧‧雛型製備步驟
S2‧‧‧電漿處理步驟
S3‧‧‧成品完備步驟

Claims (16)

  1. 一種薄膜電晶體的製作方法，其步驟包含：於一基板上形成一電晶體雛型，該電晶體雛型具有二透明電極，用以作為一薄膜電晶體之一源極及一汲極；及將該電晶體雛型的二透明電極裸露於充滿電漿的環境中，使電漿對該電晶體雛型的二透明電極進行表面處理，用以製成該薄膜電晶體，其中該電漿係為氫電漿。
  2. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該透明電極由銦錫氧化物製成。
  3. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該氫電漿的偏壓功率為200至400瓦。
  4. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該氫電漿的操作壓力為15mTorr。
  5. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該氫電漿的處理時間為20至100秒。
  6. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該氫電漿的電漿功率為500至700瓦。
  7. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該氫電漿的電漿流量為20至30sccm。
  8. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該電晶體雛型於該基板上形成一閘極，於該閘極及該基板上形成一介電層，於該介電層上形成該二透明電極。
  9. 根據申請專利範圍第8項所述之薄膜電晶體的製作方法，其中該電晶體雛型的二透明電極進行表面處理後，於該二透明電極之間形成一主動層區域，用以製成該薄膜電晶體。
  10. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該電晶體雛型於該基板上形成該二透明電極。
  11. 根據申請專利範圍第10項所述之薄膜電晶體的製作方法，其中該電晶體雛型的二透明電極進行表面處理後，於該二透明電極之間形成一主動層區域，於該透明電極、該主動層區域及該基板上形成一介電層，於該介電層上形成一閘極，用以製成該薄膜電晶體。
  12. 根據申請專利範圍第8或11項所述之薄膜電晶體的製作方法，其中該閘極由銦錫氧化物製成。
  13. 根據申請專利範圍第8或11項所述之薄膜電晶體的製作方法，其中該介電層由二氧化矽製成。
  14. 根據申請專利範圍第9或11項所述之薄膜電晶體的製作方法，其中該主動層區域由氧化鋅製成。
  15. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該薄膜電晶體的結構為共面或反共面結構。
  16. 根據申請專利範圍第1項所述之薄膜電晶體的製作方法，其中該基板為一可撓式基板、一玻璃基板、一金屬基板或一塑膠基板。
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