CN103545286A - 线路基板、半导体封装结构及线路基板制作工艺 - Google Patents

线路基板、半导体封装结构及线路基板制作工艺 Download PDF

Info

Publication number
CN103545286A
CN103545286A CN201310484756.3A CN201310484756A CN103545286A CN 103545286 A CN103545286 A CN 103545286A CN 201310484756 A CN201310484756 A CN 201310484756A CN 103545286 A CN103545286 A CN 103545286A
Authority
CN
China
Prior art keywords
plating
conductor layer
base plate
junction section
those
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310484756.3A
Other languages
English (en)
Other versions
CN103545286B (zh
Inventor
宫振越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Publication of CN103545286A publication Critical patent/CN103545286A/zh
Application granted granted Critical
Publication of CN103545286B publication Critical patent/CN103545286B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32238—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Structure Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明公开一种线路基板、半导体封装结构及线路基板制作工艺。线路基板包括一线路叠构、一图案化导体层、一介电层及多个增厚导体层。线路叠构具有一表面。图案化导体层配置在表面上并具有多个走线。各走线具有一接合区段。介电层配置在表面上且覆盖图案化导体层。介电层具有多个接合开口。各接合开口暴露出对应的接合区段。各增厚导体层配置在对应的接合区段上。一种采用上述线路基板的半导体封装结构及一种线路基板制作工艺也提供于此。

Description

线路基板、半导体封装结构及线路基板制作工艺
技术领域
本发明涉及应用于半导体封装领域的线路基板、半导体封装结构及线路基板制作工艺。 
背景技术
在半导体封装技术领域中，芯片载体（chip carrier）是一种用以将集成电路芯片（IC chip）连接至下一层级的电子元件，例如主机板或模块板等。具有高布线密度的线路基板（circuit board）经常作为高接点数的芯片载体。线路基板主要由多个图案化导体层（patterned conductive layer）及多个介电层（dielectric layer）交替叠合而成，而两图案化导体层之间可通过导体孔（conductive via）来彼此电连接。 
倒装接合（flip-chip bonding）是一种应用于高接点数（high pin count）的芯片封装技术，其通常采用线路基板作为芯片载体，并通过多个以面阵列方式排列的导电凸块（conductive bump），以将芯片电连接至线路基板的多个接垫。为了减少接垫之间的间距来提高接垫的密度，一种现有的作法是利用线路基板上的防焊层的大型开口来完全暴露出线路基板上的芯片接合区，并通过线路基板上的走线（trace）位在芯片接合区内的一接合区段（bonding segment）来焊接至对应的导体凸块。 
承上所述，当两个相邻的接合区段之间存在另一条走线的一过渡区段（transitional segment）时，为了减少这两相邻的接合区段之间的距离，需窄化上述的过渡区段。然而，为了确保过渡区段能提供电性传输的功能，过渡区段的窄化有其限制，这将不利于相邻二接合区段的间距的减少。此外，接合区段的接合面积取决于走线的宽度及厚度。为了确保接合区段具有足够的接合面积，走线的窄化也有其限制，这也不利于相邻二接合区段的间距的减少。 
发明内容
本发明的目的在于提供一种线路基板，应用于半导体封装技术。 
本发明的再一目的在于提供一种半导体封装结构，以应用于封装半导体集成电路芯片。 
本发明的又一目的在于提供一种线路基板制作工艺，用以制作出应用于半导体封装领域的线路基板。 
为达上述目的，本发明的一种线路基板，其包括一线路叠构、一图案化导体层、一介电层及多个增厚导体层。线路叠构具有一表面。图案化导体层配置在表面上并具有多个走线。各走线具有一接合区段。介电层配置在表面上且覆盖图案化导体层。介电层具有多个接合开口，各接合开口暴露出对应的接合区段。各增厚导体层配置在对应的接合区段上。 
本发明的一种半导体封装结构，包括一线路基板及一芯片。线路基板包括一线路叠构、一图案化导体层、一介电层及多个增厚导体层。线路叠构具有一表面。图案化导体层配置在表面上并具有多个走线。各走线具有一接合区段。介电层配置在表面上且覆盖图案化导体层。介电层具有多个接合开口，各接合开口暴露出对应的接合区段。各增厚导体层配置在对应的接合区段上。芯片连接这些增厚导体层。 
本发明的一种线路基板制作工艺，包括下列步骤。提供一线路叠构及一图案化导体层，其中线路叠构具有一表面，图案化导体层配置在表面上且具有多个走线，且各走线具有一接合区段及一电镀区段。形成一介电层覆盖表面及图案化导体层，其中介电层具有多个接合开口及多个电镀开口，各接合开口暴露出对应的接合区段，且各电镀开口暴露出对应的电镀区段。形成一电镀籽晶层覆盖表面、这些接合区段、这些电镀区段及介电层。形成一掩模覆盖电镀籽晶层，其中掩模具有多个掩模开口，且各掩模开口暴露出电镀籽晶层在对应的接合区段上的一部分。以掩模为蚀刻掩模蚀刻电镀籽晶层，以移除电镀籽晶层在这些接合区段上的这些部分而暴露出这些接合区段。在蚀刻电镀籽晶层以后，以掩模为电镀掩模并经由电镀籽晶层及这些走线，在各接合区段上电镀一增厚导体层。在电镀这些增厚导体层以后，移除掩模及电镀籽晶层。 
基于上述，本发明通过在接合区段上形成增厚导体层，以增加接合区段的宽度及高度，因而增加接合面积。另外，在本发明的线路基板制作工艺中， 利用介电层的电镀开口暴露出走线的电镀区段，以由此作为电流路径在走线的接合区段上电镀增厚导体层。 
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。 
附图说明
图1为本发明的一实施例的一种线路基板的俯视图； 
图2为图1的线路基板的X部位的放大图； 
图3A为图2的局部的线路基板沿线3A-3A的剖视图； 
图3B为图2的局部的线路基板沿线3B-3B的剖视图； 
图3C为图2的局部的线路基板沿线3C-3C的剖视图； 
图4A为图2的局部的线路基板的图案化导体层的走线的局部的立体图； 
图4B为图2的局部的线路基板的图案化导体层的走线的局部及增厚导体层的立体图； 
图5为本发明的一实施例的一种半导体封装结构的俯视图； 
图6为图5的半导体封装结构沿线6-6的剖视图； 
图7为图5的线路基板的Y部位的放大图； 
图8A为图7的局部的线路基板沿线8A-8A的剖视图； 
图8B为图7的局部的线路基板沿线8B-8B的剖视图； 
图8C为图7的局部的线路基板沿线8C-8C的剖视图； 
图9A至图9G为本发明的另一实施例的一种线路基板制作工艺的局部俯视图； 
图10A至图10G分别为图9A至图9G的线路基板沿着线I-I的上半部剖视图； 
图11A至图11G分别为图9A至图9G的线路基板沿着线II-II的上半部剖视图。 
符号说明 
10：半导体封装结构 
12：芯片 
14：导电凸块 
14a：焊料 
16：底胶 
18：导电球 
100：线路基板 
110：线路叠构 
110a、110b、202a：表面 
120、180、204：图案化导体层 
122、206：走线 
122a、206a：接合区段 
122a-1：顶面 
122a-2：侧面 
122b、206b：电镀区段 
130、190、208：介电层 
132a、208a：接合开口 
132b、208b：电镀开口 
140、214：增厚导体层 
182：接垫 
202：线路叠构 
210：电镀籽晶层 
212：掩模 
212a：掩模开口 
B：芯片接合区 
P：芯片投影区 
X、Y：部位 
具体实施方式
图1为本发明的一实施例的一种线路基板的俯视图，图2为图1的线路基板的X部位的放大图，图3A为图2的局部的线路基板沿线3A-3A的剖视图，图3B为图2的局部的线路基板沿线3B-3B的剖视图，而图3C为图2的局部的线路基板沿线3C-3C的剖视图。请参考图1、图2及图3A至图3C，本实施例的线路基板100包括一线路叠构110。线路叠构110具有一表面 110a。在本实施例中，线路叠构110由多个图案化导体层及一或多个介电层交替叠合而成，而这些图案化导体层之间可通过这些导体孔而彼此电连接。然而，本发明不以此为限。在其他未绘示实施例中，线路叠构110也可由其他数量的图案化导体层及介电层交替叠合而成。在另一未绘示实施例中，线路叠构110也可仅由单一介电层所构成。 
请再参考图1、图2及图3A至图3C，本实施例的线路基板100更包括一图案化导体层120、一介电层130及多个增厚导体层140。图案化导体层120配置在表面110a上并具有多个走线122。各走线122具有一接合区段122a。介电层130（例如防焊层）配置在表面110a上且覆盖图案化导体层120，且介电层130具有多个接合开口132a，各接合开口132a暴露出对应的接合区段122a。各增厚导体层140配置在对应的接合区段122a上。 
值得注意的是，在一般已知的利用走线配置接合区段的技术中，走线的接合区段仅为走线的一小线段，故已知的接合区段的宽度及厚度与构成此已知的接合区段的走线的宽度及厚度分别是相同的。然而，在本发明的实施例中，由于走线122的接合区段122a上配置有增厚导体层140，因此接合区段122a及增厚导体层140的宽度总和将大于构成接合区段122a的走线122的宽度，且接合区段122a及增厚导体层140的厚度总和将大于构成接合区段122a的走线122的厚度。因此，在本发明中，在接合区段上形成增厚导体层，以增加接合区段的宽度及高度，因而增加接合面积。 
图4A为图2的局部的线路基板的图案化导体层的走线的局部的立体图，而图4B为图2的局部的线路基板的图案化导体层的走线的局部及增厚导体层的立体图。请参考图3A、图3B、图4A及图4B，各接合区段122a具有远离表面110a的一顶面122a-1及分别从顶面122a-1两侧延伸至表面110a的两侧面122a-2，且各增厚导体层140配置在对应的接合区段122a的顶面122a-1及这些侧面122a-2上。 
请再参考图1、图2、图3B及图3C，各走线122具有一电镀区段122b，介电层具有多个电镀开口132b，且各电镀开口132b暴露出对应的电镀区段122b。此外，线路叠构110具有一芯片接合区B，且这些接合开口132a及这些电镀开口132b位于芯片接合区B内。另外，线路叠构110更具有一芯片投影区P，而这些接合开口132a位于芯片接合区B内。在另一未绘示的实施例中，当相邻的走线122之间的间距缩小时，上述的多个电镀开口132b 可以一较大的电镀开口取代。换言之，此较大电镀开口同时暴露出多条走线122以及对应的多个电镀区段122b。 
值得注意的是，这些电镀区段122b的用途在下文所介绍的线路基板制作工艺的实施例进行更详细地说明。 
请再参考图1及图3A至图3C，线路基板100还包括另一图案化导体层180及另一介电层190，且线路叠构110还包括另一表面110b。图案化导体层180配置在表面110b上，并具有多个接垫182。介电层190（例如防焊层）配置在表面110a上且覆盖图案化导体层180，但暴露出图案化导体层180的多个接垫182。因此，图案化导体层120经由线路叠构110电连接至图案化导体层180，并经由这些接垫182电连接至下一层级的电子装置（未绘示）。 
图5为本发明的一实施例的一种半导体封装结构的俯视图，而图6为图5的半导体封装结构沿线6-6的剖视图。请参考图5及图6，本实施例的半导体封装结构10包含一芯片12及上述实施例的线路基板100，其中芯片12以倒装接合的方式连接至线路基板100。 
图7为图5的线路基板的Y部位的放大图，图8A为图7的局部的线路基板沿线8A-8A的剖视图，图8B为图7的局部的线路基板沿线8B-8B的剖视图，而图8C为图7的局部的线路基板沿线8C-8C的剖视图。请参考图7及图8A至图8C，在本实施例中，半导体封装结构10具有多个导电凸块14，其配置于芯片12与线路基板100之间，以将芯片12连接至这些增厚导体层140。在本实施例中，通过焊料14a将各导电凸块14连接至对应的增厚导体层140。 
请再参考图7及图8A至图8C，半导体封装结构10更包括一底胶16，其配置于芯片12及线路基板100之间，并填入这些电镀开口132b以覆盖这些电镀区段122b，因而达到绝缘包覆这些电镀区段122b的目的。在本实施例中，底胶160的分布范围在芯片接合区B（如图1所绘示），其边界略大于芯片12的边界。此外，在本实施例中，半导体封装结构10更包括多个导电球18，其分别连接至这些接垫182，以连接至下一层级的电子装置，例如主机板或模块板等。 
图9A至图9G为本发明的另一实施例的一种线路基板制作工艺的局部俯视图，其类似于图1的线路基板的X部位的放大（即图2），图10A至图10G分别为图9A至图9G的线路基板沿着线I-I的上半部剖视图，而图11A 至图11G分别为图9A至图9G的线路基板沿着线II-II的上半部剖视图。在本实施例中，仅以线路基板的上半部进行说明。请参考图9A、10A及图11A，首先，提供一线路叠构202及一图案化导体层204，其中线路叠构202具有一表面202a，图案化导体层204配置在表面202a上且具有多个走线206，且各走线206具有一接合区段206a及一电镀区段206b。 
接着，请参考图9B、10B及图11B，形成一介电层208（例如防焊层）覆盖表面202a及图案化导体层204，其中介电层208具有多个接合开口208a及多个电镀开口208b，各接合开口208a暴露出对应的接合区段206a，且各电镀开口208b暴露出对应的电镀区段206b。在本实施例中，线路叠构202具有一芯片接合区B，且这些接合开口208a及这些电镀开口208b位于芯片接合区B内。在另一未绘示的实施例中，当相邻的走线206之间的间距缩小时，上述的多个电镀开口208b可以一较大的电镀开口取代。换言之，此较大电镀开口同时暴露出多条走线206以及对应的多个电镀区段206b。 
接着，请参考图9C、10C及图11C，形成一电镀籽晶层210覆盖表面202a、这些接合区段206a、这些电镀区段206b及介电层208。接着，请参考图9D、10D及图11D，形成一掩模212覆盖电镀籽晶层210，其中掩模212具有多个掩模开口212a，且各掩模开口212a暴露出电镀籽晶层210在对应的接合区段206a上的一部分。接着，请参考图9E、10E及图11E，以掩模212为蚀刻掩模蚀刻电镀籽晶层210，以移除电镀籽晶层210在这些接合区段206a上的这些部分而暴露出这些接合区段206a。 
接着，请参考图9F、图10F及图11F，在蚀刻电镀籽晶层210以后，以掩模212为电镀掩模并经由电镀籽晶层210及这些走线206，在各接合区段206a上电镀一增厚导体层214。类似于图4A的接合区段122a，各接合区段206a具有远离表面202a的一顶面206a-1及分别从顶面206a-1的两侧延伸至表面202a的两侧面206a-2，而对应的增厚导体层214则配置在接合区段206a的顶面206a-1及这两侧面206a-2上。 
最后，请参考图9G、图10G及图11G，在电镀这些增厚导体层214以后，移除掩模212及电镀籽晶层210。 
综上所述，本发明通过介电层（例如防焊层）覆盖配置在线路叠构上的图案化导体层，但暴露出图案化导体层的走线的接合区段，使得相邻的接合区段的间距可以减少，特别是相邻的接合区段之间存在其他走线，且相邻的 接合区段彼此不易桥接（Bridging）。此外，本发明在接合区段上形成增厚导体层，以增加接合区段的宽度及高度，因而增加接合面积。 
除此之外，在本发明的线路基板制作工艺中，利用介电层的电镀开口暴露出走线的电镀区段，以由此作为电流路径在走线的接合区段上电镀增厚导体层。同时，更可通过底胶来填充电镀开口以包覆走线的电镀区段，以达到绝缘包覆电镀区段的目的。 
虽然已结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。 

Claims (20)

1.一种线路基板，包括：
线路叠构，具有一表面；
图案化导体层，配置在该表面上并具有多个走线，各该走线具有一接合区段；
介电层，配置在该表面上且覆盖该图案化导体层，且该介电层具有多个接合开口，各该接合开口暴露出对应的该接合区段；以及
多个增厚导体层，各该增厚导体层配置在对应的该接合区段上。
2.如权利要求1所述的半导体封装结构，其中各该接合区段具有远离该表面的一顶面及分别从该顶面两侧延伸至该表面的两侧面，且各该增厚导体层配置在对应的该接合区段的该顶面及该些侧面上。
3.如权利要求1所述的线路基板，其中各该走线具有一电镀区段，该介电层具有多个电镀开口，且各该电镀开口暴露出对应的该电镀区段。
4.如权利要求3所述的线路基板，其中该线路基板适于通过一底胶与一芯片连接，而该底胶适于配置于该芯片与该线路基板之间，并填入该些电镀开口以覆盖该些电镀区段。
5.如权利要求3所述的线路基板，其中该线路叠构具有一芯片接合区，且该些接合开口及该些电镀开口位于该芯片接合区内。
6.如权利要求1所述的线路基板，其中该介电层为一防焊层。
7.如权利要求1所述的线路基板，其中各该接合区段与对应的该增厚导体层的宽度总和大于对应的该走线的宽度，且各该接合区段与对应的该增厚导体层的厚度总和大于对应的该走线的厚度。
8.一种半导体封装结构，包括：
线路基板，包括：
线路叠构，具有一表面；
图案化导体层，配置在该表面上并具有多个走线，各该走线具有一接合区段；
介电层，配置在该表面上且覆盖该图案化导体层，且该介电层具有多个接合开口，各该接合开口暴露出对应的该接合区段；以及
多个增厚导体层，各该增厚导体层配置在对应的该接合区段上；以及
芯片，连接该些增厚导体层。
9.如权利要求8所述的半导体封装结构，其中各该接合区段具有远离该表面的一顶面及分别从该顶面两侧延伸至该表面的两侧面，且各该增厚导体层配置在对应的该接合区段的该顶面及该些侧面上。
10.如权利要求8所述的半导体封装结构，其中各该走线具有一电镀区段，该介电层具有多个电镀开口，且各该电镀开口暴露出对应的该电镀区段。
11.如权利要求10所述的半导体封装结构，还包括：
底胶，配置于该芯片与该线路基板之间，并填入该些电镀开口以覆盖该些电镀区段。
12.如权利要求10所述的半导体封装结构，其中该线路叠构具有一芯片接合区，且该些接合开口及该些电镀开口位于该芯片接合区内。
13.如权利要求8所述的半导体封装结构，其中该线路叠构具有一芯片投影区，且该些接合开口位于该芯片投影区内。
14.如权利要求8所述的半导体封装结构，其中该介电层为一防焊层。
15.如权利要求8所述的半导体封装结构，还包括：
多个导电凸块，配置于该芯片与该线路基板之间，以将该芯片连接至该些增厚导体层。
16.一种线路基板制作工艺，包括：
提供一线路叠构及一图案化导体层，其中该线路叠构具有一表面，该图案化导体层配置在该表面上且具有多个走线，且各该走线具有一接合区段及一电镀区段；
形成一介电层覆盖该表面及该图案化导体层，其中该介电层具有多个接合开口及多个电镀开口，各该接合开口暴露出对应的该接合区段，且各该电镀开口暴露出对应的该电镀区段；
形成一电镀籽晶层覆盖该表面、该些接合区段、该些电镀区段及该介电层；
形成一掩模覆盖该电镀籽晶层，其中该掩模具有多个掩模开口，且各该掩模开口暴露出该电镀籽晶层在对应的该接合区段上的一部分；
以该掩模为蚀刻掩模蚀刻该电镀籽晶层，以移除该电镀籽晶层在该些接合区段上的该些部分而暴露出该些接合区段；
在蚀刻该电镀籽晶层以后，以该掩模为电镀掩模并经由该电镀籽晶层及该些走线，在各该接合区段上电镀一增厚导体层；以及
在电镀该些增厚导体层以后，移除该掩模及该电镀籽晶层。
17.如权利要求16所述的线路基板制作工艺，其中各该接合区段具有远离该表面的一顶面及分别从该顶面两侧延伸至该表面的两侧面，且各该增厚导体层配置在对应的该接合区段的该顶面及该些侧面上。
18.如权利要求16所述的线路基板制作工艺，其中该线路叠构具有一芯片接合区，且该些接合开口及该些电镀开口位于该芯片接合区内。
19.如权利要求16所述的线路基板制作工艺，其中该介电层为一防焊层。
20.如权利要求16所述的线路基板制作工艺，其中各该接合区段与对应的该增厚导体层的宽度总和大于对应的该走线的宽度，且各该接合区段与对应的该增厚导体层的厚度总和大于对应的该走线的厚度。
CN201310484756.3A 2013-08-28 2013-10-16 线路基板、半导体封装结构及线路基板制作工艺 Active CN103545286B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW102130846A TWI514530B (zh) 2013-08-28 2013-08-28 線路基板、半導體封裝結構及線路基板製程
TW102130846 2013-08-28

Publications (2)

Publication Number Publication Date
CN103545286A true CN103545286A (zh) 2014-01-29
CN103545286B CN103545286B (zh) 2016-05-11

Family

ID=49968602

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310484756.3A Active CN103545286B (zh) 2013-08-28 2013-10-16 线路基板、半导体封装结构及线路基板制作工艺

Country Status (3)

Country Link
US (2) US10103115B2 (zh)
CN (1) CN103545286B (zh)
TW (1) TWI514530B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104392978A (zh) * 2014-11-04 2015-03-04 上海兆芯集成电路有限公司 线路基板和半导体封装结构
CN106206532A (zh) * 2015-05-29 2016-12-07 三星电机株式会社 封装基板和制造封装基板的方法
CN107808869A (zh) * 2016-09-09 2018-03-16 矽品精密工业股份有限公司 电子封装件及其制法
CN110418510A (zh) * 2019-07-15 2019-11-05 宁波华远电子科技有限公司 一种开放性电镀凸台的制作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI714419B (zh) * 2020-01-06 2020-12-21 力晶積成電子製造股份有限公司 具有隱藏的識別碼的半導體堆疊結構

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535388B1 (en) * 2001-10-04 2003-03-18 Intel Corporation Wirebonded microelectronic packages including heat dissipation devices for heat removal from active surfaces thereof
CN1529545A (zh) * 2003-09-29 2004-09-15 威盛电子股份有限公司 选择性电镀法
US20070182009A1 (en) * 2006-02-09 2007-08-09 Matsushita Electric Industrial Co., Ltd. Wiring board and method for manufacturing the same and semiconductor device and method for manufacturing the same
US7902660B1 (en) * 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US20120322205A1 (en) * 2011-06-16 2012-12-20 Shinko Electric Industries Co., Ltd. Method for manufacturing wiring substrate

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6049122A (en) * 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
JP3420076B2 (ja) * 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
JP3205548B2 (ja) * 1999-10-01 2001-09-04 ソニーケミカル株式会社 多層フレキシブル配線板
TW550800B (en) * 2002-05-27 2003-09-01 Via Tech Inc Integrated circuit package without solder mask and method for the same
TW557536B (en) 2002-05-27 2003-10-11 Via Tech Inc High density integrated circuit packages and method for the same
TW543923U (en) * 2002-10-25 2003-07-21 Via Tech Inc Structure of chip package
US20040099961A1 (en) * 2002-11-25 2004-05-27 Chih-Liang Chu Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same
US6853060B1 (en) * 2003-04-22 2005-02-08 Amkor Technology, Inc. Semiconductor package using a printed circuit board and a method of manufacturing the same
JP3565835B1 (ja) * 2003-04-28 2004-09-15 松下電器産業株式会社 配線基板およびその製造方法ならびに半導体装置およびその製造方法
TW572361U (en) * 2003-06-03 2004-01-11 Via Tech Inc Flip-chip package carrier
CN2710308Y (zh) * 2003-06-13 2005-07-13 威盛电子股份有限公司 线路基板
CN1293793C (zh) * 2003-06-13 2007-01-03 威盛电子股份有限公司 线路基板
TWI241702B (en) * 2003-07-28 2005-10-11 Siliconware Precision Industries Co Ltd Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure
US7112524B2 (en) * 2003-09-29 2006-09-26 Phoenix Precision Technology Corporation Substrate for pre-soldering material and fabrication method thereof
TWI253161B (en) * 2004-09-10 2006-04-11 Via Tech Inc Chip carrier and chip package structure thereof
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP3914239B2 (ja) * 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
US8841779B2 (en) * 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
JP4171492B2 (ja) * 2005-04-22 2008-10-22 松下電器産業株式会社 半導体装置およびその製造方法
US20060255473A1 (en) * 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
JP2007059767A (ja) * 2005-08-26 2007-03-08 Shinko Electric Ind Co Ltd アンダーフィル材を用いて電子部品を搭載した基板及びその製造方法
JP2007103733A (ja) * 2005-10-05 2007-04-19 Nec Electronics Corp 基板およびそれを用いた半導体装置
JP4728782B2 (ja) * 2005-11-15 2011-07-20 パナソニック株式会社 半導体装置およびその製造方法
JP4863746B2 (ja) * 2006-03-27 2012-01-25 富士通株式会社 半導体装置およびその製造方法
JP4773864B2 (ja) * 2006-04-12 2011-09-14 パナソニック株式会社 配線基板及びこれを用いた半導体装置並びに配線基板の製造方法
TWI296184B (en) * 2006-06-06 2008-04-21 Phoenix Prec Technology Corp Method for fabricating electrical connecting structure of circuit board
JP5138277B2 (ja) * 2007-05-31 2013-02-06 京セラＳｌｃテクノロジー株式会社 配線基板およびその製造方法
US8779300B2 (en) * 2007-07-19 2014-07-15 Unimicron Technology Corp. Packaging substrate with conductive structure
KR100876899B1 (ko) * 2007-10-10 2009-01-07 주식회사 하이닉스반도체 반도체 패키지
TWI351087B (en) * 2007-10-16 2011-10-21 Unimicron Technology Corp Package substrate and method for fabricating the same
JP2009117699A (ja) * 2007-11-08 2009-05-28 Shinko Electric Ind Co Ltd 半導体パッケージ用部品及び半導体パッケージ用部品の製造方法
TWI340615B (en) * 2008-01-30 2011-04-11 Advanced Semiconductor Eng Surface treatment process for circuit board
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US7812460B2 (en) * 2008-05-30 2010-10-12 Unimicron Technology Corp. Packaging substrate and method for fabricating the same
US20100007015A1 (en) * 2008-07-11 2010-01-14 Bernardo Gallegos Integrated circuit device with improved underfill coverage
US9129955B2 (en) * 2009-02-04 2015-09-08 Texas Instruments Incorporated Semiconductor flip-chip system having oblong connectors and reduced trace pitches
US20110049703A1 (en) * 2009-08-25 2011-03-03 Jun-Chung Hsu Flip-Chip Package Structure
US20110056738A1 (en) * 2009-09-04 2011-03-10 Phoenix Precision Technology Corporation Package substrate and manufacturing method thereof
US8536718B2 (en) * 2010-06-24 2013-09-17 Stats Chippac Ltd. Integrated circuit packaging system with trenches and method of manufacture thereof
US8502377B2 (en) * 2010-08-06 2013-08-06 Mediatek Inc. Package substrate for bump on trace interconnection
KR101711499B1 (ko) * 2010-10-20 2017-03-13 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US20120152606A1 (en) * 2010-12-16 2012-06-21 Ibiden Co., Ltd. Printed wiring board
CN103229605B (zh) * 2011-07-25 2016-06-08 日本特殊陶业株式会社 布线基板
US8853853B2 (en) * 2011-07-27 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures
US8633598B1 (en) * 2011-09-20 2014-01-21 Amkor Technology, Inc. Underfill contacting stacking balls package fabrication method and structure
US20130249076A1 (en) * 2012-03-20 2013-09-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
US9461008B2 (en) * 2012-08-16 2016-10-04 Qualcomm Incorporated Solder on trace technology for interconnect attachment
TWI528517B (zh) * 2013-03-26 2016-04-01 威盛電子股份有限公司 線路基板、半導體封裝結構及線路基板製程
US9673065B2 (en) * 2013-07-18 2017-06-06 Texas Instruments Incorporated Semiconductor substrate having stress-absorbing surface layer
US10002843B2 (en) * 2015-03-24 2018-06-19 Advanced Semiconductor Engineering, Inc. Semiconductor substrate structure, semiconductor package and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535388B1 (en) * 2001-10-04 2003-03-18 Intel Corporation Wirebonded microelectronic packages including heat dissipation devices for heat removal from active surfaces thereof
CN1529545A (zh) * 2003-09-29 2004-09-15 威盛电子股份有限公司 选择性电镀法
US20070182009A1 (en) * 2006-02-09 2007-08-09 Matsushita Electric Industrial Co., Ltd. Wiring board and method for manufacturing the same and semiconductor device and method for manufacturing the same
US7902660B1 (en) * 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US20120322205A1 (en) * 2011-06-16 2012-12-20 Shinko Electric Industries Co., Ltd. Method for manufacturing wiring substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104392978A (zh) * 2014-11-04 2015-03-04 上海兆芯集成电路有限公司 线路基板和半导体封装结构
CN104392978B (zh) * 2014-11-04 2017-04-12 上海兆芯集成电路有限公司 线路基板和半导体封装结构
CN106206532A (zh) * 2015-05-29 2016-12-07 三星电机株式会社 封装基板和制造封装基板的方法
CN107808869A (zh) * 2016-09-09 2018-03-16 矽品精密工业股份有限公司 电子封装件及其制法
CN110418510A (zh) * 2019-07-15 2019-11-05 宁波华远电子科技有限公司 一种开放性电镀凸台的制作方法

Also Published As

Publication number Publication date
US20190006302A1 (en) 2019-01-03
TW201508879A (zh) 2015-03-01
US10103115B2 (en) 2018-10-16
CN103545286B (zh) 2016-05-11
US10573614B2 (en) 2020-02-25
US20150061119A1 (en) 2015-03-05
TWI514530B (zh) 2015-12-21

Similar Documents

Publication Publication Date Title
US11469201B2 (en) Semiconductor package and method for fabricating base for semiconductor package
JP5185885B2 (ja) 配線基板および半導体装置
CN103545286B (zh) 线路基板、半导体封装结构及线路基板制作工艺
CN103258807A (zh) 线路基板、半导体封装结构及线路基板制作工艺
JP2011142185A (ja) 半導体装置
US7180182B2 (en) Semiconductor component
US5362984A (en) Semiconductor device with jumping wire
CN101621045B (zh) 电路基板及其形成方法以及半导体封装
TWI566352B (zh) 封裝基板及封裝件
CN101197344B (zh) 封装基板及其制作方法
TWI493668B (zh) 接墊結構、線路載板及積體電路晶片
CN1560911B (zh) 电路载板的制造方法
CN102026498A (zh) 线路板的制作方法、线路板及晶片封装结构
CN101937901B (zh) 线路基板及其制作方法与封装结构
US7105926B2 (en) Routing scheme for differential pairs in flip chip substrates
KR102578797B1 (ko) 반도체 패키지
US20050205988A1 (en) Die package with higher useable die contact pad area
KR20090044496A (ko) 스택 패키지
TWI820697B (zh) 電子裝置
CN219457615U (zh) 半导体封装件
JPWO2006028155A1 (ja) モジュール型電子部品及び電子機器
CN112616240A (zh) 芯片基板及主板
KR20240057102A (ko) 집적 회로 디바이스 및 이를 포함하는 반도체 패키지
JP3275647B2 (ja) 半導体装置及びその製造方法並びにその実装構造
CN118055561A (zh) 电路板及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant