CN103515422A - 具有高迁移率和应变沟道的FinFET - Google Patents

具有高迁移率和应变沟道的FinFET Download PDF

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CN103515422A
CN103515422A CN201210326652.5A CN201210326652A CN103515422A CN 103515422 A CN103515422 A CN 103515422A CN 201210326652 A CN201210326652 A CN 201210326652A CN 103515422 A CN103515422 A CN 103515422A
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fin
conducting material
raceway groove
protective layer
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沈俊良
蔡国强
李后儒
梁春升
赖高廷
丁国强
吴集锡
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路器件，包括：至少被部分地嵌入浅沟槽隔离(STI)区并在源极和漏极之间延伸的鳍。该鳍由第一半导体材料形成，并且具有位于第一端部和第二端部之间的修整部分。由第二半导体材料形成的保护层，被设置在该鳍的修整部分的上方，以形成高迁移沟道。栅电极结构在该高迁移沟道上方以及第一端部和第二端部之间形成。本发明提供具有高迁移率和应变沟道的FinFET。

Description

具有高迁移率和应变沟道的FinFET
技术领域
本发明涉及一种集成电路器件，具体而言，本发明涉及鳍场效应晶体管及其形成方法。
背景技术
半导体器件被应用于大量电子器件中，如电脑，手机以及其他电子器件。半导体器件包括集成电路，该集成电路通过在半导体晶圆上设置多种薄膜材料并图案化该薄膜材料而在半导体晶圆上形成。集成电路包括：场效应晶体管(FET)，如金属氧化物半导体(MOS)晶体管。
半导体产业的目标之一是继续缩小规格以及提高单个FET的速度。为了实现这些目标，鳍FET(FinFET)或多栅极晶体管将被用在亚32nm晶体管节点中。例如，FinFET不仅提高了面密度，而且还改善了沟道的栅极控制。
虽然传统的FinFET器件可以提供流动性和/或应变沟道，但是该沟道在这种FinFET器件上形成的工艺可以导致不良结果。例如，源极/漏极选择性外延生长工艺或激活退火工艺可以对FinFET器件的沟道产生不利的热冲击。事实上，该沟道的材料特性可能改变，并且该沟道提供的应变可能衰减或减缓。
此外，沟道的材料与周围材料(如硅)之间的不匹配可能导致点或面晶体缺陷的产生，特别是当该材料受到热加工的时候。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种集成电路器件，包括：在源极和漏极之间延伸的鳍，所述鳍具有位于第一端部和第二端部之间并被保护层覆盖的修整部分，所述修整部分以及所述第一端部和所述第二端部由第一半导体材料形成，所述保护层由与所述第一半导体材料不同的第二半导体材料形成，以形成高迁移沟道；以及在位于所述第一端部和所述第二端部之间的所述高迁移沟道的上方形成的栅电极结构。
在上述集成电路器件中，其中，所述第一半导体材料是硅而所述第二半导体材料是硅锗。
在上述集成电路器件中，其中，所述第二半导体材料是硅锗，锗，以及III-V半导体合金中的一种。
在上述集成电路器件中，其中，所述高迁移沟道包括：设置在所述保护层上方的第二保护层，所述第二保护层由所述第一半导体材料形成。
在上述集成电路器件中，其中，所述高迁移沟道被配置成在鳍中产生张力或压力。
在上述集成电路器件中，其中，所述高迁移沟道的厚度至少小于所述鳍的所述第一端部和所述第二端部之一的厚度。
在上述集成电路器件中，其中，所述鳍的所述修整部分具有正方形的，矩形的，梯形的，三角形的，六边形的，八边形的，倒梯形的，弧形的，以及平面的鳍修整轮廓中的一种。
在上述集成电路器件中，其中，所述高迁移沟道具有正方形的，矩形的，梯形的，三角形的，部分六边形的，六边形的，八边形的，倒梯形的，以及弧形的沟道轮廓中的一种。
在上述集成电路器件中，其中，所述鳍至少被部分地嵌入浅沟槽隔离(STI)区。
根据本发明的另一方面，还提供了一种集成电路器件，包括：在源极和漏极之间延伸的鳍，所述鳍具有位于第一端部和第二端部之间并被第一保护层和第二保护层覆盖的修整部分，所述修整部分、所述第一端部和所述第二端部、以及所述第二保护层由第一半导体材料形成，所述第一保护层由与所述第一半导体材料不同的第二半导体材料形成，以形成高迁移沟道；以及在位于所述第一端部和所述第二端部内侧的所述高迁移沟道的上方形成的栅电极结构。
在上述集成电路器件中，其中，所述第一半导体材料是硅而所述第二半导体材料是硅锗、锗、以及III-V半导体合金中的一种。
在上述集成电路器件中，其中，所述高迁移沟道被配置成在鳍中产生张力或压力。
在上述集成电路器件中，其中，所述高迁移沟道的厚度至少小于所述鳍的所述第一端部和所述第二端部之一的厚度。
在上述集成电路器件中，其中，所述鳍的所述修整部分具有正方形的，矩形的，梯形的，三角形的，六边形的，八边形的，倒梯形的，弧形的，以及平面的鳍修整轮廓中的一种。
在上述集成电路器件中，其中，所述高迁移沟道具有正方形的，矩形的，梯形的，三角形的，部分六边形的，六边形的，八边形的，倒梯形的，以及弧形的沟道轮廓中的一种。
在上述集成电路器件中，其中，第一间隔件被设置成与所述源极相邻并位于所述鳍的所述第一端部的上方，而第二间隔件被设置成与所述漏极相邻并位于所述鳍的所述第二端部的上方。
在上述集成电路器件中，其中，所述鳍至少被部分地嵌入浅沟槽隔离(STI)区。
根据本发明的又一方面，还提供了一种形成鳍场效应晶体管(FinFET)器件的方法，包括：由第一半导体材料形成鳍，所述鳍被设置在源极和漏极之间，并且至少被部分地嵌入浅沟槽隔离(STI)区；修整所述鳍位于第一端部和第二端部之间的一部分，以形成修整部分；用第二半导体材料覆盖所述修整部分，以形成高迁移沟道；以及在所述高迁移沟道上方以及所述第一端部和所述第二端部之间形成栅电极结构。
在上述方法中，进一步包括：用所述第一半导体材料覆盖所述第二半导体材料，以形成所述高迁移沟道。
在上述方法中，进一步包括：通过所述高迁移沟道，在所述鳍中至少产生张力与压力之一。
附图说明
为了更完全地理解本发明及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1是为了说明的目的而削减了部分的现有技术FinFET器件的透视图；
图2是图1所述的现有技术FinFET器件大致沿线x-x截取的横截面；
图3是为了说明的目的而削减了部分的实施例FinFET器件的透视图；
图4是图3所述的FinFET器件大致沿线x-x截取的横截面；
图5是图3所述的FinFET器件的俯视图；
图6是用来在与图3的FinFET器件相似的实施例FinFET器件中形成高迁移沟道的第二保护层的截面图；
图7是在形成图3的FinFET器件的实施例方法中使用的替换栅极工艺的截面图；
图8是形成图3的FinFET器件的实施例方法中的保护性氧化物去除工艺的透视图；
图9是形成图3的FinFET器件的实施例方法中的修整工艺的透视图；
图10是用于形成图3的FinFET器件中的高迁移沟道的保护层的透视图；
图11-20是图3的FinFET器件大致沿图8所述线y-y截取的经过修整的鳍的实施例轮廓的截面图；以及
图21-31是图3的FinFET器件大致沿图9所述线y-y截取的迁移沟道的实施例轮廓的截面图。
除非另有说明，不同附图中的相应标号和符号通常指相应部件。将附图绘制成清楚地示出实施例的相关方面而不必须成比例绘制。
具体实施方式
以下详细讨论制作和使用实施例。然而，应当理解，本发明提供了许多可以在各种具体情况下实施的适用概念。所讨论的具体实施例，仅仅是说明性的，并不限定本发明的范围。
本发明将被描述为关于在一种具体情况下的实施例，即FinFET金属氧化物半导体(MOS)。然而，该概念也可以被应用在其他集成电路和电子结构中，其中包括，但不仅限于：多栅级场效应晶体管(MuGFET)以及纳米线器件。
图1-2代表现有技术FinFET器件10，其将被简要描述。FinFET器件10包括：支撑数个鳍14的衬底12，其至少被部分地嵌入浅沟槽隔离(STI)区16。鳍14通常在位于FinFET器件10的相对端的源漏区18之间延伸。堆叠在邻近源漏区18的一部分鳍14上的间隔件20被设置在图2所示的栅电极结构22的相对侧。
虽然为了便于图示而并未示出，图1和图2中的栅电极结构22可以包括：若干分立层或元件，例如，界面氧化层，高k介电层，以及金属栅极层。在图1-2中，衬底12由硅形成，而鳍14由硅锗形成。在实施例中，鳍14的锗剂量浓度在大约10％到100％的范围内。
如图2所示，鳍14位于间隔件20正下方(并与源漏区18相邻)的部分，以及鳍14位于栅电极结构22正下方的部分由相同材料形成，并且共同形成迁移沟道(mobility channel)24。不幸的是，当这两部分都由相同的半导体材料(如硅锗)形成时，迁移沟道24可能随着n-型FET激活而恶性退化，其将导致更高的源/漏电阻。此外，整个迁移沟道24使用相同材料，产生高热预算，其将导致升高的界面陷阱密度(Dit)。也可以认识到其他不利结果。
参见图3，示出了实施例FinFET器件26。如下将更完整地说明，可以使用简单的替换栅极工艺形成FinFET器件26，在间隔件和栅电极结构下方使用不同的半导体材料以降低沟道体积并引发低源/漏电阻，并提供更低的热预算以及更高的沟道剂量浓度。
如图3-4所示，FinFET器件26包括：一个或多个由下方衬底30支撑的鳍28，衬底可以是适当形成的硅或其他半导体材料。每个鳍28在源漏区32之间延伸。在实施例中，每个鳍28至少被部分地嵌入STI区34。在另外的实施例中，鳍28可以终止于STI区34的上表面下方或与之齐平。
每个鳍28包括：位于每个鳍28相对侧的第一端部38和第二端部40之间的修整部分(trimmed portion)36。如下将更完整的说明，修整部分36通常具有相对于第一和第二端部38，40缩减的轮廓。修整部分36以及第一和第二端部38，40由第一半导体材料42形成。在实施例中，第一半导体材料42是硅。
在实施例中，修整部分36被保护层44覆盖(又名，应变膜)。在实施例中，保护层44大约厚0.1nm(1A)到50μm。保护层44由与第一半导体材料42不同的第二半导体材料46形成，以此形成高迁移沟道48。在实施例中，第二半导体材料46是硅锗，锗，或III-V半导体合金。高迁移沟道48被配置成在鳍28中产生张力或压力。
在实施例中，间隔件50在每个鳍28的第一端部38和第二端部40的上方形成。如图所示，间隔件50通常与源漏区32相邻并设置在如图4所示的栅电极结构52的相对侧。虽然在图4中示出为单个元件，但栅电极结构52可能包括，例如：界面氧化层，高k介电层，以及金属栅极。
如图4所示，在实施例中，高迁移沟道48(以及鳍28下面的修整部分36)的宽度54小于大约5μm。此外，在实施例中，第一和第二端部38，40的宽度56小于大约5μm。仍参见图4，在实施例中，高迁移沟道48的高度58小于大约1μm。此外，在实施例中，第一和第二端部38，40的高度60小于大约1μm。在实施例中，高迁移沟道48的宽度54和/或高度58可以比第一和第二端部38，40的要小。
现参见图5，在实施例中，鳍28的高迁移沟道48的厚度62小于第一和第二端部38，40的厚度64。通过增加第一和第二端部38，40的相对于高迁移沟道48的厚度62的厚度，第一和第二端部38，40的寄生电阻被降低。为了进一步降低寄生电阻，在实施例中，如图5所示，源漏区32被扩大以合并每个鳍28。在此实施例中，源漏区32可以由外延工艺形成。
如图6所示，在实施例中，第二保护层66可以在保护层44上方形成，以形成高迁移沟道48。在实施例中，第二保护层66由第一半导体材料42形成。在实施例中，第二保护层66由硅形成。在实施例中，第二保护层66大约0.1nm(1A)至大约50μm厚。在实施例中，第二保护层66的不同部分可以具有不同的晶体结构。例如，第二保护层顶部的晶体结构可以是<001>，并且第二保护层66侧壁的晶体结构可以是<110>。在其他实施例中，不同的晶体结构可以被用于第二保护层66。在实施例中，高迁移沟道48具有<110>晶体结构，并且提供可以改进沟道迁移率的压缩应变。
总体参见图7-10，描述了形成图3的FinFET器件26的实施例方法。在图7中，示出了部分形成的集成电路器件。值得注意，去除了部分形成的集成电路器件的一部分以便于图示。首先，一个或多个传统的鳍68使用公知方法形成。此后，栅极电介质(未示出)被设置在鳍68上。其次，实施替换栅极(RPG)工艺。在RPG工艺中，保护材料70(例如，保护氧化物或多晶硅)在鳍68以及间隔件50之间的STI区域16上方形成。如图7所示，随着鳍28被保护起来，形成了源漏区32。在实施例中，源漏区32通过使用大约600℃以下的选择性外延生长(SEG)工艺形成。在实施例中，还实施了大约600℃以下的退火工艺。
在源漏区32形成之后，如图8所示，保护材料70以及栅极电介质被去除。保护氧化物70以及栅极电介质的去除使得鳍68的中心部分未被覆盖。换句话说，在间隔件50内侧的鳍68的一部分现在被暴露出来。如上面所提到的，鳍68由第一半导体材料42形成，在本实例中是硅。
其次，如图9所示，每个鳍68在第一和第二端部38，40之间的一部分被修整，以形成鳍的修整部分36。在实施例中，鳍修整工艺可以被使用，以形成修整部分36。在实施例中，可以实施可选的重塑工艺，取决于例如器件优化需求。
在鳍28被满足需要地塑形之后，如图10所示，修整部分36可以用第二半导体材料46覆盖或盖上。当修整部分36被保护层44和/或第二保护层66(图6)覆盖的时候，在鳍28中便形成了高迁移沟道48。在实施例中，正如上面提到的，保护层44可以由硅锗，锗，或III-V半导体合金形成。在实施例中，在保护层44上方形成的第二保护层66(图6)可以由硅形成。
如图10或图6所示，在高迁移沟道48形成之后，栅电极结构52(图4)便形成了。正如前面所提到的，栅电极结构52可以包括：界面氧化层，介电层，以及金属栅极层。栅电极结构52在高迁移沟道48和STI区34的上方形成。栅电极结构52同样在每个鳍28的第一和第二端部38，40之间以及间隔件50内侧形成。
总体参见图11-20，在各种实施例中，鳍28的修整部分36可以具有，例如，正方形的，矩形的，梯形的，三角形的，六边形的，八边形的，倒梯形的，弧形的，以及平面的鳍修整轮廓72。在其他实施例中，鳍28的修整部分36也可以以其他修整的轮廓72形成。此外，如图21-31整体示出的，高迁移沟道48可以具有，例如，正方形的，矩形的，梯形的，三角形的，部分六边形的，六边形的，八边形的，倒梯形的，以及弧形的沟道轮廓74。在其他实施例中，高迁移沟道48也可以以其他修整的轮廓74形成。
上述形成的FinFET器件26或其他集成电路器件具有若干有益并满足需要的特性。例如，使用实施起来相对简单的RPG工艺形成FinFET器件26。此外，FinFET器件26在间隔件50下方提供了无锗的沟道，并且具有降低的沟道体积，以引发低电阻。进一步，FinFET器件26具有更低的热预算，并且实现了更高的沟道剂量浓度。
在实施例中，集成电路器件包括：在源极和漏极之间延伸的鳍。鳍具有位于第一端部和第二端部之间的修整部分，并且被保护层覆盖。修整部分以及第一端部和第二端部由第一半导体材料形成。保护层由与第一半导体材料不同的第二半导体材料形成，以形成高迁移沟道。栅电极结构在位于第一端部和第二端部之间的高迁移沟道的上方形成。
在实施例中，集成电路器件包括：在源极和漏极之间延伸的鳍。鳍具有位于第一端部和第二端部之间的修整部分，并且被第一保护层和第二保护层覆盖。修整部分，第一端部和第二端部，以及第二保护层由第一半导体材料形成。第一保护层由与第一半导体材料不同的第二半导体材料形成，以形成高迁移沟道。栅电极结构在位于第一端部和第二端部内侧的高迁移沟道的上方形成。
在实施例中，提供了一种形成FinFET的方法。鳍由第一半导体材料形成。鳍被设置在源极和漏极之间，并且至少被部分地嵌入浅沟槽隔离(STI)区。鳍位于第一端部和第二端部之间的一部分被修整，以形成修整部分。修整部分被第二半导体材料覆盖，以形成高迁移沟道。栅电极结构在高迁移沟道上方以及第一端部和第二端部之间形成。
虽然本发明提供了示例性实施例，但本说明书不应被理解为限定的意思。示例性实施例的各种改变和组合，以及其他实施例对于所属领域的技术人员来说，在参考本说明书的基础上将是显而易见的。因此，所附的权利要求包括任何这种修改或实施例。

Claims (10)

1.一种集成电路器件，包括：
在源极和漏极之间延伸的鳍，所述鳍具有位于第一端部和第二端部之间并被保护层覆盖的修整部分，所述修整部分以及所述第一端部和所述第二端部由第一半导体材料形成，所述保护层由与所述第一半导体材料不同的第二半导体材料形成，以形成高迁移沟道；以及
在位于所述第一端部和所述第二端部之间的所述高迁移沟道的上方形成的栅电极结构。
2.根据权利要求1所述的集成电路器件，其中，所述第一半导体材料是硅而所述第二半导体材料是硅锗。
3.根据权利要求1所述的集成电路器件，其中，所述第二半导体材料是硅锗，锗，以及III-V半导体合金中的一种。
4.根据权利要求1所述的集成电路器件，其中，所述高迁移沟道包括：设置在所述保护层上方的第二保护层，所述第二保护层由所述第一半导体材料形成。
5.根据权利要求1所述的集成电路器件，其中，所述高迁移沟道被配置成在鳍中产生张力或压力。
6.一种集成电路器件，包括：
在源极和漏极之间延伸的鳍，所述鳍具有位于第一端部和第二端部之间并被第一保护层和第二保护层覆盖的修整部分，所述修整部分、所述第一端部和所述第二端部、以及所述第二保护层由第一半导体材料形成，所述第一保护层由与所述第一半导体材料不同的第二半导体材料形成，以形成高迁移沟道；以及
在位于所述第一端部和所述第二端部内侧的所述高迁移沟道的上方形成的栅电极结构。
7.根据权利要求6所述的集成电路器件，其中，所述第一半导体材料是硅而所述第二半导体材料是硅锗、锗、以及III-V半导体合金中的一种。
8.根据权利要求6所述的集成电路器件，其中，所述高迁移沟道被配置成在鳍中产生张力或压力。
9.一种形成鳍场效应晶体管(FinFET)器件的方法，包括：
由第一半导体材料形成鳍，所述鳍被设置在源极和漏极之间，并且至少被部分地嵌入浅沟槽隔离(STI)区；
修整所述鳍位于第一端部和第二端部之间的一部分，以形成修整部分；
用第二半导体材料覆盖所述修整部分，以形成高迁移沟道；以及
在所述高迁移沟道上方以及所述第一端部和所述第二端部之间形成栅电极结构。
10.根据权利要求9所述的方法，进一步包括：用所述第一半导体材料覆盖所述第二半导体材料，以形成所述高迁移沟道。
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