CN108807276A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN108807276A
CN108807276A CN201710312533.7A CN201710312533A CN108807276A CN 108807276 A CN108807276 A CN 108807276A CN 201710312533 A CN201710312533 A CN 201710312533A CN 108807276 A CN108807276 A CN 108807276A
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China
Prior art keywords
semiconductor structure
substrate
source
side wall
forming method
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CN201710312533.7A
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English (en)
Inventor
周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710312533.7A priority Critical patent/CN108807276A/zh
Priority to US15/971,002 priority patent/US10431498B2/en
Publication of CN108807276A publication Critical patent/CN108807276A/zh
Pending legal-status Critical Current

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Abstract

本发明提供一种半导体结构及其形成方法，所述形成方法包括：提供基底，所述基底上形成有栅极结构，所述栅极结构包括栅极以及位于栅极侧壁上的侧墙，所述栅极结构两侧的基底中形成有源漏掺杂区；在所述侧墙的侧壁上形成牺牲层；对所述源漏掺杂区进行预非晶化离子注入处理。本发明形成的半导体结构的电学性能得到提高。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体制造技术领域，特别涉及一种半导体结构及其形成方法。
背景技术
随着半导体技术的飞速发展，半导体器件的特征尺寸不断缩小，使得集成电路的集成度越来越高，这对器件的性能也提出了更高的要求。
目前，随着金属-氧化物半导体场效应晶体管(MOSFET)的尺寸不断变小。为了适应工艺节点的减小，只能不断缩短MOSFET场效应管的沟道长度。沟道长度的缩短具有增加芯片的管芯密度、增加MOSFET场效应管的开关速度等好处。
然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，这样一来栅极对沟道的控制能力变差，栅极电压夹断(pinch off)沟道的难度也越来越大，使得亚阀值漏电现象，即短沟道效应(SCE：short-channel effects)成为一个至关重要的技术问题。
因此，为了更好的适应器件尺寸按比例缩小的要求，半导体工艺逐渐开始从平面MOSFET晶体管向具有更高功效的三维立体式的晶体管过渡，如鳍式场效应管(FinFET)。FinFET具有很好的沟道控制能力。
现有技术形成的半导体结构的电学性能有待提高。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法，提高半导体结构的电学性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底上形成有栅极结构，所述栅极结构包括栅极以及位于栅极侧壁上的侧墙，所述栅极结构两侧的基底中形成有源漏掺杂区；在所述侧墙的侧壁上形成牺牲层；对所述源漏掺杂区进行预非晶化离子注入处理。
可选的，所述牺牲层的材料为：SiO2、SiC或者SiON中的一种或者多种。
可选的，所述牺牲层的厚度在30埃至150埃范围内。
可选的，形成所述牺牲层的步骤包括：在所述基底以及栅极结构的侧壁和顶部上形成牺牲膜；在所述牺牲膜上形成硬掩膜；以所述硬掩膜为掩膜刻蚀所述牺牲膜，去除位于所述基底以及栅极结构顶部上的牺牲膜，形成所述牺牲层。
可选的，形成所述牺牲膜的工艺为化学气相沉积工艺。
可选的，去除位于所述基底以及栅极结构顶部上的牺牲膜的工艺为干法刻蚀工艺。
可选的，对所述源漏掺杂区进行预非晶化离子注入处理的掺杂离子为：C、Ge或者Si中的一种或者多种。
可选的，所述预非晶化离子注入处理的工艺参数包括：掺杂离子的注入能量为5kev至20kev，掺杂离子的注入剂量为4.0e13atom/cm2至2.3e15atom/cm2。
可选的，所述栅极为金属栅极或者多晶硅栅极。
可选的，形成所述源漏掺杂区之后，形成所述牺牲层之前，还包括：在所述基底以及栅极结构的侧壁和顶部上形成刻蚀停止层。
可选的，所述刻蚀停止层的材料与所述牺牲层的材料不同。
可选的，对所述源漏掺杂区进行预非晶化离子注入处理之后，还包括：在所述源漏掺杂区顶部上形成与所述源漏掺杂区电连接的导电插塞。
可选的，所述基底包括：衬底以及位于衬底上的多个分立的鳍部；所述栅极横跨所述鳍部；所述源漏掺杂区位于所述栅极两侧的鳍部中。
相应地，本发明还提供一种半导体结构，包括：基底，所述基底上具有栅极结构，所述栅极结构包括栅极以及位于栅极侧壁上的侧墙；牺牲层，位于所述侧墙的侧壁上；源漏掺杂区，位于所述栅极结构两侧的基底中。
可选的，所述牺牲层的材料为：SiO2、SiC或者SiON中的一种或者多种。
可选的，所述牺牲层的厚度在30埃至150埃范围内。
与现有技术相比，本发明的技术方案具有以下优点：
所述牺牲层由于位于所述侧墙的侧壁上，在进行预非晶化离子注入处理的过程中，能够使得所述离子注入处理的离子注入位置远离所述半导体结构的沟道区，从而使得进行预非晶化离子注入之后形成的非晶层也远离所述沟道区。所述非晶层位于远离所述沟道区的位置，有利于缓解非晶层重结晶时发生的应力释放问题。所述非晶层质量的提高使得在所述源漏掺杂区上形成的金属硅化物层质量也得到改善，从而有利于降低半导体结构的肖基特势垒，减小半导体结构的接触电阻，进而使得所述半导体结构的电学性能得到改善。
可选方案中，所述牺牲层的厚度在30埃至150埃范围内。若所述牺牲层的厚度过大，则会导致所述预非晶化离子注入到所述源漏掺杂区的范围过小，从而不利于降低所述半导体结构的接触电阻；若所述牺牲层的厚度过小，则会造成预非晶化离子注入的位置靠近沟道区，从而使得所述非晶层重结晶时容易发生应力释放问题，进而使得所述半导体结构的电学性能差。
附图说明
图1至图12是本发明实施例半导体结构形成过程的结构示意图。
具体实施方式
根据背景技术形成的半导体结构的电学性能有待提高。现结合半导体结构的形成过程对半导体结构电学性能有待提高的原因进行分析。
所述形成方法包括：提供基底；在所述基底上形成栅极；在所述栅极的侧壁上形成侧墙；在所述栅极两侧的基底中形成源漏掺杂区；形成所述源漏掺杂区之后，对所述源漏掺杂区进行预非晶化离子注入处理。
经分析发现，导致所述半导体结构电学性能有待提高的原因包括：形成所述源漏掺杂区的步骤之后，再对所述源漏掺杂区进行预非晶化离子注入处理，位于栅极侧壁上的侧墙用于定义所述源漏掺杂区的位置，同时也用于定义所述预非晶化离子注入的离子注入位置，使得所述离子注入位置容易距离半导体结构沟道区的位置近。在进行预非晶化离子注入之后，在所述源漏掺杂区中会形成非晶层，由于所述非晶层的位置距离所述沟道区近，所述非晶层重结晶时容易发生应力释放问题，降低了所述非晶层的质量，相应地也使得后续在所述源漏掺杂区上形成的金属硅化物层的质量下降，从而不利于降低所述半导体结构的肖基特势垒，无法减小所述半导体结构的接触电阻，进而导致所述半导体结构的电学性能下降。
为了解决上述问题，本发明实施例中通过在所述侧墙的侧壁上形成牺牲层，所述牺牲层用于定义后续对所述源漏掺杂区进行预非晶化离子注入的位置，使得预非晶化离子注入位置远离所述半导体结构的沟道区，从而使得进行预非晶化离子注入之后形成的非晶层也远离所述沟道区。所述非晶层位于远离所述沟道区的位置，解决了所述非晶层重结晶时发生的应力释放问题，从而使得所述半导体结构的电学性能得到改善。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图12是本发明实施例半导体结构形成过程的结构示意图。
参考图1，提供基底，所述基底包括衬底200以及位于衬底200上的多个分立的鳍部210；在所述鳍部210露出的衬底200上还形成有隔离结构220，所述隔离结构220顶部低于所述鳍部210顶部。
本实施例中，所述半导体结构为鳍式场效应管。在本发明其他实施例中，形成的半导体结构还可以为平面结构，相应的，所述基底为平面衬底。
本实施例中，所述衬底200包括用于形成NMOS器件的第一区域I和用于形成PMOS器件的第二区域II。在本发明其他实施例中，所述衬底还可以仅包括第一区域或者第二区域中的一种，相应形成的半导体器件为NMOS器件或者PMOS器件。
本实施例中，所述衬底200的材料为Si。在本发明其他实施例中，所述衬底的材料还可以为Ge、SiGe、SiC、GaAs或InGa。在其他实施例中，所述衬底还可以为绝缘体上的Si衬底或者绝缘体上的Ge衬底。
本实施例中，所述鳍部210的材料为Si。在本发明其他实施例中，所述鳍部的材料还可以为Ge、SiGe、SiC、GaAs或InGa。
本实施例中，所述隔离结构220可以起到电学隔离相邻所述鳍部210的作用。所述隔离结构220的材料为SiO2。在本发明其他实施例中，所述隔离结构的材料还可以为SiN或SiON。
结合参考图2至图4，在所述基底上形成栅极结构(未标示)，所述栅极结构包括栅极230以及位于栅极230侧壁上的侧墙(未标示)。
本实施例中，所述栅极结构横跨所述鳍部210，所述侧墙为叠层结构，包括：偏移侧墙232和主侧墙233。
以下将结合附图对所述栅极结构的形成过程做详细说明。
参考图2，形成横跨所述鳍部210的栅极230，所述栅极230覆盖所述鳍部210的部分侧壁和顶部，所述栅极230顶部上具有硬掩膜231。
本实施例中，所述栅极230为多晶硅栅极。在本发明其他实施例中，所述栅极还可以为金属栅极。
本实施例中，形成所述栅极230的步骤包括：在所述鳍部210以及隔离结构220顶部上形成栅极膜；在所述栅极膜上形成掩膜层；对所述掩膜层进行图形化处理，形成硬掩膜231；以所述硬掩膜231为掩膜刻蚀所述栅极膜，形成所述栅极230。
本实施例中，所述硬掩膜231在后续工艺中可以起到保护所述栅极230顶部的作用。所述硬掩膜231的材料为SiN。
参考图3，在所述栅极230的侧壁上形成偏移侧墙232，形成偏移侧墙232之后，在所述栅极230两侧的鳍部210中形成轻掺杂区(图未示)。
本实施例中，所述偏移侧墙232用于定于所述轻掺杂区的位置。所述偏移侧墙232的材料为SiN。
本实施例中，所述轻掺杂区为后续源漏掺杂区提供杂质浓度梯度，从而减小结与沟道区之间的电场，有利于防止产生热载流子。
参考图4，在所述偏移侧墙232的侧壁上形成主侧墙233。
本实施例中，所述主侧墙233用于定义后续源漏掺杂区的位置。所述主侧墙233的材料为SiN。
参考图5，在所述栅极结构两侧的鳍部210中形成源漏掺杂区240。
本实施例中，位于第一区域I的源漏掺杂区240的材料为Si或者SiC，且所述源漏掺杂区240中还掺杂有N型离子，所述N型离子为P、As或Sb；位于第二区域II的源漏掺杂区240的材料为Si或者SiGe，且所述源漏掺杂区240中还掺杂有P型离子，所述P型离子为B、Ga或In。
参考图6，在所述隔离结构220顶部、鳍部210以及栅极结构的侧壁和顶部上形成刻蚀停止层250。
本实施例中，所述刻蚀停止层250为后续形成导电插塞提供刻蚀停止位置。所述刻蚀停止层250的材料为SiN、SiBCN、SiCN或者SiOCN中的一种或者多种。
本实施例中，所述刻蚀停止层250的厚度既不能过大也不能过小。若所述刻蚀停止层250的厚度过大，则会导致后续层间介质层填洞能力差；若所述刻蚀停止层250的厚度过小，则会使得后续去除所述牺牲层的刻蚀工艺会对半导体结构产生不良影响。因此，所述刻蚀停止层250的厚度为40埃至100埃。
结合参考图7和图8，在所述侧墙的侧壁上形成牺牲层261(如图8所示)。
以下将结合附图对所述牺牲层261的形成过程做详细说明。
本实施例中，先形成所述牺牲层261，后续步骤中再对所述源漏掺杂区240进行预非晶化离子注入处理。由于所述牺牲层261位于所述侧墙的侧壁上，所述牺牲层261用于定义预非晶化离子注入的位置，因此，通过所述牺牲层261可以使得进行离子注入的位置远离所述半导体结构的沟道区。进行预非晶化离子注入的步骤中，会在所述源漏掺杂区240中形成非晶层，相应地所述非晶层的位置距离沟道区的距离较远，从而可以改善所述非晶层重结晶时导致的应力释放问题，进而提高了所述非晶层的质量。后续步骤中会在所述源漏掺杂区240上形成金属硅化物层，由于所述非晶层质量好，使得所述金属硅化物层的质量也得到提高，从而有利于降低半导体结构的肖基特势垒，减小半导体结构的接触电阻，进而使得所述半导体结构的电学性能得到改善。
本实施例中，所述牺牲层261的材料与所述刻蚀停止层250的材料不同。由于后续对所述源漏掺杂区240进行预非晶化离子注入处理之后，还会去除所述牺牲层261，因此所述牺牲层261选取与所述刻蚀停止层250具有选择比，且易于去除的材料，具体为：SiO2、SiC或者SiON中的一种或者多种。
本实施例中，通过控制所述牺牲层261的厚度能够使得所述预非晶化离子注入的位置在合适的范围内。若所述牺牲层261的厚度过大，则会导致所述预非晶化离子注入到所述源漏掺杂区240的范围过小，从而不利于降低所述半导体结构的接触电阻；若所述牺牲层261的厚度过小，则会造成预非晶化离子注入的位置靠近沟道区，从而使得所述非晶层重结晶时容易发生应力释放问题，进而使得所述半导体结构的电学性能差。因此，所述牺牲层261的厚度在30埃至150埃范围内。
本实施例中，形成所述牺牲层261的步骤包括：在所述刻蚀停止层250上形成牺牲膜260(参考图7)；在所述牺牲膜260上形成硬掩膜；以所述硬掩膜为掩膜刻蚀所述牺牲膜260，去除位于所述隔离结构220顶部、鳍部210的侧壁和顶部以及栅极结构顶部上的牺牲膜260，形成所述牺牲层261。
本实施例中，形成所述牺牲膜260的工艺为原子层沉积工艺。所述原子层沉积工艺的参数包括：前驱体为Si和O2,，温度为80℃至300℃，压力为5mtorr至20mtorr，次数为5次至50次。在本发明其他实施例中，形成所述牺牲膜的工艺还可以为化学气相沉积工艺。
参考图9，对所述源漏掺杂区240进行预非晶化离子注入处理。
本实施例中，对所述源漏掺杂区240进行预非晶化离子注入处理的目的是在所述源漏掺杂区240内形成非晶层，使得后续在所述源漏掺杂区240上形成的金属硅化物层质量得到提高，从而降低所述半导体结构的肖基特势垒，并使得所述半导体结构的接触电阻得以减小，提高所述半导体结构的电学性能。由于所述牺牲层261使得预非晶化离子注入形成的非晶层位于远离沟道区的位置，从而缓解了所述非晶层重结晶时造成的应力释放问题，进而有利于减小所述半导体结构的接触电阻。
本实施例中，对所述源漏掺杂区240进行预非晶化离子注入处理的掺杂离子为：C、Ge或者Si中的一种或者多种。具体地，所述预非晶化离子注入处理的工艺参数包括：掺杂离子的注入能量为5kev至20kev，掺杂离子的注入剂量为4.0e13atom/cm2至2.3e15atom/cm2。
参考图10，对所述源漏掺杂区240进行预非晶化离子注入处理之后，去除所述牺牲层261(如图9所示)。
本实施例中，去除所述牺牲层261能够提高后续层间介质层的填洞能力，从而提高所述层间介质层的质量。在本发明其他实施例中，对所述源漏掺杂区进行预非晶化离子注入处理之后，还可以保留所述牺牲层，这样可以简化半导体结构的工艺流程。
参考图11，在所述栅极230露出的衬底200上形成层间介质层262。
本实施例中，所述层间介质层262起到隔离相邻金属层的作用。所述层间介质层262的材料为SiO2、SiN、SiON、SiOC中的一种或者多种。
参考图12，去除所述栅极230(参考图11)和硬掩膜231(参考图11)形成开口(图未示)，形成填充满所述开口的金属栅极270；在所述层间介质层262上形成介电层263；在所述源漏掺杂区240顶部上形成与所述源漏掺杂区240电连接的导电插塞280。
本实施例中，在形成所述导电插塞280的步骤之前，通常还会在所述源漏掺杂区240顶部上形成金属硅化物层(图未示)，所述金属硅化物层用于减小所述半导体结构的接触电阻。由于对所述源漏掺杂区240进行预非晶化离子注入的位置远离沟道区，使得形成的非晶层不容易发生应力释放问题，即所述非晶层远离所述沟道区，使得所述应力得以保持，从而提高了所述非晶层的质量，进而使得所述金属硅化物层的质量也得到改善，因此，所述半导体结构的接触电阻得到减小。
本实施例中，所述金属栅极270的材料为：Ti、Ta、TiN、TaN、AlTi、AlNTi、Cu、Al、Wu、Ag或Au中的一种或多种。
本实施例中，所述介电层263的材料为低K介电常数的材料。所述低介电常数的材料是指介电常数低于3.9的材料。
相应地，本发明还提供一种半导体结构，参考图8，包括：基底，所述基底包括衬底200以及位于衬底200上的多个分立的鳍部210；隔离结构220，位于所述鳍部210露出的衬底200上；栅极结构，位于所述鳍部210上，所述栅极结构顶部上具有硬掩膜231，所述栅极结构包括栅极230以及位于栅极230侧壁上的侧墙，所述侧墙包括偏移侧墙232和主侧墙233；牺牲层261，位于所述侧墙的侧壁上；源漏掺杂区240，位于所述栅极结构两侧的鳍部210中。
本实施例中，所述牺牲层261能够使得对所述源漏掺杂区240进行预非晶化离子注入处理的位置远离所述半导体结构沟道区，从而有利于减小半导体接触电阻，提高半导体结构的电学性能。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (16)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底上形成有栅极结构，所述栅极结构包括栅极以及位于栅极侧壁上的侧墙，所述栅极结构两侧的基底中形成有源漏掺杂区；
在所述侧墙的侧壁上形成牺牲层；
对所述源漏掺杂区进行预非晶化离子注入处理。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述牺牲层的材料为：SiO2、SiC或者SiON中的一种或者多种。
3.如权利要求2所述的半导体结构的形成方法，其特征在于，所述牺牲层的厚度在30埃至150埃范围内。
4.如权利要求3所述的半导体结构的形成方法，其特征在于，形成所述牺牲层的步骤包括：
在所述基底以及栅极结构的侧壁和顶部上形成牺牲膜；
在所述牺牲膜上形成硬掩膜；
以所述硬掩膜为掩膜刻蚀所述牺牲膜，去除位于所述基底以及栅极结构顶部上的牺牲膜，形成所述牺牲层。
5.如权利要求4所述的半导体结构的形成方法，其特征在于，形成所述牺牲膜的工艺为化学气相沉积工艺。
6.如权利要求4所述的半导体结构的形成方法，其特征在于，去除位于所述基底以及栅极结构顶部上的牺牲膜的工艺为干法刻蚀工艺。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，对所述源漏掺杂区进行预非晶化离子注入处理的掺杂离子为：C、Ge或者Si中的一种或者多种。
8.如权利要求7所述的半导体结构的形成方法，其特征在于，所述预非晶化离子注入处理的工艺参数包括：掺杂离子的注入能量为5kev至20kev，掺杂离子的注入剂量为4.0e13atom/cm2至2.3e15atom/cm2。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，所述栅极为金属栅极或者多晶硅栅极。
10.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述源漏掺杂区之后，形成所述牺牲层之前，还包括：在所述基底以及栅极结构的侧壁和顶部上形成刻蚀停止层。
11.如权利要求10所述的半导体结构的形成方法，其特征在于，所述刻蚀停止层的材料与所述牺牲层的材料不同。
12.如权利要求1所述的半导体结构的形成方法，其特征在于，对所述源漏掺杂区进行预非晶化离子注入处理之后，还包括：在所述源漏掺杂区顶部上形成与所述源漏掺杂区电连接的导电插塞。
13.如权利要求1所述的半导体结构的形成方法，其特征在于，所述基底包括：
衬底以及位于衬底上的多个分立的鳍部；
所述栅极横跨所述鳍部；
所述源漏掺杂区位于所述栅极两侧的鳍部中。
14.一种半导体结构，其特征在于，包括：
基底，所述基底上具有栅极结构，所述栅极结构包括栅极以及位于栅极侧壁上的侧墙；
牺牲层，位于所述侧墙的侧壁上；
源漏掺杂区，位于所述栅极结构两侧的基底中。
15.如权利要求14所述的半导体结构，其特征在于，所述牺牲层的材料为：SiO2、SiC或者SiON中的一种或者多种。
16.如权利要求15所述的半导体结构，其特征在于，所述牺牲层的厚度在30埃至150埃范围内。
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