CN103247599A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN103247599A
CN103247599A CN2012103974514A CN201210397451A CN103247599A CN 103247599 A CN103247599 A CN 103247599A CN 2012103974514 A CN2012103974514 A CN 2012103974514A CN 201210397451 A CN201210397451 A CN 201210397451A CN 103247599 A CN103247599 A CN 103247599A
Authority
CN
China
Prior art keywords
semiconductor element
insulation material
metallic film
material layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012103974514A
Other languages
English (en)
Other versions
CN103247599B (zh
Inventor
泽地茂典
山方修武
井上广司
板仓悟
近井智哉
堀将彦
胜又章夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rely On Technology Japan Co
Original Assignee
J Devices Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by J Devices Corp filed Critical J Devices Corp
Publication of CN103247599A publication Critical patent/CN103247599A/zh
Application granted granted Critical
Publication of CN103247599B publication Critical patent/CN103247599B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82031—Reshaping, e.g. forming vias by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

本发明涉及半导体器件及其制造方法。一种半导体器件，包括：半导体元件；支撑基板；用于密封半导体元件及其周边的绝缘材料层；在绝缘材料层中提供的金属薄膜布线层，其一部分暴露在外表面上；以及在绝缘材料层中提供并电连接到金属薄膜布线层的金属过孔，其中提供多个半导体元件，并且各半导体元件通过绝缘材料层叠以便每个半导体元件的电路表面面向金属薄膜布线层，以及每个半导体元件的电极衬垫被暴露而没有被层叠在其上的半导体元件隐藏，并电连接到金属薄膜布线层。可以更小和更薄的尺寸制造半导体器件，而且通过使得多个半导体芯片成为垂直层叠结构可以减少制造步骤的数目。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法。更具体地，本发明涉及具有其中垂直层叠多个半导体芯片的结构的多芯片封装型半导体器件及其制造方法。 
背景技术
根据最近对高性能并且轻便、超薄以及更小电子设备的要求，发展了电子部件的高密度集成和甚高密度安装，并且在前述电子设备中使用的半导体器件的尺寸减小同样比以往任何时候发展都快。 
作为制造如LSI单元或者IC模块的半导体器件的方法，如图10中所示，存在一种制造通过如下方式获得的叠层MCP（多芯片封装）的方法：首先使在电性能测试中被检测为无缺陷的多个半导体元件2的电路表面面向相同方向并且以各半导体元件的电极衬垫（未示出）被暴露而没有被其它半导体元件隐藏的方式在支撑基板43上层叠这样的半导体元件2，通过线接合46电连接半导体元件的电极衬垫和支撑基板43，其后，用密封树脂55密封产品，形成焊料球56作为外部连接端子，并且单独切割半导体元件以完成半导体器件（例如，参考日本专利申请No.2002-33442）。 
然而，对于如上所述获得的常规半导体器件，因为使用线接合用于连接，所以半导体元件仅有一侧或者两侧可以与支撑基板电连接，所以存在仅两个半导体元件可以同时操作的限制。 
另外，存在减薄层叠多个半导体元件的封装的要求，而且为了满足此要求，减少每个半导体元件的厚度并且安装这样的薄半导体元件并且减少如线接合的连接构件的高度是必须的。 
然而，连接到半导体元件的线接合的连接需要在安装的半导体元件上 经过，而如果连接构件的高度很低，其将与半导体元件连接引起短路。 
因此，为了防止除半导体元件的电极以外的部分与线接合接触，如图11所示，在半导体元件2的电极形成部分或者侧面或者背面的一部分上形成作为保护树脂层的绝缘材料层34以防止短路（例如，参考日本专利申请No.2009-49118）. 
当同时操作多于两个半导体元件时，需要层叠半导体元件以便直接连接要操作的两个半导体元件以用于与两个半导体元件的同时操作。因此，半导体器件的尺寸变大，并且源于层叠结构的差的热辐射，在半导体元件中的结的温度升高，因此导致不可能进行前述同时操作的问题。 
最近的趋势，要求半导体封装尺寸下降和可安装的半导体元件数量增加。为了满足这些要求，下列方面被提议并且发展；即，具有POP（层叠封装）结构的半导体器件，其中另一个半导体封装或者电路板层叠在半导体封装上（日本专利发明No.2008-218505）以及具有TSV（硅通孔）结构的半导体器件（日本专利发明No.2010-278334）。 
现在基于图8解释常规POP结构半导体器件。POP（层叠封装）是一种封装模式其中多个不同LSI被作为独立封装组装，被测试并且随后层叠封装。 
通过层叠在半导体封装41上的另一个半导体封装42配置半导体器件40。在下半导体封装41的基板43上安装半导体元件44，并且在半导体元件44的周边处形成电极衬垫（未示出）和基板上的电极衬垫45通过线46电连接。用密封构件47密封半导体元件44的整个表面。另外，半导体封装41和半导体封装42通过在半导体封装42的下表面上形成的外部连接端子48（焊料球）基于回流互相电连接。 
POP的优点是作为层叠多个上述封装的结果安装区域可以在安装器件上增加，并且因为每个封装可以独立测试，可以减少成品率损耗。然而，用POP，因为独立封装是独立组装并且完成的封装被层叠，所以难以基于半导体元件的尺寸的减小（缩小）减少组装成本，并且存在叠层模块的组装成本很昂贵的问题。 
现在参考图9解释常规TSV结构半导体器件。如图9所示，半导体器件50具有一种结构，其中多个半导体元件51具有彼此相同的功能和结构并且使用相同制造掩模分别制备以及通过树脂层53层叠在插入基板52上。每个半导体元件51都是使用硅基板的半导体元件并且都通过垂直于硅基板的多个贯穿电极（TSV：硅通孔）54电连接到上和下邻接半导体元件并且用密封树脂55密封。同时，插入基板52是由树脂制造的电路板并且在其背面形成多个外部连接端子（焊料球）56。 
对于常规TSV（硅通孔）叠层模块结构，因为向每个独立的半导体元件提供通孔所以存在半导体元件损坏的可能性，并且其还需要增加几个在通孔中形成过孔电极的复杂并且成本高的晶片工艺。因此，这导致整个垂直叠层模块的成本的明显增加。另外，对于常规结构，层叠并且安装不同尺寸的芯片很困难并且源于如在存储器件中的在相同芯片的层叠之后所必须的“用于每个层的不同重布线层的增加”，与普通存储器件模块相比制造成本增加明显，并且存在不能通过大规模制造减少成本的问题。 
发明内容
本发明的一个目标是提供一种半导体器件及其制造方法，其可以获得更小并且更薄的半导体器件并且通过使得多个半导体芯片成为垂直层叠结构明显减少了制造步骤的数目。 
为了获得前述目标，本发明的发明人通过发现前述目标可以通过下述配置实现而完成了本发明；即，通过采用作为单元结构部件的结构，该结构包括半导体元件，用于密封所述半导体元件及其周边的绝缘材料层，在所述绝缘材料层中提供的金属薄膜布线层，金属薄膜布线层的一部分暴露在外表面上；以及在所述绝缘材料层中提供并电连接到所述金属薄膜布线层的金属过孔，其中提供多个所述半导体元件，并且各半导体元件通过绝缘材料层叠以便每个半导体元件的电路表面面向所述金属薄膜布线层，以及其中每个半导体元件的电极衬垫被暴露而没有被层叠在其上的所述半导体元件隐藏，并电连接到所述金属薄膜布线层。 
换句话说，本发明如下所述： 
（1）一种半导体器件，包括； 
半导体元件； 
支撑基板； 
绝缘材料层，用于密封所述半导体元件及其周边； 
金属薄膜布线层，被提供在所述绝缘材料层中，所述金属薄膜布线层的一部分在外表面上暴露；以及 
金属过孔，被提供在所述绝缘材料层中并电连接到所述金属薄膜布线层，其中 
提供多个所述半导体元件，并且各半导体元件通过绝缘材料层叠以便每个半导体元件的电路表面面向所述金属薄膜布线层，以及 
每个半导体元件的电极衬垫被暴露而没有被层叠在其上的所述半导体元件隐藏，并电连接到所述金属薄膜布线层。 
（2）一种半导体器件，包括多个层叠在支撑基板上的单元结构部件，每个单元结构部件包括： 
半导体元件； 
绝缘材料层，用于密封所述半导体元件及其周边； 
金属薄膜布线层，被提供在所述绝缘材料层中，所述金属薄膜布线层的一部分在外表面上暴露；以及 
金属过孔，被提供在所述绝缘材料层中并电连接到所述金属薄膜布线层，其中 
提供多个所述半导体元件，并且各半导体元件被层叠为每个半导体元件的电路表面面向所述金属薄膜布线层，以及 
每个半导体元件的电极衬垫被暴露而没有被层叠在其上的所述半导体元件隐藏，并电连接到所述金属薄膜布线层。 
其中各所述单元结构部件通过所述金属过孔电连接。 
（3）根据上述（1）或（2）的半导体器件，其中由各自不同的绝缘材料构成的多个绝缘材料层形成所述绝缘材料层。 
（4）根据上述（1）到（3）的任意一个的半导体器件，其中由光敏绝缘树脂层和非光敏绝缘树脂层形成所述绝缘材料层。 
（5）根据上述（1）到（4）的任意一个的半导体器件，其中所述支撑基板由金属材料构成，以及所述支撑基板连接到GND。 
（6）根据上述（1）到（4）的任意一个的半导体器件，其中所述支撑基板由有机材料构成或者由有机材料和金属导体构成。 
（7）根据上述（6）的半导体器件，其中其它半导体封装或者电子部件通过所述支撑基板层叠，并且所述半导体器件通过向所述支撑基板提供的通孔而电连接到所述其它半导体封装或者电子部件。 
（8）一种制造根据上述（1）的半导体器件的方法，包括如下步骤： 
在支撑基板上层叠并固定多个半导体元件以便所述半导体元件的电路表面面向同一方向，并且每个半导体元件的电极衬垫被暴露而没有被其它半导体元件隐藏； 
形成第一绝缘材料层以密封所述半导体元件及其周边； 
在所述第一绝缘材料层中形成用于形成金属过孔的开口和用于电连接所述电极衬垫的开口； 
在所述第一绝缘材料层表面上形成金属薄膜种子层； 
在所述开口中填充导电材料，并且在所述金属薄膜种子层上的预定区域形成金属薄膜布线层； 
去除在所述第一绝缘材料层表面上的除了形成所述金属薄膜布线层的区域之外的所述金属薄膜种子层；以及 
在其上具有所述金属薄膜布线层的所述第一绝缘材料层上形成第二绝缘材料层。 
（9）一种制造根据上述（2）的半导体器件的方法，包括如下步骤： 
在支撑基板上层叠并固定多个半导体元件以便所述半导体元件的电路表面面向同一方向，并且每个半导体元件的电极衬垫被暴露而没有被其它半导体元件隐藏； 
形成第一绝缘材料层以密封所述半导体元件及其周边； 
在所述第一绝缘材料层中形成用于形成金属过孔的开口和用于电连接所述电极衬垫的开口； 
在所述第一绝缘材料层表面上形成金属薄膜种子层； 
在所述开口中填充导电材料，并且在所述金属薄膜种子层上的预定区域形成金属薄膜布线层； 
去除在所述第一绝缘材料层表面上的除了形成所述金属薄膜布线层的区域之外的所述金属薄膜种子层；以及 
在其上形成有所述金属薄膜布线层的所述第一绝缘材料层上形成第二绝缘材料层，从而将半导体元件层叠体制造为单元结构部件；以及 
通过重复前述步骤序列，在所述第二绝缘材料层上安装多个所述单元结构部件， 
其中各所述单元结构部件通过所述金属过孔电连接。 
本发明的半导体器件产生如下效果。 
在多芯片封装的制造方法中可以减少布线层形成步骤的数量。能够实现与通过再布线技术层叠的半导体元件的电连接。金属支撑基板和有机支撑基本两者都可以用作支撑基板。 
附图说明
图1示出了根据本发明的半导体器件的实施例1。 
图2A和2B的每一个都示出了层叠半导体元件时的层叠实例。 
图3A到3O示出了制造实施例1的半导体器件的方法步骤。 
图4示出了本发明的半导体器件的实施例2。 
图5示出了本发明的半导体器件的实施例3。 
图6示出了作为参考实例的半导体器件的实例的截面图。 
图7A到7N示出了在图6中示出的半导体器件的制造方法的步骤。 
图8示出了常规POP结构半导体器件的结构图。 
图9示出了常规TSV结构半导体器件的结构图。 
图10示出了作为常规LSI单元或者IC模块的半导体器件的结构图。 
图11示出了常规半导体元件中用于防止短路的结构图 
具体实施方式
当完成本发明时，本发明的发明人检测了成为本发明的原型的半导体器件及其制造方法。通过与原型半导体器件及其制造方法的比较本发明的特征将更明显，此原型半导体器件（下文指“半导体器件D”）下文中作为参考实例并且首先说明。 
图6示出了半导体器件D的结构图。通过层叠多个单元结构部件构成此半导体器件D，其中每个单元结构部件都配置有半导体元件2、用于密封半导体元件2及其周边的绝缘材料层4、在绝缘材料层4中提供的金属薄膜布线层6以及在绝缘材料层4中提供并且与金属薄膜布线层6电连接的过孔9，其中示出的结构配置有层叠的八个半导体元件。 
现在参考图7A到7N解释此半导体器件D的制造方法。图7A到7N分别示出了半导体器件D的制造方法的步骤（a）到（c）、（e）、（g）到（j）、（l）、（n）、（p）到（s），并且下面解释各步骤。 
（a）在支撑基板上安装半导体元件的步骤 
在电性能测试中被确定为无缺陷的半导体元件2被通过粘合剂固定在支撑基板1上，半导体元件2的电路表面面向上。 
（b）绝缘材料层形成步骤 
在固定在支撑基板上的半导体元件2的周围施加绝缘树脂以形成绝缘材料层4（绝缘材料层a）。 
（c）在绝缘材料层中形成开口的步骤 
在电极衬垫3上的绝缘材料层中形成开口5用于使半导体元件2的电极衬垫从绝缘材料层4暴露。 
（d）金属薄膜种子层形成步骤（未示出） 
通过气相沉积方法（溅射）、无电镀或者类似的方法在具有开口5的绝缘材料层4的整个上表面上形成金属薄膜种子层（底层）。 
（e）金属薄膜布线层形成步骤 
为了在其上形成种子层的绝缘材料层4的预定区域上形成金属薄膜布线层，形成抗镀剂并且通过电解镀敷在绝缘材料层4的通过构图去除抗镀剂的区域上形成导电金属薄膜布线层。用导电金属填充开口5。 
（f）金属薄膜种子层去除步骤（未示出） 
在形成金属薄膜布线层6之后，通过蚀刻去除没有形成布线层的区域的抗镀剂和在抗镀剂下的种子层（底层）。 
（g）绝缘材料层形成步骤 
在其上具有形成的金属薄膜布线层6的绝缘材料层4的表面上形成绝缘材料层7（绝缘材料层b）。 
（h）在绝缘材料层上安装半导体元件的步骤 
在电性能测试中被检测为无缺陷的半导体元件2被通过粘合剂固定在绝缘材料层7上（绝缘材料层b），其中半导体元件2的电路表面面向上以便在绝缘材料层7上安装半导体元件2。 
（i）绝缘材料层形成步骤 
在绝缘材料层7上固定的半导体元件2的周围提供绝缘树脂以形成绝缘材料层4（绝缘材料层a），从而树脂密封半导体元件2。 
（j）在绝缘材料层中形成开口的步骤 
在绝缘材料层4上形成用于形成过孔的开口8和用于暴露半导体元件2的电极衬垫的开口5。 
（k）金属薄膜种子层形成步骤（未示出） 
通过气相沉积方法（溅射）、无电镀或者类似的方法在具有开口5和开口8的绝缘材料层4的整个上表面上形成金属薄膜种子层（底层）。 
（l）金属薄膜布线层形成步骤 
为了具有在其上形成的种子层的绝缘材料层4的预定区域上形成金属薄膜布线层，形成抗镀剂并且通过电解镀敷在绝缘材料层4的通过构图去除抗镀剂的区域上形成金属薄膜布线层。用导电金属填充开口5和开口8。 
（m）金属薄膜种子层去除步骤（未示出） 
在形成金属薄膜布线层6之后，通过蚀刻去除没有形成布线层的区域 的抗镀剂和在抗镀剂之下的种子层（底层）。 
（n）绝缘材料层形成步骤 
在具有在其上形成的金属薄膜布线层6的绝缘材料层4的表面上形成绝缘材料层7（绝缘材料层b）。 
（o）重复步骤 
重复六次前述步骤（h）到（n）。从而可能获得图6中示出的结构，其中层叠了8个半导体元件 
（p）抗蚀剂层形成步骤 
为了保护布线，在金属薄膜布线层的表面上形成如阻焊剂的布线保护膜（抗蚀剂层）10。当阻焊剂是液态形式时用辊涂机提供阻焊剂并且当阻焊剂具有薄膜形状时用层积或者接合提供阻焊剂。 
（q）布线保护膜（抗蚀剂层）开口步骤 
为了将半导体器件与半导体封装或者电子部件电连接，在布线保护膜中形成用于向对应于过孔9的预定位置提供外部金属电极的抗蚀剂开口11。 
（r）端子镀敷步骤 
在抗蚀剂开口11上形成用于提供外部金属电极的端子镀层12或者有机保护膜。 
（s）外部金属电极形成步骤 
在端子镀层上形成由导电金属制造的外部金属电极（在示出的实例中的焊料球13）。作为导电材料，可以使用如焊料球、导电浆糊、焊膏等等。 
如上述获得的半导体器件（多芯片封装）被分成独立的片段，从而完成半导体器件。 
前述制造方法具有一个问题，其中需要为每个半导体元件形成一个金属薄膜布线层，从而增加了步骤数量。 
因此，作为将多个半导体元件电连接到一个金属薄膜布线层的结构的结果，本发明使得半导体器件的制造步骤简化并且缩小了半导体器件的尺寸。 
下面参考实施例解释该半导体器件。 
实施例1 
图1示出了本发明的实施例1的半导体器件A的结构图。 
如图所示，此半导体器件A包括半导体元件2a，2b，用于密封半导体元件2a，2b及其周边的绝缘材料层4、在绝缘材料层4中提供并且其中其一部分暴露于外表面上的金属薄膜布线层6以及在绝缘材料层中提供并且与金属薄膜布线层电连接的金属过孔9。标号1表示金属支撑基板。 
另外，两个半导体元件2a，2b是层叠的并且向绝缘材料层4提供，并且这样的结构为向两个半导体元件提供一个金属薄膜布线层6。 
通过绝缘材料层叠两个半导体元件2a，2b，半导体元件2a，2b的电路表面面向金属薄膜布线层6并且暴露各半导体元件2a，2b的电极衬垫以便下半导体的衬垫不被层叠在其上的半导体元件隐藏并电连接到金属薄膜布线层。 
当两个半导体元件2a，2b层叠时，为了使得下半导体元件的电极衬垫暴露而不被上半导体元件隐藏，例如，如图2A中所示，存在一种方法将相同尺寸的半导体芯片的方向相反并且层叠半导体元件以便暴露下半导体元件的电极衬垫，或者，如图2B中所示，使用不同尺寸的半导体元件并且层叠半导体元件以便暴露下半导体元件的电极衬垫。 
现在参考分别示出了下述步骤（A）到（C）、（E）、（G）到（K）、（M）、（O）、（Q）到（T）的图3A到3O详细解释实施例1的半导体器件A的制造步骤。 
（A）在金属支撑基板上安装半导体元件的步骤 
在电性能测试中被检测为无缺陷的第一半导体元件2a被通过粘合剂固定在支撑基板1上，第一半导体元件的电路表面面向上。另外，通过粘合剂将第二半导体元件2b固定在第一半导体元件上，其中第二半导体元件的电路表面面向上以便暴露第一半导体元件的电极衬垫。参考标号14是管芯附着。 
（B）绝缘材料层形成步骤 
在固定在金属支撑基板1上的半导体元件2a和2b的周围提供绝缘树脂以形成绝缘材料层4（绝缘材料层a）。热固树脂用作绝缘树脂但是还可以使用光敏树脂。 
热固树脂可以用作半导体元件周围的绝缘材料层并且光敏树脂层可以用作其上面的层。因此，可以期望通过热固树脂层的半导体元件的密封可靠性增强效果以及通过光敏树脂层的构图特性增强效果。 
（C）在绝缘材料层中形成开口的步骤 
在电极衬垫3上的绝缘材料层中形成开口5用于导致半导体元件2a和2b的电极衬垫从绝缘材料层4暴露，并且在绝缘材料层4中还形成用于形成过孔的开口8。 
可以通过激光束加工形成开口5,8。另外，还可以通过微孔钻形成开口5,8或者当由光敏树脂制造绝缘材料层时，还可以通过曝光和显影形成开口5,8。另外，可以使用多个处理方式的组合。 
（D）金属薄膜种子层形成步骤（未示出） 
通过气相沉积方法（溅射）、无电度等等在具有开口5，8的绝缘材料层4的整个上表面上形成金属薄膜种子层（底层）。 
（E）过孔填充和金属薄膜布线层形成步骤 
为了在其上形成有种子层的绝缘材料层4的上表面上形成布线层，形成抗镀剂并且通过电解镀敷在绝缘材料层4的通过构图去除抗镀剂的区域上形成导电金属薄膜布线层并且用导电金属填充开口5，8。通过填充有导电材料的开口8形成过孔9。 
（F）金属薄膜种子层去除步骤（未示出） 
在形成金属薄膜布线层6之后，通过蚀刻去除没有形成布线层的区域的抗镀剂并且通过蚀刻去除在抗镀剂下的种子层（底层）。 
（G）绝缘材料层形成步骤 
在其上形成有金属薄膜布线层6的绝缘材料层4的表面上形成绝缘材料层7（绝缘材料层b）。 
（H）在绝缘材料层中形成开口的步骤 
在绝缘材料层7中形成位于过孔9之上的开口8，用于确保过孔9的电连接。 
（I）在绝缘材料层上安装半导体元件的步骤 
通过粘合剂将半导体元件2a和2b固定在绝缘材料层7上（绝缘材料层b），其中半导体元件的电路表面面向上以便在绝缘材料层7上安装半导体元件2a和2b。 
（J）绝缘材料层形成步骤 
在绝缘材料层7上固定的半导体元件2a和2b的周围提供绝缘树脂以形成绝缘材料层4（绝缘材料层a），从而树脂密封半导体元件2a和2b。关于绝缘树脂的详细描述如在前述步骤（B）中所述。 
（K）在绝缘材料层中形成开口的步骤 
对于绝缘材料层7，在绝缘材料层4中形成用于形成过孔的开口8和用于暴露半导体元件2a和2b的电极衬垫的开口5。处理方法如前述步骤（C）中所述 
（L）金属薄膜种子层形成步骤（未示出） 
通过气相沉积方法（溅射）、无电度等等在其中形成有开口5和开口8的绝缘材料层4的整个上表面上形成金属薄膜种子层（底层）。 
（M）金属薄膜布线层形成步骤 
为了在其上形成有种子层的绝缘材料层4的上表面上形成布线层，形成抗镀剂并且通过电解镀敷在绝缘材料层4的通过构图去除抗镀剂的区域上形成金属薄膜布线层6。另外，用导电金属填充开口8，从而形成过孔9并且用导电金属填充开口5。 
（N）种子层去除步骤（未示出） 
在形成金属薄膜布线层6之后，通过蚀刻去除没有形成布线层的区域的抗镀剂和该区域处的在抗镀剂之下的种子层（底层）。 
（O）绝缘材料层形成步骤 
在其上形成有金属薄膜布线层6的绝缘材料层4的表面上形成绝缘材料层7（绝缘材料层b）。 
（P）重复步骤 
重复两次前述步骤（H）到（O）。从而可能获得图1中示出的结构，其中层叠了8个半导体元件。 
（Q）布线保护膜（抗蚀剂层）形成步骤 
为了保护布线，在金属薄膜布线层的表面上形成如阻焊剂的布线保护膜（抗蚀剂层）10。当阻焊剂是液态形式时用辊涂机（roll coater）提供阻焊剂并且当阻焊剂具有薄膜形状时用层积或者接合提供阻焊剂。 
（R）抗蚀剂层开口步骤 
为了将半导体器件与半导体封装或者电子部件电连接，形成用于向对应于过孔9的预定位置提供外部金属电极的抗蚀剂开口11。 
（S）端子镀敷步骤 
在抗蚀剂开口11上形成用于提供外部金属电极的端子镀层12或者有机保护膜。 
（T）外部金属电极形成步骤 
在端子镀层上形成由导电材料制造的外部金属电极13（在示出的实例中的焊料球13）。作为导电材料，可以使用如焊料球、导电浆糊、焊膏等等。 
通常，在大面积支撑基板的垂直方向和水平方向上同时形成多个半导体器件。这样，在形成外部电极13之后，获得的多芯片封装被分成独立的片段，从而完成半导体器件。 
虽然图1中示出的半导体A是层叠了八个半导体元件的结构，作为重复步骤（H）到（O）的结果，可以制造一种半导体器件其中层叠了多于八个的半导体元件。在上述半导体器件A的情况下，在每个层叠体中使用的半导体元件作为单元结构部件都用相同的参考标号2a，2b表示以为了简化，这不总是意味着在所有单元结构部件中都使用相同的半导体。在各单元结构部件中可以使用不同的半导体元件。 
实施例2 
实施例2的半导体器件B使用有机支撑基板1’替代实施例1的半导体 器件A中的金属支撑基板，如图4所示。 
虽然金属支撑基板就散热性能有优势并且能够连接到GND，但是存在可加工性能差和难以打孔的缺点并且很难提供绝缘性。因此，很难在金属支撑基板上安装其它半导体封装或者电子部件。 
同时，由如玻璃增强环氧树脂的有机化合物材料制造的有机支撑基板与金属支撑基板相比就如打孔的可加工性而言是有利的，并且具有绝缘性能。因此，如图4所示，作为开通孔并提供电连接部分的结果，在半导体器件上安装如半导体封装或者电容器的钝化部件是可能的。 
实施例3 
对于图5中示出的实施例3的半导体器件C，向焊料球13安装侧提供在实施例2中使用的有机支撑基板1’。 
如在使用线用于布线的情况中，此结构能够获得面向上结构（半导体元件电路表面面向安装面），并且容易获得与实施例2中相同的端子设置。 
另外，还存在一个优点，即，下侧与主板是匹配的，因为其为有机支撑基板。 
标号说明： 
1,1’：支撑基板 
2,2a，2b：半导体元件 
3：电极衬垫 
4：绝缘材料层 
5：开口 
6：金属薄膜布线层 
7：绝缘材料层 
8：开口 
9：过孔 
10：抗蚀剂层 
11：抗蚀剂开口 
12：端子镀层或者有机保护膜13：焊料球 
14：管芯附着 
40,50：半导体器件 
34：绝缘材料层 
36：过孔部分 
37：焊料球 
38：焊料树脂层 
41,42：半导体封装 
43：支撑基板 
45：电极衬垫 
46：线 
47：密封构件 
48：外部连接端子 
50：半导体器件 
51：半导体元件 
52：插入基板 
53：树脂层 
54：TSV（硅通孔） 
55：密封树脂 
56：外部连接端子（焊料球） 

Claims (9)

1.一种半导体器件，包括；
半导体元件；
支撑基板；
绝缘材料层，用于密封所述半导体元件及其周边；
金属薄膜布线层，被提供在所述绝缘材料层中，所述金属薄膜布线层的一部分在外表面上暴露；以及
金属过孔，被提供在所述绝缘材料层中并电连接到所述金属薄膜布线层，其中
提供多个所述半导体元件，并且各半导体元件通过绝缘材料层叠以便每个半导体元件的电路表面面向所述金属薄膜布线层，以及
每个半导体元件的电极衬垫被暴露而没有被层叠在其上的所述半导体元件隐藏，并电连接到所述金属薄膜布线层。
2.一种半导体器件，包括多个层叠在支撑基板上的单元结构部件，每个单元结构部件包括：
半导体元件；
绝缘材料层，用于密封所述半导体元件及其周边；
金属薄膜布线层，被提供在所述绝缘材料层中，所述金属薄膜布线层的一部分在外表面上暴露；以及
金属过孔，被提供在所述绝缘材料层中并电连接到所述金属薄膜布线层，其中
提供多个所述半导体元件，并且各半导体元件被层叠为每个半导体元件的电路表面面向所述金属薄膜布线层，以及
每个半导体元件的电极衬垫被暴露而没有被层叠在其上的所述半导体元件隐藏，并电连接到所述金属薄膜布线层。
其中各所述单元结构部件通过所述金属过孔电连接。
3.根据权利要求1或2的半导体器件，其中由各自不同的绝缘材料构成的多个绝缘材料层形成所述绝缘材料层。
4.根据权利要求1到3的任意一个的半导体器件，其中由光敏绝缘树脂层和非光敏绝缘树脂层形成所述绝缘材料层。
5.根据权利要求1到4的任意一个的半导体器件，其中所述支撑基板由金属材料构成，以及所述支撑基板连接到GND。
6.根据权利要求1到4的任意一个的半导体器件，其中所述支撑基板由有机材料构成或者由有机材料和金属导体构成。
7.根据权利要求6的半导体器件，其中其它半导体封装或者电子部件通过所述支撑基板层叠，并且所述半导体器件通过向所述支撑基板提供的通孔而电连接到所述其它半导体封装或者电子部件。
8.一种制造根据权利要求1的半导体器件的方法，包括如下步骤：
在支撑基板上层叠并固定多个半导体元件以便所述半导体元件的电路表面面向同一方向，并且每个半导体元件的电极衬垫被暴露而没有被其它半导体元件隐藏；
形成第一绝缘材料层以密封所述半导体元件及其周边；
在所述第一绝缘材料层中形成用于形成金属过孔的开口和用于电连接所述电极衬垫的开口；
在所述第一绝缘材料层表面上形成金属薄膜种子层；
在所述开口中填充导电材料，并且在所述金属薄膜种子层上的预定区域形成金属薄膜布线层；
去除在所述第一绝缘材料层表面上的除了形成所述金属薄膜布线层的区域之外的所述金属薄膜种子层；以及
在其上具有所述金属薄膜布线层的所述第一绝缘材料层上形成第二绝缘材料层。
9.一种制造根据权利要求2的半导体器件的方法，包括如下步骤：
在支撑基板上层叠并固定多个半导体元件以便所述半导体元件的电路表面面向同一方向，并且每个半导体元件的电极衬垫被暴露而没有被其它半导体元件隐藏；
形成第一绝缘材料层以密封所述半导体元件及其周边；
在所述第一绝缘材料层中形成用于形成金属过孔的开口和用于电连接所述电极衬垫的开口；
在所述第一绝缘材料层表面上形成金属薄膜种子层；
在所述开口中填充导电材料，并且在所述金属薄膜种子层上的预定区域形成金属薄膜布线层；
去除在所述第一绝缘材料层表面上的除了形成所述金属薄膜布线层的区域之外的所述金属薄膜种子层；以及
在其上形成有所述金属薄膜布线层的所述第一绝缘材料层上形成第二绝缘材料层，从而将半导体元件层叠体制造为单元结构部件；以及
通过重复前述步骤序列，在所述第二绝缘材料层上安装多个所述单元结构部件，
其中各所述单元结构部件通过所述金属过孔电连接。
CN201210397451.4A 2012-02-08 2012-10-18 半导体器件及其制造方法 Active CN103247599B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP025042/2012 2012-02-08
JP2012025042A JP5912616B2 (ja) 2012-02-08 2012-02-08 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
CN103247599A true CN103247599A (zh) 2013-08-14
CN103247599B CN103247599B (zh) 2017-07-21

Family

ID=47221945

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210397451.4A Active CN103247599B (zh) 2012-02-08 2012-10-18 半导体器件及其制造方法

Country Status (6)

Country Link
US (1) US8872350B2 (zh)
EP (1) EP2634796B1 (zh)
JP (1) JP5912616B2 (zh)
KR (1) KR101653856B1 (zh)
CN (1) CN103247599B (zh)
TW (1) TWI557868B (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517934A (zh) * 2013-09-27 2015-04-15 英特尔公司 用于互连堆叠的半导体器件的方法
TWI507907B (zh) * 2014-08-29 2015-11-11 Taiwan Semiconductor Mfg Co Ltd 半導體裝置及其設計方法
CN105702637A (zh) * 2014-12-11 2016-06-22 株式会社吉帝伟士 半导体封装件及其制造方法
CN109075761A (zh) * 2016-09-16 2018-12-21 株式会社大真空 压电振动器件
CN111683471A (zh) * 2019-03-11 2020-09-18 株式会社村田制作所 多层布线基板
CN112968012A (zh) * 2021-02-01 2021-06-15 长江存储科技有限责任公司 扇出型芯片堆叠封装结构及其制造方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014082245A (ja) 2012-10-15 2014-05-08 J Devices:Kk 半導体記憶装置及びその製造方法
JP6377894B2 (ja) * 2013-09-03 2018-08-22 信越化学工業株式会社 半導体装置の製造方法、積層型半導体装置の製造方法、及び封止後積層型半導体装置の製造方法
JP6961885B2 (ja) * 2013-09-27 2021-11-05 インテル・コーポレーション 半導体組立体及び半導体組立体の製造方法
WO2015042886A1 (en) 2013-09-27 2015-04-02 Intel Corporation Method for interconnecting stacked semiconductor devices
JP6331452B2 (ja) * 2014-02-19 2018-05-30 愛知製鋼株式会社 有機膜のエッチング方法
KR102186150B1 (ko) * 2014-07-29 2020-12-03 삼성전기주식회사 절연 필름을 이용한 인쇄회로기판 및 그 제조 방법
US9609749B2 (en) 2014-11-14 2017-03-28 Mediatek Inc. Printed circuit board having power/ground ball pad array
US10455708B2 (en) 2015-06-29 2019-10-22 Samsung Electro-Mechanics Co., Ltd. Multilayered substrate and method for manufacturing the same
US9832866B2 (en) * 2015-06-29 2017-11-28 Samsung Electro-Mechanics Co., Ltd. Multilayered substrate and method of manufacturing the same
KR102564324B1 (ko) 2018-10-15 2023-08-07 삼성전자주식회사 반도체 메모리 장치 및 이의 제조 방법
KR102302563B1 (ko) 2019-12-05 2021-09-15 고려대학교 산학협력단 비아 형성 방법, 이를 기반으로 하는 반도체 장치의 제조 방법 및 반도체 장치
US11211310B1 (en) * 2020-09-03 2021-12-28 Delta Electronics, Inc. Package structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050046002A1 (en) * 2003-08-26 2005-03-03 Kang-Wook Lee Chip stack package and manufacturing method thereof
CN1625805A (zh) * 2002-02-06 2005-06-08 揖斐电株式会社 半导体芯片安装用基板及其制造方法和半导体模块
US20090134528A1 (en) * 2007-11-28 2009-05-28 Samsung Electronics Co, Ltd. Semiconductor package, electronic device including the semiconductor package, and method of manufacturing the semiconductor package
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068714A (en) * 1989-04-05 1991-11-26 Robert Bosch Gmbh Method of electrically and mechanically connecting a semiconductor to a substrate using an electrically conductive tacky adhesive and the device so made
US5032896A (en) * 1989-08-31 1991-07-16 Hughes Aircraft Company 3-D integrated circuit assembly employing discrete chips
JP3818359B2 (ja) 2000-07-18 2006-09-06 セイコーエプソン株式会社 半導体装置、回路基板及び電子機器
EP2866258B1 (en) * 2002-05-31 2019-04-17 Socionext Inc. Semiconductor device and manufacturing method thereof
JP3801158B2 (ja) * 2002-11-19 2006-07-26 セイコーエプソン株式会社 多層配線基板の製造方法、多層配線基板、電子デバイス及び電子機器
TWI222734B (en) * 2003-10-03 2004-10-21 Thin Film Module Inc High density module card, substrate and fabrication for the same
JP4340517B2 (ja) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
JP4403407B2 (ja) * 2005-02-03 2010-01-27 ソニー株式会社 半導体装置およびその製造方法
JP4507101B2 (ja) * 2005-06-30 2010-07-21 エルピーダメモリ株式会社 半導体記憶装置及びその製造方法
JP4843515B2 (ja) * 2007-02-01 2011-12-21 パナソニック株式会社 半導体チップの積層構造
JP5135828B2 (ja) 2007-02-28 2013-02-06 ソニー株式会社 基板およびその製造方法、半導体パッケージおよびその製造方法、並びに半導体装置およびその製造方法
JP5143451B2 (ja) * 2007-03-15 2013-02-13 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
KR100845006B1 (ko) * 2007-03-19 2008-07-09 삼성전자주식회사 적층 칩 패키지 및 그 제조 방법
JP4496241B2 (ja) 2007-08-17 2010-07-07 株式会社東芝 半導体素子とそれを用いた半導体パッケージ
JP4538058B2 (ja) * 2008-03-28 2010-09-08 株式会社東芝 集積半導体装置及び集積３次元半導体装置
JP2010278334A (ja) 2009-05-29 2010-12-09 Elpida Memory Inc 半導体装置
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
JP2010232702A (ja) * 2010-07-20 2010-10-14 Toshiba Corp 積層型半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1625805A (zh) * 2002-02-06 2005-06-08 揖斐电株式会社 半导体芯片安装用基板及其制造方法和半导体模块
US20050046002A1 (en) * 2003-08-26 2005-03-03 Kang-Wook Lee Chip stack package and manufacturing method thereof
US20090134528A1 (en) * 2007-11-28 2009-05-28 Samsung Electronics Co, Ltd. Semiconductor package, electronic device including the semiconductor package, and method of manufacturing the semiconductor package
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517934A (zh) * 2013-09-27 2015-04-15 英特尔公司 用于互连堆叠的半导体器件的方法
TWI507907B (zh) * 2014-08-29 2015-11-11 Taiwan Semiconductor Mfg Co Ltd 半導體裝置及其設計方法
US9984191B2 (en) 2014-08-29 2018-05-29 Taiwan Semiconductor Manufacturing Company Cell layout and structure
US10664639B2 (en) 2014-08-29 2020-05-26 Taiwan Semiconductor Manufacturing Company Cell layout and structure
US11281835B2 (en) 2014-08-29 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Cell layout and structure
CN105702637A (zh) * 2014-12-11 2016-06-22 株式会社吉帝伟士 半导体封装件及其制造方法
CN109075761A (zh) * 2016-09-16 2018-12-21 株式会社大真空 压电振动器件
CN111683471A (zh) * 2019-03-11 2020-09-18 株式会社村田制作所 多层布线基板
CN111683471B (zh) * 2019-03-11 2023-11-21 株式会社村田制作所 多层布线基板
CN112968012A (zh) * 2021-02-01 2021-06-15 长江存储科技有限责任公司 扇出型芯片堆叠封装结构及其制造方法
CN112968012B (zh) * 2021-02-01 2022-09-09 长江存储科技有限责任公司 扇出型芯片堆叠封装结构及其制造方法

Also Published As

Publication number Publication date
TWI557868B (zh) 2016-11-11
JP2013162071A (ja) 2013-08-19
US20130200523A1 (en) 2013-08-08
EP2634796B1 (en) 2020-04-08
EP2634796A3 (en) 2015-03-25
US8872350B2 (en) 2014-10-28
JP5912616B2 (ja) 2016-04-27
TW201334143A (zh) 2013-08-16
EP2634796A2 (en) 2013-09-04
KR20130091624A (ko) 2013-08-19
KR101653856B1 (ko) 2016-09-02
CN103247599B (zh) 2017-07-21

Similar Documents

Publication Publication Date Title
CN103247599A (zh) 半导体器件及其制造方法
CN101515554B (zh) 半导体器件的制造方法、半导体器件以及配线基板
EP2130224B1 (en) Apparatus for packaging semiconductor devices
CN104064551B (zh) 一种芯片堆叠封装结构和电子设备
EP2551904A1 (en) Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof
US9917042B2 (en) 2.5D microelectronic assembly and method with circuit structure formed on carrier
US7884486B2 (en) Chip-stacked package structure and method for manufacturing the same
US20150249075A1 (en) Semiconductor chips having a dual-layered structure, packages having the same, and methods of fabricating the semiconductor chips and the packages
KR20090055316A (ko) 반도체 패키지와, 이를 구비하는 전자 기기 및 반도체패키지의 제조방법
CN102130025B (zh) 晶片及其处理方法和制造半导体装置的方法
US9837378B2 (en) Fan-out 3D IC integration structure without substrate and method of making the same
EP3104410B1 (en) Multi-chip module, on-board computer, sensor interface substrate, and multi-chip module manufacturing method
US20130307145A1 (en) Semiconductor package and method of fabricating the same
US9147671B2 (en) Semiconductor device, semiconductor stacked module structure, stacked module structure and method of manufacturing same
US10515883B2 (en) 3D system-level packaging methods and structures
JP4919689B2 (ja) モジュール基板
KR20130050077A (ko) 스택 패키지 및 이의 제조 방법
US20040089930A1 (en) Simplified stacked chip assemblies
TWI832703B (zh) 半導體裝置以及半導體裝置的製造方法
EP2903021A1 (en) Semiconductor device, semiconductor stacked module structure, stacked module structure and method of manufacturing same
TW202401721A (zh) 半導體裝置以及半導體裝置的製造方法
TW201530715A (zh) 半導體裝置、半導體積層模組構造、積層模組構造及此等之製造方法
TWM648920U (zh) 線路載板及電子封裝體

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Oita Prefecture

Patentee after: Rely on Technology Japan company

Address before: Oita Prefecture

Patentee before: J-DEVICES Corp.