TWI222734B - High density module card, substrate and fabrication for the same - Google Patents
High density module card, substrate and fabrication for the same Download PDFInfo
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- TWI222734B TWI222734B TW092127385A TW92127385A TWI222734B TW I222734 B TWI222734 B TW I222734B TW 092127385 A TW092127385 A TW 092127385A TW 92127385 A TW92127385 A TW 92127385A TW I222734 B TWI222734 B TW I222734B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Wire Bonding (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
1222734 JE__η 曰1222734 JE__η
案號 92127385_ 五、發明說明(1) [發明所屬之技術領域] 本發明是有關於一種模組卡(high density m()d card)、基板及其製造方法,且特別是有關於一種e 模組卡、基板及其製造方法。 n广度 [先前技術] 晶片封裝技術的發展趨勢朝向尺寸縮小及輪人/ _ 接點增加,因而覆晶(f 1 i P c h i p )技術成為主流之_輪出 晶技術主要是在晶圓上對外的接點(通常是金屬焊 。覆 長凸塊,並透過凸塊與基板(substrate)電性連接。、上成 覆晶技術可以高密度地連接輸入/輸出接點。且因運運^ 晶技術可使晶片與基板的連接路徑為最短,故 用覆 感連接。 逐立低電 習知模組基板的構成可區分為兩類:壓合 (laminated)基板及積層(bui It up)基板。以壓合 成基板時’越外層的部份由於平坦度^“卜㈣丨^)^ 所以精度控制困難,因而難以符合高密度覆晶封褒的^間 距需求。若以積層方式構成基板時,雖可做出較 =,但是基板的強度不足,無法在製程中提供足夠= 撐。 又 以此類習知的基板應用於覆晶封裝之高密度⑴ density)及微間距(fine pitch)的需求時,會造m 組卡之厚度較厚,無法符合輕薄短小的趨勢,亦或 古果 基板強度不足的問題點。 /疋會有 [發明内容]Case No. 92127385_ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a module card (high density m () d card), a substrate and a manufacturing method thereof, and in particular to an e-mode Group card, substrate and manufacturing method thereof. n breadth [previous technology] The development trend of chip packaging technology is toward shrinking size and increasing the number of contacts / _, so the flip chip (f 1 i P chip) technology has become the mainstream _ wheel chip technology is mainly on the wafer to the outside Contacts (usually metal soldering. Overlay bumps and electrically connect to the substrate through the bumps.) Chip-on-chip technology can connect input / output contacts at high density. The technology can make the connection path between the chip and the substrate the shortest, so it is connected by overlay. The structure of the conventional low-power module substrate can be divided into two types: laminated substrate and bui it up substrate. When synthesizing a substrate, the part of the outer layer is difficult to control due to the flatness ^ "卜 ㈣ 丨 ^) ^, so it is difficult to meet the ^ pitch requirements of high-density flip-chip sealing. If the substrate is constructed in a laminated manner, although It is relatively low, but the strength of the substrate is insufficient to provide sufficient support in the manufacturing process. When such conventional substrates are applied to the requirements of high density (density) and fine pitch of flip-chip packaging, they will Make m card thickness The thickness is too thick, which cannot meet the trend of thinness, thinness and shortness, or the problem of insufficient strength of the ancient fruit substrate. / 疋 有 [发明 内容]
1222734 案號 92127385 日 修正 五、發明說明(2) 為解決習知的問題點,本發明的目的之一係,提出 一種高密度模組卡、基板及其製造方法,使基板具足夠強 度,並可符合高密度、小間距的需求。 為達成上述及其他目的,本發明提出一種高密度模 組基板,包括:一金屬基板、一薄膜内連線層、一防焊層 以及一貫孔。金屬基板具有一第一表面及一第二表面,以 及一基板開口 ,位於第二表面。薄膜内連線層具有一頂面 及與之相對的一底面,以底面與金屬基板之第一表面相連 接。且薄膜内連線層具有多個介電層以及多個導線層,每 二個相鄰之導線層之間具有一介電層。基板開口暴露出部 份之底面,且暴露出之底面具有多個電性連接開口 ,暴露 出部份之導線層。防焊層覆於薄膜内連線層之頂面,具有 多個防焊開口 ,暴露出最接近頂面之部份導線層。貫孔, 位於基板開口之外的區域,貫穿各介電層,同時電性連接 各導線層及金屬基板。 本發明更提出一種高密度模組卡,如上述的模組基 板更包括:多個晶片、多個封膠結構,以及多個連接墊。 其中晶片係,分別搭載於薄膜内連線層之頂面,電性連接 至防焊層所暴露出之導線層,並搭載於基板開口所暴露出 之部份底面,電性連接至最接近底面之導線層。封膠結構 係,包覆晶片與導線層之電性連接處。連接墊係,覆於薄 膜内連線層之頂面,覆於防焊層所暴露出之部份導線層。 本發明更提出一種高密度模組卡的製造方法,包括: 提供一金屬基板,具有一第一表面及一第二表面。以薄膜1222734 Case No. 92127385 Amendment V. Description of the Invention (2) In order to solve the conventional problems, one object of the present invention is to propose a high-density module card, a substrate and a manufacturing method thereof, so that the substrate has sufficient strength, and It can meet the requirements of high density and small pitch. To achieve the above and other objectives, the present invention proposes a high-density module substrate, including: a metal substrate, a thin-film interconnect layer, a solder mask layer, and a through hole. The metal substrate has a first surface and a second surface, and a substrate opening is located on the second surface. The film interconnect layer has a top surface and a bottom surface opposite thereto, and the bottom surface is connected to the first surface of the metal substrate. In addition, the film interconnect layer has a plurality of dielectric layers and a plurality of wire layers, and a dielectric layer is provided between every two adjacent wire layers. The substrate opening exposes a part of the bottom surface, and the exposed bottom surface has a plurality of electrical connection openings, exposing a part of the wire layer. The solder mask layer covers the top surface of the film interconnect layer, and has a plurality of solder mask openings, exposing a portion of the conductor layer closest to the top surface. Through-holes, located outside the opening of the substrate, penetrate through the dielectric layers and electrically connect the lead layers and the metal substrate at the same time. The present invention further provides a high-density module card. The above-mentioned module substrate further includes a plurality of chips, a plurality of sealing structures, and a plurality of connection pads. The chip system is respectively mounted on the top surface of the thin film interconnect layer, electrically connected to the wire layer exposed by the solder resist layer, and mounted on the bottom surface of the exposed portion of the substrate opening, and electrically connected to the closest bottom surface. Of the wire layer. The sealant structure covers the electrical connection between the chip and the wire layer. The connection pad system covers the top surface of the thin film interconnect layer and covers part of the conductor layer exposed by the solder mask. The invention further provides a method for manufacturing a high-density module card, which includes: providing a metal substrate having a first surface and a second surface. Film
10391twfl.ptc 第8頁 1222734 _案號92127385_年月日 修正_ 五、發明說明(3) 沈積法形成一内連線層,覆於金屬基板之第一表面。形成 内連線的方法包括:形成一介電層,形成一導線層覆於介 電層,重覆此步驟數次,以形成内連線層。内連線層具有 一頂面及與之相對的一底面,以底面覆於金屬基板。形成 至少一基板開口 ,於金屬基板之第二表面,以暴露出内連 線層之部份底面。基板開口其中至少之一具有一晶片放置 區、一點膠區及一抽真空區。點膠區及抽真空區係與晶片 放置區域相連,並為沿晶片放置區之對角往外延伸之一對 區域。形成一防焊層,覆於内連線層之頂面。形成多個電 性連接開口 ,於防焊層及最接近底面的介電層,以暴露出 最接近頂面之部份導線層及最接近底面之部份導線層。形 成多個連接墊,覆於頂面,並覆於電性連接開口所暴露出 之部份導線層。貼附多個晶片,分別貼附於頂面,電性連 接至暴露的最接近頂面之部份導線層,並貼附於基板開口 所暴露出之部份底面,電性連接至最接近底面之部份導線 層。此些晶片中至少之一為覆晶晶片,貼附於晶片放置 區。於基板開口之點膠區進行點膠,並於抽真空區進行抽 真空,以將一底膠填入覆晶晶片與導線層之電性連接處。 將一封膠材料包覆晶片與導線層之電性連接處。 依照本發明特徵,利用金屬基板作為高密度模組卡 的基底,可提供穩定的機械強度。再利用半導體製程中的 薄膜沈積方式增層(build up),可得高平坦度的增層,因 而精度控制佳,並可達高密度、微間距的需求。因而做出 較基板支持強度夠,又可符合微間距需求的模組基板。且10391twfl.ptc Page 8 1222734 _Case No. 92127385_ Year, Month, Date, Amendment_ V. Description of the Invention (3) The deposition method forms an interconnecting layer, which covers the first surface of the metal substrate. The method of forming the interconnect includes forming a dielectric layer, forming a wire layer overlying the dielectric layer, and repeating this step several times to form the interconnect layer. The interconnecting layer has a top surface and a bottom surface opposite to the top surface layer, and the bottom surface covers the metal substrate. Forming at least one substrate opening on the second surface of the metal substrate to expose a portion of the bottom surface of the interconnect layer. At least one of the substrate openings has a wafer placement area, a glue area, and an evacuation area. The dispensing area and the evacuation area are connected to the wafer placement area and are a pair of areas extending outward along the diagonal of the wafer placement area. A solder mask is formed and covers the top surface of the interconnect layer. A plurality of electrical connection openings are formed in the solder mask and the dielectric layer closest to the bottom surface to expose a portion of the conductive layer closest to the top surface and a portion of the conductive layer closest to the bottom surface. A plurality of connection pads are formed, covering the top surface, and covering a part of the wire layer exposed by the electrical connection opening. Attach multiple chips, attach to the top surface separately, electrically connect to the exposed part of the wire layer closest to the top surface, and attach to the bottom surface of the exposed part of the substrate opening, electrically connect to the bottom surface closest Part of the wire layer. At least one of these wafers is a flip-chip wafer and is attached to the wafer placement area. Dispensing is performed in the dispensing area of the opening of the substrate, and vacuuming is performed in the evacuation area to fill a primer into the electrical connection of the chip-on-chip and the wire layer. A piece of glue material is used to cover the electrical connection between the chip and the wire layer. According to the features of the present invention, the use of a metal substrate as the base of a high-density module card can provide stable mechanical strength. The thin film deposition method used in the semiconductor manufacturing process is used for build up to obtain a high flatness. Therefore, the precision control is good, and the requirements of high density and fine pitch can be achieved. Therefore, a module substrate with sufficient support strength compared with the substrate and which can meet the requirements of micro-pitch is made. And
10391twfl.ptc 第9頁 1222734 _案號92127385_年月曰 修正_ 五、發明說明(4) 因支持強度夠,本發明可在基板的兩面形成模組,因而可 更進一步提高密度。 依照本發明特徵,在晶片放置區的對角延伸有一對 點膠區及抽真空區,貼附覆晶晶片之後的底膠製程係,在 晶片放置區的一隅進行點膠,而在相對的另一隅進行抽真 空,以此方式,可縮短填底膠的時間。又因為在基板開口 已設置了點膠區及抽真空區,可將晶片放置區最小化,而 提高封裝的可靠度。 依照本發明特徵,各導線層在對應晶片放置開口處 係呈波浪狀,在基板形變時,具有緩衝作用,因而可提高 基板之忍受應變的能力,因而提高產品之可靠度。 依照本發明特徵,利用貫孔使薄膜内連線層的導線 層和金屬基板相連接,並使金屬基板接地,可使模組卡上 的各晶片獲得極佳的電流輸送效果。 為讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂,下文特舉一較佳實施例,並配合所附圖式,作 詳細說明如下: [實施方式] [第一實施例] 請依序參考第1〜5圖,其繪示依照本發明之較佳實施 例的高密度模組卡之製程流程剖視圖。 請參考第1圖,提供一金屬基板100,具有一第一表 面100a及一第二表面100b。以薄膜沈積法形成一内連線層 114(第3圖),其係以介電層及導線層交替形成,覆於金屬10391twfl.ptc Page 9 1222734 _Case No. 92127385_ Year Month Amendment _ V. Description of the invention (4) Due to the sufficient support strength, the present invention can form modules on both sides of the substrate, thereby further increasing the density. According to the features of the present invention, a pair of dispensing areas and a vacuuming area extend diagonally from the wafer placement area, and the primer process system after attaching the wafer-on-wafer is performed in a row of the wafer placement area, and the opposite Vacuum can be applied at once, in this way, the time for filling the primer can be shortened. And because the dispensing area and the vacuum area have been set in the opening of the substrate, the chip placement area can be minimized, and the reliability of the package can be improved. According to the features of the present invention, each wire layer is wavy at the opening where the corresponding wafer is placed, and has a buffering effect when the substrate is deformed, thereby improving the ability of the substrate to withstand strain and thus improving the reliability of the product. According to the features of the present invention, the through-hole is used to connect the wire layer of the film interconnecting layer with the metal substrate and ground the metal substrate, so that each chip on the module card can obtain an excellent current transmission effect. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: [Embodiment] [First Embodiment ] Please refer to FIGS. 1 to 5 in order, which are cross-sectional views showing a process flow of a high-density module card according to a preferred embodiment of the present invention. Referring to FIG. 1, a metal substrate 100 is provided, which has a first surface 100a and a second surface 100b. An interconnect layer 114 (Fig. 3) is formed by a thin film deposition method, which is alternately formed by a dielectric layer and a wire layer, and is coated on a metal
10391twf1.ptc 第10頁 1222734 __案號92127385_年月 日 倏__ 五、發明說明(5) 基板100之第一表面,使得相鄰之兩導線層之間具有一介 電層。 如第2圖,以薄膜沈積法形成一介電層1〇1 ,覆於金 屬基板1 0 0之第一表面1 0 0 a。以積層法形成一圖案化導線 層103覆於介電層101。形成一圖案化的介電層1〇2,導線 層103。接著形成一圖案化的導線層1〇4,覆於介電層 102。在此,形成圖案化介電層的方法舉而言,包括雷射 鑽孔。形成圖案化導線層的方法舉例而言,為半加成法, 即先沈積一種子層(seed layer)(未圖示)覆於介電層上, 再形成一圖案化光阻層(未圖示)覆於此種子層上,之後, 利用電鍍的方法將導線層鍍於圖案化光阻層的圖案開口 (未圖示)中,再移除掉圖案化光阻層,並移除部份之種子 層0 值得注意的是,本發明之貫孔1 0 5之形成。利用例如 雷射開孔的方法,在介電層1 〇 1、1 〇 2中形成開口,並配合 利用上述的電鍍方法,在導線層1 〇 3、1 〇 4之間形成貫孔 1 〇 5。貝孔1 〇 5的位置需位於基板上欲形成開口以外的區 域。使貫孔105,貫穿介電層1〇2,以接觸導線層1〇3、 ,並貫穿介電層1〇1,以接觸金屬基板丨〇〇。在此,配 ^上述貫孔105的結構特徵,可再使金屬基板1〇〇連 =丄如此則可形成路徑短且寬廣的接地連線,因而,, &升晶片之電流輸送效能。 大大 如第3圖所示,繼續形成内連線114的步驟, -圖案化的介電層106,覆於導線層1〇4,接著 '成 ^ 圖10391twf1.ptc Page 10 1222734 __Case No. 92127385_ Year Month Day __ V. Description of the invention (5) The first surface of the substrate 100 has a dielectric layer between two adjacent wire layers. As shown in FIG. 2, a dielectric layer 101 is formed by a thin film deposition method and covers a first surface 100a of a metal substrate 100a. A patterned wire layer 103 is formed on the dielectric layer 101 by a lamination method. A patterned dielectric layer 102 and a wiring layer 103 are formed. Next, a patterned wiring layer 104 is formed and covered with the dielectric layer 102. Here, the method of forming the patterned dielectric layer includes, for example, laser drilling. The method for forming the patterned conductive layer is, for example, a semi-additive method, that is, a seed layer (not shown) is deposited on the dielectric layer, and then a patterned photoresist layer (not shown) is formed. (Shown) overlying the seed layer, and then plating the wire layer in the pattern opening (not shown) of the patterned photoresist layer by electroplating, and then remove the patterned photoresist layer and remove a part Seed layer 0 It is worth noting that the through holes 105 of the present invention are formed. Openings are formed in the dielectric layers 101 and 102 using a method such as laser perforation, and through-holes 105 are formed between the wiring layers 101 and 104 in conjunction with the aforementioned plating method. . The position of the beaker hole 105 needs to be located in a region other than the opening to be formed on the substrate. The through hole 105 is penetrated through the dielectric layer 102 to contact the wiring layer 103, and penetrates the dielectric layer 101 to contact the metal substrate. Here, with the structural features of the through-hole 105 described above, the metal substrate 100 can be further connected, so that a short and wide ground connection can be formed. Therefore, the current transmission efficiency of the chip is improved. Much as shown in FIG. 3, the step of forming the interconnect 114 is continued,-the patterned dielectric layer 106 is overlaid on the wire layer 104, and then 'formed'
1222734 案號 92127385 五、發明說明(6) 案化的導線層108,覆於介電層11〇,並形成一防焊層 122,覆於内連線層114之頂面114a。在此定義出内連線 11 4的頂面11 4a及與之相對的底面11 4b,以利後續的說 明。内連線層1 1 4係以底面1 1 4 b和金屬基板1 〇 〇連接。 本發明利用金屬基板作為高密度模組卡的基底,可 提供穩定的機械強度。又,本發明再利用半導體製程中的 薄膜沈積法,於金屬基板上形成内連線層,亦即,以薄膜 沈積的方式增層(build up),可得高平坦度的增層,因而 精度控制佳,並可達高密度、微間距的需求。 接著,如第4圖所示,形成至少一基板開口丨丨6、 1 18(圖示係以2個為例),位於金屬基板丨00之第二表面 1 0 0 b,以暴露出内連線層1 1 4之部份底面1 1 4 b。此外,亦 可形成凹穴120,位於金屬基板100之第一表面i〇〇b。在 此,形成各基板開口、凹穴的方法,舉例而言,為濕式餘 刻。 請再配合參考第1 1圖,其繪示依照本發之較佳實施 例的基板開口之平面圖例示。基板開口 1 1 6、1 1 8其中至少 之一(實施例中係以1 1 6為例),具有一晶片放置區丨i 6 a / 一點膠區116b及一抽真空區116c。且點膠區116b及抽真* 區1 1 6 c係與晶片放置區1 1 6 a相連,並為沿著晶片放置區 1 1 6 a之對角往外延伸之一對區域。 之後,如第5圖所示,形成多個電性連接開口 1 2 4, 於防焊層122及最接近内連線層114之底面114b的介電> 1 〇 1,以暴露出最接近頂面11 4 a之部份導線層1 1 2及最&近Case No. 1222734 Case No. 92127385 V. Description of the Invention (6) The patterned wire layer 108 covers the dielectric layer 110 and forms a solder resist layer 122 covering the top surface 114a of the interconnect layer 114. The top surface 11 4a and the bottom surface 11 4b of the inner line 11 4 are defined here for the convenience of subsequent description. The interconnect layer 1 1 4 is connected to the metal substrate 100 with a bottom surface 1 1 4 b. The invention uses a metal substrate as the base of a high-density module card, which can provide stable mechanical strength. In addition, the present invention utilizes a thin film deposition method in a semiconductor manufacturing process to form an interconnect layer on a metal substrate, that is, build up in a thin film deposition manner, so that a highly flattened layer can be obtained, so the accuracy Good control, and can meet the requirements of high density and fine pitch. Next, as shown in FIG. 4, at least one substrate opening 6, 1 18 (the illustration is based on 2 as an example), is located on the second surface 1 0 0 b of the metal substrate 1 00 to expose the interconnection Part of the bottom layer 1 1 4 of the wire layer 1 1 4 b. In addition, a cavity 120 may be formed on the first surface i00b of the metal substrate 100. Here, the method for forming the openings and recesses in each substrate is, for example, a wet etching. Please refer to FIG. 11 again, which illustrates a plan view of a substrate opening according to a preferred embodiment of the present invention. At least one of the substrate openings 1 1 6 and 1 1 8 (in the embodiment, 1 1 6 is taken as an example) has a wafer placement area i 6 a / a little glue area 116 b and a vacuum extraction area 116 c. In addition, the dispensing area 116b and the extraction * area 1 1 6 c are connected to the wafer placement area 1 1 6 a and are a pair of areas extending outward along the diagonal of the wafer placement area 1 1 6 a. Thereafter, as shown in FIG. 5, a plurality of electrical connection openings 1 2 4 are formed, and the dielectric > 1 〇1 on the solder resist 122 and the bottom surface 114b closest to the interconnect layer 114 is exposed to the nearest Part of the conductor layer of the top surface 11 4 a 1 1 2 and the most & near
10391twfl.ptc 第12頁10391twfl.ptc Page 12
1222734 案號 92127385 發明說明(7) ::1 二:份導線層1〇3。至此完成本發明之高密度模 [第二實施例] 承接著第一實施例的步驟,還可以進一牛 ^ ”二士。此高密度模組卡係例示於第二實施二二其= f \ 貫施例之第1圖〜第5圖的步驟,再繼續進行如 =ί第和第一實施例相同的元件係採用气 同的軚唬,在此便省略重覆的說明。 如坌β图齡- 形成多個連接墊126(在侧視剖視圖中僅顯示出一=不, 於(在内連線114的頂面11 4a的)電性連接開口124 是1222734 Case No. 92127385 Description of the invention (7) :: 1 2: Part of the wire layer 103. So far, the high-density mold of the present invention is completed. [Second embodiment] Following the steps of the first embodiment, it is also possible to add a new one. This high-density module card is exemplified in the second embodiment. Follow the steps in Figures 1 to 5 of the example, and then continue with the same components as in the first example using the same bluff, so repeated explanations are omitted here. Figure 坌 β Age-forming a plurality of connection pads 126 (only one is shown in the side cross-sectional view = no, for the electrical connection opening 124 (of the top surface 11 4a of the interconnect 114) is
之部份導線層112。此些連接墊126,可做為本模組之= 入/輸出接點,舉例而言,包括金手指。 、’、· M 一如第7圖所示,可將多個封裝元件(包括表面黏著的 i「a\ V Vt、式封裝广件、覆晶式封裴元件,及被動元 件[圖未繪示]等)電性連接至此模組基板。 (打繞H、晶片1 ϋ於内連線層114之頂面114a,電性連接 站附曰y接)至暴露的最接近頂面114a之部份導線層112。 茫接=^Λ34 ’置於凹穴120内’並電性連接(打線連接)至 ίΪΪΞ 層114之頂面U4a之部份導線層"3。並將- f 料,包覆晶片128與導線層112之電性連接處’以形 封《膠結構136。將一封膠材料填於凹穴12〇内,包覆晶 i、二日】則與導線層103之電性連接處,以形成-封 貼附晶片130於内連線層114之頂面丨丨“,電性連接Of the wire layer 112. These connection pads 126 can be used as the input / output contacts of the module, for example, including gold fingers. , ', · M As shown in Fig. 7, multiple package components (including i \ a \ V Vt, surface-mounted package components, flip-chip package components, and passive components [not shown) (Shown, etc.) is electrically connected to the module substrate. (Wound H, chip 1 pinched on the top surface 114a of the interconnect layer 114, and the electrical connection station is attached with a y connection) to the exposed part closest to the top surface 114a Part of the wire layer 112. The connection = ^ Λ34 'Placed in the cavity 120' and is electrically connected (wired) to a portion of the wire layer U4a on the top surface of the layer 114 " 3. The electrical connection between the cover wafer 128 and the wire layer 112 is sealed in a “glue structure 136. A glue material is filled in the cavity 120, and the crystal i, two days] is electrically connected to the wire layer 103. At the connection, a chip 130 is formed-sealed on the top surface of the interconnect layer 114. The electrical connection is made.
1222734 - --案號 921273RR___年月日_修4___ 五、發明說明(8) (覆晶式連接)至暴露的最接近頂面丨丨4a之部份導線層 1 12。將一封膠材料(底膠)填充至晶片13〇與暴露的部份導 線層1 1 2,以形成一底膠結構丨38。 在此,亦可利表面黏著技術(SMT)將電子元件,焊接 至内連線層的頂面或底面。例如將封裝元件丨3 2、1 5 〇 (或 是被動兀件等[圖未繪示]),焊接至内連線層114之頂面 1 14a及底面1 14b,電性連接至暴露的最接近頂面丨丨“及底 面114b之部份導線層Η?。 如第8圖所示,將一覆晶晶片148,貼附於基板開口 116所暴露出之部份底面114b,置於晶片放置區丨丨以(第u 圖)’電性連接至最接近底面丨丨4b之部份導線層丨〇 3。其中 第1 0圖中的基板開口丨丨6部份為針對第丨3圖沿丨—!剖線/的剖 於基板開口 1 1 6之點膠區11 6b進行點膠,舉例而古, 可利用一點膠裝置,例如為一點膠針頭丨44深入點膠區 11 6b,以供應一封膠材料146至基板開口116内。並於抽直 接ϊ〆曰未圖示)抽真空。藉此,以將封膠材料填 ς = 曰曰片148與導線層103之電性連接處,而作為j底 /依本發明之精神可知,並不需限定晶片放置開口 1 的形狀,其關鍵在於晶#放晉及 "、日日片狄罝區116a係接近並略大於嚣曰 晶片148之外形。而馱赚F ,丄古〜广,,p 人於覆日日 叩點膠& 1 1 6 b及抽真空區1 1 6 C係盥晶μ 放置區1 1 6a相連,並分別砬於曰u *里广彳彳β 1亍…、日日片 I刀另J位於日日片放置區1 1 6 a之相對的兩1222734--Case No. 921273RR _ Month and Day _ Rev. 4___ V. Description of the invention (8) (Flip-Chip Connection) to the exposed part of the wire layer closest to the top surface 丨 4a 1 12. A piece of adhesive material (primer) is filled in the wafer 130 and the exposed part of the wiring layer 1 12 to form a primer structure 38. Here, surface mount technology (SMT) can also be used to solder electronic components to the top or bottom surface of the interconnect layer. For example, package components 丨 3 2, 1 5 (or passive elements, etc. [not shown]) are soldered to the top surface 1 14a and the bottom surface 1 14b of the interconnect layer 114, and are electrically connected to the exposed surfaces. Near the top surface 丨 丨 "and a part of the conductor layer of the bottom surface 114b. As shown in Fig. 8, a flip-chip wafer 148 is attached to a part of the bottom surface 114b exposed by the substrate opening 116 and placed on the wafer. Area 丨 丨 is electrically connected to (bottom u) the part closest to the bottom surface 丨 4b part of the wire layer 丨 03. Among them, the substrate opening in figure 10 丨 6 is for the edge of figure 丨 3丨 —! Section line / section 1 1 6 of the substrate opening 1 6b is used for dispensing. For example and ancient times, a point dispensing device can be used, for example, a point needle 44. 44 penetrates into the section 11 6b, A piece of adhesive material 146 is supplied into the opening 116 of the substrate. The vacuum material is evacuated. (This method is used to fill the sealing material = electrical connection between the film 148 and the wire layer 103.) As the bottom of the present invention / the spirit of the present invention, the shape of the wafer placement opening 1 does not need to be limited. The key lies in the crystal # 放 晋 和 " The Dili area 116a is close to and slightly larger than the outer shape of the chip 148. And the earning F, the ancient ~ the broad, the p people dispense & 1 1 6 b and the vacuum area 1 1 6 C The toilet area μ placement area 1 1 6a is connected to each other, and is respectively located at u * 里 彳 彳 β 1 亍 ..., the Japanese-Japanese film I knife and the other J are located in the two opposite sides of the Japanese-Japanese film placement area 1 1 6 a.
10391twf1.ptc 第14頁 1222734 案號 92127385 Λ_η 曰 修正 五、發明說明(9) 側,以利於抽真空作業。以得如第9圖之結構。至此完成 本發明之高密度模組卡之例示。 除了基板開口以濕式蝕刻較佳之外,在上述其他開 口(欲形成圖案化導線層所使用的圖案化光阻層、圖案化 介電層、防焊層中的開口、電性連接開口等)之形成,在 習知中雖有各式各樣的作法,但若針對工廠的試車階段, 則以雷射法較佳,因為各規格品尚未確定,在試作中仍需 不斷地修正設計,使用雷射開口的話,可使設計的變更較 具彈性,並縮短變更設計所需的時間。 為進一步改善各導線層之線路圖案因基板或其他原 因溫度增加時,承受張力的能力,以提昇可靠性,本發明 對導線層的結構還可以略微變化。 請參考第1 〇圖,其繪示各導線層對應於基板開口 1 1 6、1 1 8周圍處的線路圖案之一例示。圖中係以導線層 1 0 4為例子。在此值得注意的是,在形成上述導線層 (1 0 3、1 0 4、1 0 8、1 1 2 )時,各導線層的線路圖案在對應基 板開口 1 1 6、1 1 8的邊緣處係呈波浪狀。 依照本發明之精神,利用在基板開口的邊緣處呈波 浪狀拉長的線路圖案,在基板形變時,具有緩衝作用,可 不致使導線因形變而被破壞,因而可提高產品之可靠度。 由此可知,本發明亦不需限定此波浪狀,簡言之如鋸齒 狀,或是其他彎摺形狀者皆屬之。 由實施例之揭露可知,本發明至少具有如下之優點: (1 ).本發明利用金屬基板作為高密度模組卡的基底,可提10391twf1.ptc Page 14 1222734 Case No. 92127385 Λ_η Revision V. Description of invention (9) side to facilitate vacuuming operation. To get the structure as shown in Figure 9. This completes the illustration of the high-density module card of the present invention. Except for the substrate opening, which is preferably wet-etched, the other openings mentioned above (the patterned photoresist layer, the patterned dielectric layer, the opening in the solder resist layer, the electrical connection opening, etc. used to form the patterned wire layer) Although there are various methods in the practice, the laser method is better for the test phase of the factory, because various specifications have not yet been determined, and the design needs to be continuously revised during the trial. The laser opening can make the design changes more flexible and shorten the time required to change the design. In order to further improve the ability of the wiring pattern of each wire layer to withstand tension when the temperature of the substrate or other reasons increases, so as to improve reliability, the structure of the wire layer of the present invention may be slightly changed. Please refer to FIG. 10, which illustrates an example of a wiring pattern around each of the conductor layers corresponding to the substrate openings 1 1 6 and 1 1 8. In the figure, the wire layer 104 is taken as an example. It is worth noting here that when forming the above-mentioned wire layer (1 0 3, 1 0 4, 1 0 8, 1 1 2), the circuit pattern of each wire layer is at the edge of the corresponding substrate opening 1 1 6 and 1 1 8 Department is wavy. According to the spirit of the present invention, the use of a wave-shaped elongated circuit pattern at the edge of the opening of the substrate has a buffering effect when the substrate is deformed, so that the wires are not damaged due to the deformation, thereby improving the reliability of the product. It can be seen that the present invention does not need to be limited to this wavy shape, in short, such as a zigzag shape or other bent shapes. It can be known from the disclosure of the embodiments that the present invention has at least the following advantages: (1). The present invention uses a metal substrate as the base of a high-density module card, which can provide
10391twfl.ptc 第15頁 1222734 _案號92127385_年月日 修正_ 五、發明說明(10) 供穩定的機械強度。又,本發明再利用半導體製程中的薄 膜沈積方式增層(build up),可得高平坦度的增層,因而 精度控制佳,並可達高密度、微間距的需求。 (2 ).本發明在晶片放置區的對角延伸有一對點膠區及抽真 空區,針對覆晶晶片的底膠製程係,利用在晶片放置區的 一隅進行點膠,而在相對的另一隅進行抽真空,以此方 式,可縮短填底膠的時間。 (3 ).同理如(2 ),因為在晶片放置開口已設置了點膠區及 抽真空區,可將晶片放置區最小化,而提高封裝的可靠 度。 (4 ).本發明的各導線層在對應晶片放置開口處係呈波浪 狀,在基板形變時,具有缓衝作用,因而可提高基板之忍 受應變的能力,因而提高產品之可靠度。 (5 ).本發明可利用貫孔使薄膜内連線層的導線層和金屬基 板相連接,並使金屬基板接地,可使模組卡上的各電子元 件(如晶片及封裝元件等)有良好的電流輸送性能。 雖然本發明已以較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍内,當可作些許之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。10391twfl.ptc Page 15 1222734 _ Case No. 92127385_ Year Month Day Amendment _ V. Description of the invention (10) Provide stable mechanical strength. In addition, the present invention reuses the thin film deposition method build-up in the semiconductor process to obtain a high-flatness build-up. Therefore, the precision control is good, and the requirements of high density and fine pitch can be achieved. (2) The present invention has a pair of dispensing areas and a vacuuming area extending diagonally from the wafer placement area. For the primer process system of a flip-chip wafer, a stack of wafers is used for dispensing, and Vacuum can be applied at once, in this way, the time for filling the primer can be shortened. (3). Similarly to (2), because the dispensing area and the vacuum area have been set in the wafer placement opening, the wafer placement area can be minimized, and the reliability of the package can be improved. (4) Each wire layer of the present invention is wavy at the opening where the corresponding wafer is placed, and has a buffering effect when the substrate is deformed, so that it can improve the ability of the substrate to withstand strain and thus improve the reliability of the product. (5) The present invention can use a through hole to connect the wire layer of the film interconnecting layer and the metal substrate, and ground the metal substrate, so that each electronic component (such as a chip and a package component) on the module card has Good current delivery performance. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
10391twf1.ptc 第16頁 1222734 _案號92127385_年月日_ί±^_ 圖式簡單說明 第1〜5圖繪示本發明之第一實施例的一種高密度模組 基板之製程流程剖視圖; 第6〜9圖繪示接續第一實施例的步驟之本發明之第二 實施例的一種高密度模組卡之製程流程剖視圖; 第1 0圖繪示依照本發明之較佳實施例的各導線層之 線路圖案之一例示的平面圖;以及 第1 1圖繪示依照本發明之較佳實施例的基板開口之 一例示的平面圖。 [圖式標示說明] 100 : 金屬基板 100a :第一表面 100b :第二表面 114:内連線層(薄膜内連線 層) 114a: 頂面 114b: 底面 101 、 102 、 106 、 110 :介電層 103、104、108、112 :導線層 1 0 5 : 貫孔 1 1 6、1 1 8 : 基板開口 116a : 晶片放置區 116b : 點膠區 116c : 抽真空區 120: 凹穴 1 2 2 : 防焊層 12 4 : 電性連接開口 126 :連接墊 128、130、134、148 :晶片 132、150 : 封裝元件 1 3 6、1 4 0 : 封膠結構 14 2 : 抽真空管 1 4 4 : 點膠針頭 14 6 : 封膠材料10391twf1.ptc Page 16 1222734 _Case No. 92127385_Year Month Day_ί ± ^ _ Brief Description of Drawings Figures 1 to 5 are cross-sectional views showing the process flow of a high-density module substrate according to the first embodiment of the present invention; 6 to 9 are cross-sectional views showing a process flow of a high-density module card according to a second embodiment of the present invention following the steps of the first embodiment; and FIG. 10 is a diagram showing each of the processes according to the preferred embodiment of the present invention. An exemplary plan view of one of the wiring patterns of the wire layer; and FIG. 11 illustrates an exemplary plan view of one of the substrate openings according to a preferred embodiment of the present invention. [Explanation of Graphical Remarks] 100: metal substrate 100a: first surface 100b: second surface 114: interconnecting layer (film interconnecting layer) 114a: top surface 114b: bottom surface 101, 102, 106, 110: dielectric Layers 103, 104, 108, 112: wire layer 105: through-hole 1 1 6, 1 1 8: substrate opening 116a: wafer placement area 116b: dispensing area 116c: vacuum area 120: cavity 1 2 2: Solder mask 12 4: Electrical connection openings 126: Connection pads 128, 130, 134, 148: Wafers 132, 150: Package components 1 3 6, 1 4 0: Sealant structure 14 2: Evacuation tube 1 4 4: Points Glue Needle 14 6: Sealant
10391twfl.ptc 第17頁10391twfl.ptc Page 17
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