CN103229294A - 无芯衬底处理中的电解沉积和通孔填充 - Google Patents
无芯衬底处理中的电解沉积和通孔填充 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 238000012545 processing Methods 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 239000002184 metal Substances 0.000 claims abstract description 76
- 238000000034 method Methods 0.000 claims abstract description 36
- 238000009713 electroplating Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 122
- 230000008021 deposition Effects 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 17
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 238000007772 electroless plating Methods 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 230000005540 biological transmission Effects 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 3
- 239000011162 core material Substances 0.000 claims 26
- 239000002344 surface layer Substances 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 abstract description 3
- 230000000712 assembly Effects 0.000 abstract 1
- 238000000429 assembly Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 23
- 229910052802 copper Inorganic materials 0.000 description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 238000000151 deposition Methods 0.000 description 17
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 15
- 239000010931 gold Substances 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 8
- 238000005868 electrolysis reaction Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 229910052763 palladium Inorganic materials 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 229910000906 Bronze Inorganic materials 0.000 description 5
- 239000010974 bronze Substances 0.000 description 5
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 5
- 238000004070 electrodeposition Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000002335 surface treatment layer Substances 0.000 description 4
- 239000011135 tin Substances 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229960004643 cupric oxide Drugs 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
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- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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Abstract
描述包括无芯衬底的电子组件及其利用电解电镀的制造。一种方法包括:提供包括金属的核芯;以及在核芯上形成电介质材料。该方法还包括在电介质材料中形成通孔,通孔定位成曝露金属区域。该方法还包括执行在通孔中以及在金属区域上电解电镀金属的步骤,其中核芯在在通孔中电解电镀金属期间电耦合到电源,并将电流传输至金属区域。该方法还包括在在通孔中电解电镀金属之后去除金属核芯。还描述其它实施例并要求其它实施例的权利。
Description
背景技术
可以在由诸如硅的材料制成的半导体晶圆上形成集成电路。对半导体晶圆进行处理以便形成各种电子器件。将晶圆切割成半导体芯片(芯片又称为管芯),然后可利用各种已知方法将芯片附连到衬底。衬底通常设计成将管芯耦合到印刷电路板、插口或其它连接。衬底还可以执行一个或多个其它功能,包括但不限于保护、隔离、绝缘和/或热控制管芯。传统上,衬底由核芯形成,核芯由包括浸渍环氧树脂材料的玻璃织物层的层压多层结构组成。在该结构上形成接触焊盘和导电迹线以便将管芯电耦合至与封装衬底耦合的器件。
已经开发了无芯衬底以便减小衬底的厚度。在无芯衬底中,通常提供可去除核芯层,在可去除核芯上堆积导电层和电介质层,然后去除核芯。无芯衬底通常包括多个通孔,在这些通孔中形成有层间电连接。
在一种类型的管芯附连工艺中,通过利用称为C4(可控塌陷芯片连接)工艺的方法,利用倒装芯片配置中的常规焊料凸块阵列将管芯安装到衬底上,其中,焊料凸块位于管芯和衬底之间。在C4工艺中,可以利用例如镂空掩膜印刷法将焊料放置在管芯的活性一侧上、衬底上或管芯和衬底上的焊盘上。然后,将焊料熔融并允许其流动,从而确保每个凸块完全浸润它下面的焊盘。接着,进行二次回流操作,并在管芯焊盘和衬底焊盘之间进行焊料连接。然后,使接合后的封装冷却以完成焊料凸块接点。也可以在封装和诸如母板的印刷电路板之间进行焊料凸块连接。
可以在衬底上提供表面处理层。表面处理层通常起到在装配之前保护底层衬底电连接的作用。例如,如果衬底包括铜(Cu)连接,那么可以在铜上设置表面处理层。如果将器件焊接到衬底,那么表面处理层可以与焊料相互作用。或者,可以在焊接操作之前去除表面处理层。用于保护铜的典型表面处理层包括镍/钯/金(Ni/Pd/Au)层和有机可焊性保护层(OSP)。镍钯金表面处理层包括位于铜上的镍层,紧接是镍上的钯层,再紧接是钯上的金层。镍提供铜迁移屏障,并保护铜表面以免氧化。钯充当镍层的氧化屏障。金层起到在焊料接点形成期间提高浸润性的作用。OSP表面处理层通常包括水基有机化合物,它与铜选择性地键合以便形成起到保护铜以免氧化的作用的有机金属层。
当使用无铅焊料来将管芯耦合到衬底时,通常使用包括锡、银和铜合金(SAC)的锡基焊料。表面处理层对于确保坚固、耐用的接点来说很重要。例如,如果表面处理层不足以保护铜,那么会发生氧化,并且氧化铜和无铅焊料之间的相互作用会导致形成不合适的接点。另外,取决于表面处理层中所用的材料,可能会发生不良反应而不利地影响接点的性能。
附图说明
将参考附图举例描述实施例,附图不一定按比例绘制,并且其中:
图1(A)-1(U)示出根据某些实施例用于形成无芯衬底的处理操作的视图;
图2示出根据某些实施例用于形成无芯衬底的工艺操作的流程图;
图3示出根据某些实施例包括耦合到管芯和板的无芯衬底的组件的横截面图;
图4示出可应用实施例的电子系统装置。
具体实施方式
在制造无芯衬底期间用于填充通孔的常规方法利用无电解镀(electroless plating)来形成Cu层以作为用于随后电解电镀的电镀母线(buss)。在无电解沉积层上图案化光刻胶层以定义导电迹线之后,在通过电解Cu电镀法电镀迹线的同时填充通孔。无电解Cu层(其延伸到衬底的边缘)在边缘之一处电耦合到电源,并充当电镀母线以便为电解沉积提供电流。用于在高密度焊盘上形成表面处理层(surface finish)的常规方法也利用无电解镀。在无电解镀中,不使用电流。通过电镀溶液中的化学物来还原金属离子,并在所有表面上沉积期望的金属。但是,随着通孔尺寸减小以及电介质层厚度增加(改变了通孔的高宽比),在常规的无电解通孔填充期间会出现空隙和通孔凹穴形成,从而导致可靠性问题。另外,无电解镀一般以比电解电镀缓慢的速率进行。注意,电解沉积层是结晶性的,并且一般具有比无电解沉积层大得多的密度。并且,对于表面层形成和随后的焊料接点形成,已发现,无电解表面处理镀层具有磷诱导焊料接点质量问题、氧化和较差抗腐蚀性的缺陷。
某些实施例涉及无芯衬底的形成,其中利用电解电镀工艺来填充通孔,而无需如同常规工艺中的第一无电解镀操作。电解电镀工艺利用穿过包含溶解金属离子的溶液的电流,离子附着到待沉积的带电金属表面。某些实施例利用这样一种方法,其中临时衬底核芯可以用作电镀母线,然后利用电解工艺来填充通孔。
图1(A)-1(U)示出根据某些实施例用于形成无芯衬底的操作。如在图1(A)中可见,提供临时衬底核芯10。核芯10可以由例如诸如铜的金属形成。图1(B)示出图案化的抗蚀剂层12的形成,其中具有曝露核芯10的开口14。然后,可以在核芯10上于开口14内沉积多个层,如图1(C)所示。可以在核芯上电解电镀第一铜层16。该铜层16可以在稍后的工艺中去除,从而可以在衬底的表面上形成凹穴。然后,可以在第一铜层16上电解电镀表面处理层18。表面处理层18的一个实例包括金、钯和镍的子层。接着,可以在表面处理层18上电解电镀第二铜层20。临时核芯10可以通过连接64连接到电源,并用作所有或一部分电镀母线以用于电解沉积。电镀母线是指用于将电流传输到待电镀区域的结构。在本文所描述的各种实施例的一个方面,核芯在电解电镀操作期间充当电镀母线的至少一部分。
接着,如在图1(D)中可见,去除图案化的抗蚀剂12。如图1(E)所示,在核芯10和电解电镀层16、18、20上方形成电介质层22。电介质层22可以利用堆积工艺由诸如聚合物的材料形成。合适材料的一个实例是可以从Ajinomoto Fine-Techno Company, Inc获得的称为Aginomoto Build-up Film(ABF)的聚合环氧膜。可以在电介质层22中形成通孔24,以便曝露第二铜层22,如图1(F)所示。通孔可以利用诸如激光钻孔的任何合适的技术来形成。
通孔24可以利用电解沉积法用材料(例如,铜)填充以便形成填充通孔26。如图1(G)所示,临时核芯10可以通过连接64电耦合至电源。定义通孔的底表面是铜层20,铜层20通过层18和16电耦合至临时核芯10。通孔24可以用电解电镀到铜层20上的材料来填充。
根据某些实施例,一旦填充了通孔24,便可在电介质层22的表面和填充通孔24表面上无电解沉积薄金属层30。可以形成并图案化光刻胶层(例如,干膜抗蚀剂)以便定义曝露将形成导电迹线的区域的开口。然后,可以进行电解沉积以便形成导电迹线30,如图1(H)所示。迹线30可以包括无电解沉积金属薄层和电解沉积金属较厚层。迹线的电解沉积可以利用耦合到电源以便提供电流以用于电解电镀的无电解沉积金属来进行(如上文第11段所描述),或者可以利用耦合到电源的核芯10以便提供电流以用于电解电镀。然后,可以去除光刻胶层30,如图1(I)所示。还可以进行诸如利用例如称为CZ工艺的常规工艺的表面粗化和闪速蚀刻(flash etch)的操作以便去除底层无电解沉积金属。
如图1(J)所示,可以沉积另一电介质层32(例如,ABF)并形成通孔34。可以利用如上所述的电解电镀来填充通孔34以便形成填充通孔36,其中电连接包括穿过迹线层30、填充通孔24、电解沉积层20、18、16、以及在电镀操作期间通过连接64耦合到电源的临时核芯10形成的路径,如图1(K)所示。
可以采用与如上所述的迹线30相同的方式形成迹线40,包括形成图案化的光刻胶38,如图1(L)所示。可以去除图案化的光刻胶38,并如上所述进行诸如表面粗化和闪速蚀刻的其它操作,从而得到如图1(M)所示的结构。如果需要,可以采用如上所述的方式形成电介质材料、通孔和迹线的额外层。图1(N)示出具有电解填充通孔46的额外的电介质层42,在电解填充通孔46上形成有导电迹线区域50。
如图1(O)所示,可以在结构上形成另一电介质材料层52。在某些实施例中,该电介质材料可以是将在衬底表面上使用的焊料抗蚀剂材料。当电介质材料52由抗蚀剂材料形成时,可对其进行图案化以便形成开口54,如图1(O)所示。可以在开口54中电解形成多个层。这些层可以包括例如在合适表面处理层中所用的各种层或子层。如图1(P)所示,一个实例包括电解沉积的镍(Ni)层60、钯(Pa)层58和金(Au)层56。还可以使用众多其它表面处理层材料。在某些实施例中,在去除核芯之后,图中所示的最上层56具有曝露表面,该曝露表面可以与诸如焊料凸块的焊料连接直接接触,然后进行加热以便使焊料回流,从而对包括但不限于半导体管芯的器件形成焊料触点。
如图1(Q)所示,可以去除临时核芯10,从而得到无芯衬底。临时核芯10可以利用任何合适的方法来去除,包括但不限于蚀刻。还可以去除沉积在临时核芯10上的第一铜层16,从而在下表面上留下凹穴76,如图1(R)所示。凹陷表面可以用作例如接触焊盘或焊料凸块的接收空间。
在某些实施例中,有用的是能够具有在衬底的不同区域有所不同的表面处理层。这可以通过利用与电解沉积工艺兼容的保护膜来实现。如图1(S)所示,在衬底的部分上方形成保护膜62(例如,包括但不限于光刻胶膜的聚合物膜)。如在图1(S)中可见,衬底右侧上的两个开口54被膜62覆盖,并且左侧上的两个则未被覆盖。然后,可进行电解沉积以便形成层60、58和56,如图1(T)所示。
如图1(U)所示,接着可以去除临时核芯10(它在电解沉积期间用作电镀母线)和保护膜62,从而得到在不同表面区域具有不同表面处理层的衬底。
已发现,表面处理层(例如,层56、58、60)的电解沉积提供比无电解沉积层更好的抗氧化性和焊料接点可靠性。
图2示出根据某些实施例的操作的流程图。框110是在临时核芯上形成导电区域。临时核芯可以包括诸如铜的金属。框112是在导电区域和临时核芯上形成诸如ABF的电介质层。框114是通过钻通电介质层(ABF)以到达导电区域而形成通孔。框116是利用耦合到电源以便提供执行电解电镀的电流的临时核芯来进行通孔填充。框118是无电解镀和干膜抗蚀剂(DFR)图案化。框120是电解电镀以便完成导电图案(迹线)的形成。框122是去除干膜抗蚀剂、表面粗化处理(CZ)和利用堆积工艺形成另一电介质层(ABF)。框124是通过钻通电介质层(ABF)以到达导电图案而形成通孔。框126是利用电解电镀填充通孔,如同框116。框128是无电解镀和干膜抗蚀剂(DFR)图案化。框130是电解电镀以便完成另一导电图案层的形成。
框132是确定是否已经实现期望数量的通孔和导电图案层。如果否,那么返回到框124并继续形成额外层。如果是,那么进行到框134,框134是干膜抗蚀剂去除、表面处理(CZ)和焊料抗蚀剂沉积。可以形成并图案化焊料抗蚀剂以便留下开口,可以在开口中沉积表面处理层金属层。
框136是确定衬底表面的不同区域中是否需要不同的表面处理层。对于某些类型的连接,例如某些C4连接,不同区域中的不同表面处理层是有用的。
如果框136的答案是“否”,那么接着按照框138利用电解电镀在焊料抗蚀剂的开口中沉积表面处理层。然后,在完成电解电镀之后,可以去除临时核芯,如框140所指示。如果框136的答案是“是”,那么继续进行至框142,并在表面上的合适位置形成保护膜。框144是在焊料抗蚀剂的开口中电解沉积表面处理金属层。框146是去除保护膜,这可以利用合适的加热或蚀刻操作来进行。框148是形成额外的保护膜(保护膜2)(如果需要的话),以便可以利用电解沉积来进行第二表面处理层(SF2)的沉积。然后,去除第二保护膜。框150是去除临时核芯。应了解,在各种实施例的范围内,可以对结合图2描述的以上操作进行各种添加和/或修改。另外,某些实施例可以涉及图2中所指定的操作的子集,而与图2中所指定的其它操作无关。
图3示出根据某些实施例的组件的一部分,包括在一侧上通过焊料连接78耦合到管芯74、而在另一侧上通过焊料连接76耦合到板72的无芯衬底。衬底在它的厚度内包括多个层级的通孔和布线迹线(图案)。衬底对应于耦合到管芯74和板72之后的如图1(R)所示的衬底。通孔用利用耦合到电源以便传输电流用于电镀操作的核芯10(因为已经去除)形成的电解电镀金属(如铜)来填充。焊料连接76、78可以利用诸如SAC(锡/银/铜)焊料的无铅焊料来形成。在该实施例中,上、下表面上的表面处理层的至少一部分已经与焊料发生反应,并且因此,衬底上的界面焊料连接处和附近的区域可以包括诸如由包括例如锡、银、铜、镍、钯和金的金属的各种组合形成的合金和金属间化合物的反应产物。
包括如以上实施例中所描述地那样形成的部件的组件可以应用于各种电子部件。图4示意性地示出可以实施所描述的实施例的方面的电子系统环境的一个实例。其它实施例无需包括图4中所指定的所有特征,并且可以包括图4中没有指定的备选特征。
图4的系统201可以包括至少一个中央处理单元(CPU)203。CPU 203又称为微处理器,它可以是附连到集成电路封装衬底205的管芯,而集成电路封装衬底205接着耦合到印刷电路板207,在该实施例中,印刷电路板207可以是母板。CPU 203和耦合到板207的封装衬底205是可根据诸如上述的实施例形成的电子器件组件的实例。包括但不限于以下论述的存储器和其它部件的各种其它系统部件也可以包括根据上述实施例形成的结构。
系统201还可包括同样沉积在母板207上的存储器209和一个或多个控制器211a、211b…211n。母板207可以是单层或多层板,它具有在封装205中的电路和安装到板207的其它部件之间提供通信的多条导线。或者,CPU 203、存储器209和控制器211a、211b…211n中的一个或多个可以沉积在诸如子卡或扩展卡的其它卡上。CPU 203、存储器209和控制器211a、211b…211n均可坐落在各个插口中,或者可以直接连接到印刷电路板。还可包含显示器215。
任何合适的操作系统和各种应用可以在CPU 203上执行,并驻存在存储器209中。驻存在存储器209中的内容可以根据已知的缓存技术进行缓存。存储器209中的程序和数据可以作为存储器管理操作的一部分交换到存储设备213中。系统201可以包括任何合适的计算装置,包括但不限于大型计算机、服务器、个人计算机、工作站、膝上型计算机、手持计算机、手持游戏装置、手持娱乐装置(例如,MP3(移动图片专家组第3层音频)播放器)、PDA(个人数字助理)、电话装置(无线或有线)、网络器具、虚拟化装置、存储控制器、网络控制器、路由器等。
控制器211a、211b…211n可以包括以下控制器中的一种或多种:系统控制器、外围控制器、存储器控制器、集线器控制器、I/O(输入/输出)总线控制器、视频控制器、网络控制器、存储控制器、通信控制器等。例如,存储控制器可以根据存储协议层控制从/向存储设备213读取/写入数据。该层的存储协议可以是多种已知存储协议中的任一种协议。写入到或从存储设备213读取的数据可以根据已知的缓存技术进行缓存。网络控制器可以包括用于通过网络217向/从远程装置发送/接收网络分组的一个或多个协议层。网络217可以包括局域网(LAN)、互联网、广域网(WAN)、存储区域网(SAN)等。实施例可以配置成通过无线网络或连接传送和接收数据。在某些实施例中,网络控制器和各种协议层可以采用非屏蔽双绞线电缆上的以太网协议、令牌环协议、光纤信道协议等或任何其它合适的网络通信协议。
本文所用的术语“一(a/an)”表示所提到的项存在至少一个,而不是表示数量的限制。另外,本文所用的诸如“第一”、“第二”等术语不一定表示任何特定的次序、数量或重要性,而是用于区分一个要素和另一个要素。
尽管上文描述并在附图中示出了某些实例性实施例,但应了解,这些实施例只是说明性而不是限制性的,并且实施例不限于所示和所描述的特定构造和布置,因为本领域技术人员可以联想到修改。
Claims (16)
1. 一种方法,包括:
提供包括金属的核芯;
在所述核芯上形成电介质材料;
在所述电介质材料中形成通孔,所述通孔定位成曝露金属区域;
执行在所述通孔中以及在所述金属区域上电解电镀金属的步骤,其中所述核芯在在所述通孔中电解电镀金属期间电耦合到电源,并将电流传输至所述金属区域;以及
在在所述通孔中电解电镀金属之后去除所述金属核芯。
2. 如权利要求1所述的方法,还包括:在所述核芯上形成电介质材料之前,
在所述金属核芯上形成图案化的光刻胶层;
执行在所述图案化的光刻胶层的开口中电解电镀至少一个金属层的步骤,其中所述核芯在在所述开口中电解电镀所述至少一个金属层期间电耦合到电源,并将电流传输至所述开口中的所述至少一个金属层;以及
去除所述图案化的光刻胶层,
其中在所述核芯上形成电介质材料包括在所述核芯以及所述至少一个金属层上定位所述电介质材料。
3. 如权利要求1所述的方法,还包括:
执行在所述电介质层上和所述通孔中的金属上无电解镀金属层的步骤;
在所述无电解镀金属层上形成图案化的抗蚀剂层以便定义导电迹线区域;以及
执行在所述导电迹线区域上电解电镀金属的步骤,以便形成导电迹线。
4. 如权利要求3所述的方法,还包括:
在所述导电迹线和所述电介质层上形成额外的电介质层;
在所述额外的电介质层中形成额外通孔,所述额外通孔定位成从所述导电迹线接触底层金属;以及
执行在所述额外通孔中的所述底层金属上电解电镀金属的步骤,其中所述核芯在在所述底层金属上电解电镀所述金属期间电耦合到电源,并将电流传输至所述底层金属。
5. 如权利要求4所述的方法,还包括:
执行在所述额外电介质层上以及在所述额外通孔中的底层金属上的电解电镀金属上额外地无电解镀额外金属层的步骤;
在所述额外的无电解镀金属层上形成图案化的抗蚀剂层以便定义额外的导电迹线区域;以及
执行在所述额外导电迹线区域上电解电镀金属的步骤,以便形成额外的导电迹线。
6. 如权利要求5所述的方法,还包括在所述额外导电迹线和所述额外电介质层上形成图案化的焊料抗蚀剂层,在所述图案化的焊料抗蚀剂层中包含开口。
7. 如权利要求6所述的方法,其中所述图案化的焊料抗蚀剂层中的所述开口曝露所述额外导电迹线的部分,并且执行在所述额外导电迹线的曝露部分上电解电镀金属的步骤以便形成表面处理层,其中所述核芯在在所述额外导电迹线的曝露部分上电解电镀金属期间电耦合到电源并向所述曝露部分传输电流。
8. 如权利要求7所述的方法,其中在在所述开口中电解电镀金属之后去除所述核芯以便形成所述表面处理层。
9. 一种方法,包括:
提供包括金属的核芯;
在所述核芯上形成电介质材料;
在所述电介质材料中形成通孔,所述通孔定位成曝露金属区域;
执行在所述通孔中的所述金属区域上电解电镀金属的步骤;
其中所述核芯在在所述通孔中的所述金属区域上电解电镀金属期间耦合到电源并传输电流;
其中在在所述通孔中的所述金属区域上电解电镀金属期间,所述核芯用作电镀母线;
在在所述通孔中电解沉积所述金属之后,在所述电介质材料和填充后的通孔上形成导电迹线;
在所述导电迹线上形成焊料抗蚀剂层并在所述焊料抗蚀剂层中提供开口,所述开口曝露额外的金属区域;
通过在所述焊料抗蚀剂层中的开口中的额外金属区域上电解电镀金属来形成金属表面处理层,其中所述核芯在在所述开口中的所述额外金属区域上电解电镀金属期间耦合到电源并向所述额外金属区域传输电流;以及
在所述额外金属区域上电解电镀金属之后去除所述核芯。
10. 如权利要求9所述的方法,还包括:在形成所述表面处理层之前,在所述焊料抗蚀剂层中的开口中的至少一个开口上形成保护层,其中所述保护层由在电解电镀过程期间不会被金属电镀的材料形成。
11. 如权利要求9所述的方法,还包括:在形成所述表面处理层之后,去除所述保护层。
12. 如权利要求10所述的方法,还包括:在去除所述保护层之后,以及在去除所述核芯之前,形成额外的保护层以便覆盖所述焊料抗蚀剂层中的开口中的不会被之前形成的保护层覆盖的至少一些开口。
13. 如权利要求12所述的方法,还包括:在所述焊料抗蚀剂层的开口中的不会被所述额外保护层覆盖的额外金属区域上电解电镀金属,其中所述核芯在在所述开口中的不会被所述额外保护层覆盖的额外金属区域上电解电镀金属期间耦合到电源并向所述额外金属区域传输电流。
14. 一种方法,包括:
提供包括金属的核芯材料;
在所述核芯材料上形成多个层,所述层包括电介质层和在所述电介质层内延伸的导电路径;
其中所述导电路径中的至少一个导电路径从所述核芯延伸到所述电介质层之一的上表面;
在延伸到所述电介质层之一的上表面的所述至少一个导电路径上电解电镀至少一个金属层,其中所述核芯在电解电镀所述至少一个金属层期间耦合到电源并向延伸到所述电介质层之一的上表面的所述至少一个导电路径传输电流;以及
在电解电镀所述至少一个金属层之后去除所述核芯以便形成无芯衬底。
15. 如权利要求14所述的方法,
其中所述至少一个金属层包括曝露表面处理层金属层;
将所述曝露表面处理层金属层定位成与焊料凸块直接接触;以及
加热所述焊料凸块以便形成将所述焊料凸块耦合到所述无芯衬底的焊料接点。
16. 如权利要求15所述的方法,还包括将管芯耦合到所述焊料凸块。
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US12/890,662 US8127979B1 (en) | 2010-09-25 | 2010-09-25 | Electrolytic depositon and via filling in coreless substrate processing |
US12/890,662 | 2010-09-25 | ||
PCT/US2011/053307 WO2012040724A1 (en) | 2010-09-25 | 2011-09-26 | Electrolytic depositon and via filling in coreless substrate processing |
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KR (1) | KR101593280B1 (zh) |
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Also Published As
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WO2012040724A1 (en) | 2012-03-29 |
US20120074209A1 (en) | 2012-03-29 |
TW201220989A (en) | 2012-05-16 |
TWI571191B (zh) | 2017-02-11 |
US8127979B1 (en) | 2012-03-06 |
KR101593280B1 (ko) | 2016-02-11 |
KR20130096281A (ko) | 2013-08-29 |
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