CN103210475A - 衬托器和外延晶片的制造方法 - Google Patents
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Abstract
本发明提供一种衬托器,其可以通过增大衬托器的厚度,来增大衬托器外周部的热容,使晶片外周部与内周部的热条件相等;进一步,提供一种外延晶片的制造方法,其是使用所述衬托器,来进行外延层的气相生长。本发明人根据至目前为止的实验结果和经验,推测背面沉积与晶片和衬托器之间所产生的热传递存在密切的关系,即推测由于晶片与衬托器接触、或晶片与衬托器靠近,因此,晶片外周部的温度高于晶片内周部,而导致容易产生背面沉积;并尝试通过使晶片背面的晶片外周部与内周部的热条件固定,来解决问题。
Description
技术领域
本发明涉及一种衬托器(susceptor)及外延晶片的制造方法,具体来说,涉及一种衬托器、及使用该衬托器的外延晶片的制造方法,其可以在外延气相生长时减少晶片背面外周所产生的析出物(沉积(deposition))。
背景技术
在硅晶片的外延生长中,常常使用一种设置有贯穿至衬托器背面且敞开的通孔的衬托器,以提高外周电阻率分布或改善背面外观(专利文献1)。利用衬托器上所设置的通孔,可以达成各种品质改善,但与此同时,在晶片的背面外周部会产生局部的沉积(以下称为“背面沉积”)。
一般来说,原料气体是在晶片表面侧流动,但在外延制造装置的机构上,原料气体可能会绕到衬托器背面。绕到衬托器背面的原料气体,从衬托器的通孔,进一步绕到晶片的背面,并在晶片的背面反应,而产生背面沉积。
此时,在衬托器与晶片的接触部附近,即晶片背面的外周部分(如果是直径为300mm的晶片,则为距离晶片的中心的半径为147~149mm左右的部分)上,局部地产生晶片的背面沉积,它的高度依据反应时间而变化,达到几百纳米。
当根据背面标准来测定产生了背面沉积的外延晶片的平坦度时,外延晶片的厚度形状呈外周部分急剧增大的形状,并成为平坦度恶化的主要原因。在元件细微化、对晶片外周部分都要求高平坦度的当今,背面沉积对于尖端产品制造而言,成为较大的阻碍。
先前,由于背面沉积是集中产生在晶片与衬托器接触或非常靠近以致重合的部分上、即衬托器的载置余量处,且背面沉积高度是依据衬托器侧的加热量而变动,因此,主要使用以下方法等来应对:尽可能缩小前述衬托器的载置余量;或反而放大衬托器的载置余量,并使背面沉积连续地产生;或减少由衬托器底部的灯管所实施的灯管加热。
然而,上述方法虽然对背面沉积较为有效,但存在以下弊病:容易产生滑移位错、损害表面的纳米拓扑(nano topology)品质、损害外周电阻率分布品质。
并且,在专利文献2中,记载有以下事项:通过在衬托器背面的与晶片外周部相对应的位置处设置突出物,增大衬托器的热容,提高保温效果,来使晶片外周部温度增加,抑制滑移位错的产生。
现有技术文献
专利文献
专利文献1:日本特开2003-229370
专利文献2:日本特开2003-37071
发明内容
发明所要解决的课题
本发明人根据至目前为止的实验结果和经验,推测背面沉积,与晶片和衬托器之间所产生的热传递存在密切的关系,即推测由于晶片(wafer)与衬托器接触、或晶片与衬托器靠近,因此,晶片外周部的温度高于晶片内周部,而导致容易产生背面沉积;并尝试通过使晶片外周部与内周部的热条件固定,来解决问题。
即,为了消除上述问题,本发明的目的在于提供一种衬托器,其可以通过增大衬托器的厚度,来增大衬托器外周部的热容,使晶片的外周部与内周部的热条件相等;进一步,提供一种外延晶片的制造方法,其是使用所述衬托器,来进行外延层的气相生长。
解决课题的方法
为了解决上述课题,在本发明中,提供一种衬托器,其在进行外延层的气相生长时,支持半导体基板,其特征在于,在该衬托器的上面,形成有内部将要配置前述半导体基板的锪孔,该锪孔呈双层结构,具有支持前述半导体基板的外周缘部的上层锪孔部、与在该上层锪孔部的下层且形成于中心侧的下层锪孔部,在前述下层锪孔部,形成有贯穿至前述衬托器的背面且在进行前述气相生长时为敞开状态的孔部,在前述衬托器的背面侧,至少在与前述上层锪孔部相对应的位置处设置有突出部。
这样一来,前述衬托器由于增大对应前述上层锪孔部的位置的厚度,热容也增大,而使晶片外周部的温度不易上升,因此,可以使晶片外周部与内周部的热条件固定,从而可以抑制背面沉积的产生,而并不损害晶片表面的纳米拓扑品质和外周电阻率分布品质。
并且此时,优选为,前述突出部的厚度是与前述上层锪孔部相对应的位置处的除了前述突出部以外的衬托器的厚度的3倍以下。
这样一来,由于可以更准确地固定晶片外周部与内周部的热条件,因此,可以实现本发明的效果,即实现更有效地抑制背面沉积。
并且此时,优选为,在前述突出部上施加有沟槽。
这样一来,由于必然可以在前述突出部上产生遮挡灯管加热的部分,并且表面积变大而易于散热,因而可以降低前述突出部的温度,因此,可以实现本发明的效果,即实现更有效地抑制背面沉积。
并且此时,优选为前述沟槽呈格子状。
这样一来,可以进一步有效地降低前述突出部的温度,可以抑制背面沉积。
并且此时,优选为,前述沟槽的深度是与前述上层锪孔部相对应的位置处的衬托器的厚度的1/10以上。
这样一来,可以进一步有效地降低前述突出部的温度,可以抑制背面沉积的产生。
并且,本发明提供一种外延晶片的制造方法,其是制造外延晶片的方法,其特征在于,使用前述本发明的衬托器,在该衬托器的锪孔上载置晶片,并一边流入原料气体,一边在前述晶片上进行外延层的气相生长。
通过这样进行气相生长,可以制造一种外延晶片,所述外延晶片的背面沉积的产生得以被抑制,且不会损害晶片表面的纳米拓扑品质和外周电阻率分布品质。
发明的效果
如上所述,根据本发明,当在晶片表面上使外延层气相生长时,可以使晶片外周部与内周部的热条件固定,并且可以抑制背面沉积的产生,而不会损害晶片表面的纳米拓扑品质和外周电阻率分布品质。并且,通过使用这种衬托器,在晶片表面上进行外延层的气相生长,可以制造一种背面沉积的产生得以被抑制的外延晶片。
附图说明
图1是表示本发明中所使用的外延生长装置的示意剖面图。
图2是表示本发明的衬托器的示意仰视图、示意剖面图及突出部的一部分的放大视图。
图3是表示在本发明的实施例中,分别使用现有技术的衬托器与本发明的衬托器,在晶片表面上进行外延层的气相生长,并利用Wafer Sight(松下电器(股)(Panasonic Corporation)制造)来评价所述晶片背面的结果。
图4是表示在本发明的实施例中,使用本发明的衬托器,在晶片表面上进行外延层的气相生长,并利用UA3P(KLA-Tencor Corporation制造)来评价所述晶片背面的结果。
图5是表示表示适用本发明的外延晶片的制造方法的处理次序的流程图。
具体实施方式
以下,参照附图,详细说明本发明的实施方式,但本发明并不限定于这些实施方式。
将适用本发明的外延晶片的制造方法的次序的流程图示于图5。
首先,在工序(a)中,准备使外延层生长的晶片(硅晶片)。在此,本发明并不限定于硅晶片,也可以使用碳化硅晶片(silicon carbide wafer)、或GaP晶片、GaAs晶片等化合物半导体晶片等。
其次,在工序(b)中,对硅晶片,适当进行RCA清洗等清洗。
此清洗工序中的清洗法,除了典型的RCA清洗以外,还可以使用在一般进行的范围内更改药液的浓度或种类的方法。
在工序(c)之后,将硅晶片转移至外延生长装置中,进行处理。将工序(c)之后所使用的外延生长装置的一个实例的示意图示于图1。
外延生长装置51是由以下部分构成:腔室52;衬托器71,是配置于腔室内部;衬托器支持构件53,是从下方支持衬托器,且自由地旋转并上下移动;晶片搬送口54,是用于将晶片搬入至腔室52内,或相反地向外搬出;气体导入管55,是向腔室内供给各种气体;未图示的氢气供给构件及原料气体供给构件,是连接于气体导入管55,向腔室内供给氢气、及供给硅烷等原料气体;气体排出管57,是将各种气体从腔室内排出;加热构件58,是备置于腔室52的外部;及,未图示的晶片转移构件,是将硅晶片转移至腔室内,并且从腔室52内转移硅晶片。
而且,在衬托器71上,也可以形成有顶料销(lift pin)用通孔73。顶料销75,插通顶料销用通孔73。
并且,在腔室52的内部,也可以设置顶料销升降构件,所述顶料销升降构件可以使顶料销75相对于衬托器,而相对地上升下降。
进一步,将本发明的衬托器71的放大示意图示于图2。图2(a)是仰视图,图2(b)是剖面图。并且,图2(c)是突出部76的一部分的放大视图。
在衬托器71上,形成有定位所载置的硅晶片的锪孔(COUNTER BORE)72,该锪孔72呈双层结构,具有支持晶片W的外周缘部的上层锪孔部72a、与在该上层锪孔部的下层且形成于中心侧的下层锪孔部72b。并且,在下层锪孔部72b的大致整个面上,形成有多个通孔74。
并且,在衬托器背面与上层锪孔部相对应的位置处,设置有突出部76(以下,也称为凸块(block))。
而且,突出部76也可以通过以下方法来形成:在衬托器背面粘合凸块状的突起物;或在形成衬托器本身时,进行背面加工,预先在衬托器背面形成突起物。
通过设置上述突出部76,由于可以使衬托器与前述上层锪孔部相对应的位置处的厚度增大,同时热容也增大,因此,此部分的温度不易上升,可以使晶片外周部与内周部的热条件固定,可以抑制背面沉积的产生,而不会损害晶片主表面的纳米拓扑品质和外周电阻率分布品质。
并且,通过使突出部76的厚度为与前述上层锪孔部相对应的位置处的除了前述突出部以外的衬托器的厚度的3倍以下,可以防止因热容差过大而导致加热时的衬托器破损。
进一步,如图2(c)所示,可以使用在前述突出部上施加有沟槽77的衬托器。并且进一步,可以使用前述沟槽77为格子状的衬托器。并且进一步,可以使用前述沟槽77的深度为与前述上层锪孔部相对应的位置处的衬托器的厚度的1/10以上的衬托器。
通过在前述突出部76上施加前述沟槽77,由于必然可以在前述突出部上产生遮挡灯管加热的部分,并且,前述沟槽77使表面积变大而易于散热,从而可以降低前述突出部的温度,因此,可以更有效地实现本发明的效果,即实现抑制背面沉积。进一步,通过使用前述沟槽77为格子状的衬托器、或使用前述沟槽77的深度为与前述上层锪孔部72a相对应的位置处的衬托器的厚度的1/10以上的衬托器,可以进一步有效地抑制背面沉积。
使用具备这种衬托器71的外延生长装置51,如下所述地,在硅晶片表面上使外延层气相生长。
首先,在工序(c)中,使用未图示的晶片转移构件,将硅晶片转移至腔室52内,并载置于衬托器71的锪孔部72上。将硅晶片载置于衬托器71上的方法,除了使用顶料销75的方法以外,可以适用一般所使用的载置方法。
其次,在自然氧化膜去除工序(d)中,在腔室52内,由氢气供给构件通过气体导入管55,向腔室52内导入氢气,利用加热构件58加热并进行氢处理,来去除硅晶片表面所产生的自然氧化膜。
其次,在工序(e)中,在硅晶片的表面上,进行外延层的气相生长。此外延层的气相生长是通过以下方法来进行:将单硅烷(monosilane)或三氯硅烷、四氯化硅等原料气体、与作为载气(carrier gas)的氢气导入至腔室52内并加热。
这样一来,可以制造一种在硅晶片的表面上形成有外延层的外延晶片。在此处所使用的外延生长装置中,由于在衬托器背面与上层锪孔部相对应的部分处,设置有突出部,使衬托器与前述上层锪孔部相对应的位置处的厚度增大,同时热容也增大,因此,可以使晶片外周部与内周部的热条件固定,可以抑制背面沉积的产生,而不会损害晶片主表面的纳米拓扑品质和外周电阻率分布品质。
以下,示出实施例,更具体地说明本发明,但本发明并不限定于此实施例。
(实施例)
在衬托器的锪孔上载置硅晶片,一边流入原料气体一边在前述硅晶片表面上进行外延层的气相生长,在以上所述的外延生长装置中,如图4所示,在一个衬托器背面的与厚度为4mm的上层锪孔部相对应的部分的圆周方向上,均等地设置厚度为3.8mm的凸块、厚度为7.6mm的凸块、施加有深度为3.8mm的沟槽且厚度为7.6mm的凸块、及未设置凸块的部分,使反应压力为常压,反应温度为1100℃,生长速度为2.7μm/min,在直径为300mm的硅晶片表面上,进行厚度为5μm的外延层的气相生长。这样一来,使除了衬托器背面有无突出部等以外的条件完全一致,可以验证本发明的效果。
此时,使用评价装置即Wafer Sight(松下电器(股)(Panasonic Corporation)制造)及UA3P(KLA-Tencor Corporation制造),分别评价距离硅晶片背面的中心的半径为145mm~149mm左右的范围,即在硅晶片背面,本发明的设置有突出部的衬托器与背面部分相对应的范围,并测定背面沉积的高度。此时,利用Wafer Sight获得的测定结果示于图3,利用UA3P获得的测定结果示于图4,并且此实验结果示于下述表1。
在此,Wafer Sight是一种测定器,它的原理是向晶片上入射光,并根据由晶片的反射光与基准面的反射光的光波干涉所产生的干扰条纹的数量与宽度,来计量晶片表面的位移量。在实际测定中,在晶片两面进行前述计量,根据预先测定的某一特定点的厚度,来计算整体的厚度变化。
并且,UA3P是根据触针式表面位移量来进行测定的测定仪器。原理是用微弱的固定负荷将探针推碰到对象上,并根据对象的凹凸,利用激光来计量动针的位移量。
表1
单位:μm
由图3、图4及表1可知,相较于背面与上层锪孔部相对应的部分处未设置凸块的现有技术的衬托器部分,设置有凸块的本发明的衬托器部分的背面沉积的高度较低。并且,当衬托器背面设置凸块时,如果该凸块的厚度为与前述上层锪孔部相对应的位置处的除了前述突出部以外的衬托器的厚度的3倍以下,能够防止因热容差过大而导致的加热时的衬托器破损。进一步,如果凸块上实施有沟槽,由于必然可以在凸块上产生遮挡灯管加热的部分,并且表面积变大而易于散热,因而可以降低凸块的温度,因此,可以进一步有效地抑制背面沉积的产生。此时,未设置凸块的部分的实验结果,与在上述外延生长条件相同的条件下,使用完全未设置突出部的现有技术的衬托器进行外延层的气相生长时相同。
另外,本发明并不限定于上述实施方式。上述实施方式为例示,具有与本发明的权利要求书所述的技术思想实质上相同的构成、并发挥相同作用效果的所有发明均包含在本发明的技术范围内。
Claims (6)
1.一种衬托器,其在进行外延层的气相生长时,支持半导体基板,其特征在于,
在该衬托器的上面,形成有内部将要配置前述半导体基板的锪孔,该锪孔呈双层结构,具有支持前述半导体基板的外周缘部的上层锪孔部、与在该上层锪孔部的下层且形成于中心侧的下层锪孔部,在前述下层锪孔部,形成有贯穿至前述衬托器的背面且在进行前述气相生长时为敞开状态的孔部,在前述衬托器的背面侧,至少在与前述上层锪孔部相对应的位置处设置有突出部。
2.如权利要求1所述的衬托器,其中,前述突出部的厚度是与前述上层锪孔部相对应的位置处的除了前述突出部以外的衬托器的厚度的3倍以下。
3.如权利要求1或2所述的衬托器,其中,在前述突出部上施加有沟槽。
4.如权利要求3所述的衬托器,其中,前述沟槽呈格子状。
5.如权利要求3或4所述的衬托器,其中,前述沟槽的深度是与前述上层锪孔部相对应的位置处的衬托器的厚度的1/10以上。
6.一种外延晶片的制造方法,其是制造外延晶片的方法,其特征在于,
其使用权利要求1至5中的任一项所述的衬托器,在该衬托器的锪孔上载置晶片,并一边流入原料气体,一边在前述晶片上进行外延层的气相生长。
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CN108475635B (zh) * | 2015-12-21 | 2022-08-02 | 昭和电工株式会社 | 晶片支承机构、化学气相沉积装置和外延晶片的制造方法 |
US11427929B2 (en) | 2015-12-21 | 2022-08-30 | Showa Denko K.K. | Wafer supporting mechanism, chemical vapor deposition apparatus, and epitaxial wafer manufacturing method |
CN106252209A (zh) * | 2016-08-30 | 2016-12-21 | 四川广瑞半导体有限公司 | 一种功率芯片用外延片生产工艺 |
CN111286723A (zh) * | 2018-12-10 | 2020-06-16 | 昭和电工株式会社 | 基座和化学气相沉积装置 |
CN110429050A (zh) * | 2019-08-05 | 2019-11-08 | 西安奕斯伟硅片技术有限公司 | 一种外延生长基座 |
CN110429050B (zh) * | 2019-08-05 | 2022-02-08 | 西安奕斯伟材料科技有限公司 | 一种外延生长基座 |
CN113699586A (zh) * | 2021-08-27 | 2021-11-26 | 江苏第三代半导体研究院有限公司 | 一种带空气桥结构的托盘及外延生长方法 |
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KR20140018189A (ko) | 2014-02-12 |
DE112011103491T5 (de) | 2013-09-26 |
JP5565472B2 (ja) | 2014-08-06 |
JPWO2012066752A1 (ja) | 2014-05-12 |
US20130180447A1 (en) | 2013-07-18 |
US9797066B2 (en) | 2017-10-24 |
KR101808054B1 (ko) | 2017-12-12 |
DE112011103491B4 (de) | 2020-09-24 |
WO2012066752A1 (ja) | 2012-05-24 |
CN103210475B (zh) | 2016-04-27 |
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