CN102956609A - 用于凸块对接合迹线比的结构和方法 - Google Patents

用于凸块对接合迹线比的结构和方法 Download PDF

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CN102956609A
CN102956609A CN2012102389227A CN201210238922A CN102956609A CN 102956609 A CN102956609 A CN 102956609A CN 2012102389227 A CN2012102389227 A CN 2012102389227A CN 201210238922 A CN201210238922 A CN 201210238922A CN 102956609 A CN102956609 A CN 102956609A
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integrated circuit
coupling post
metal
metal coupling
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CN102956609B (zh
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余振华
郭庭豪
陈承先
李明机
吴胜郁
林彦良
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种集成电路。集成电路包括形成在衬底上的互连结构；形成在互连结构上并且与互连结构连接的接合金属迹线，其中接合金属迹线包括以第一方向限定的第一宽度T；以及形成在接合金属迹线上并且与接合金属迹线对准的金属凸块柱，其中金属凸块柱包括以第一方向限定的第二宽度U，并且第二宽度U大于第一宽度T。本发明还提供用于凸块对接合迹线比的结构和方法。

Description

用于凸块对接合迹线比的结构和方法
本申请要求于2011年7月27日提交的美国临时专利申请第61/512,283号名称为“用于凸块对接合迹线比值的结构和方法”的优先权，特此将其全部内容并入本申请作为参考。
技术领域
本发明涉及集成电路，具体而言，本发明涉及用于凸块对接合迹线比的结构和方法。
背景技术
在日益发展的集成电路技术中，器件尺寸按比例缩小。各种因素降低集成电路的性能。电迁移(EM)问题受到线的后端中的凸块下金属(UBM)的结构和尺寸的影响。另一方面，为了改善EM性能而改变UBM的结构和尺寸可能导致其他问题，例如用于桥接的凸块(bump to bride bridging)。凸块疲劳性能退化了。因此，需要UBM的结构及其制造方法来解决上述问题。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种集成电路，包括：互连结构，形成在衬底上；接合金属迹线，形成在所述互连结构上并且与所述互连结构连接，其中，所述接合金属迹线包括以第一方向限定的第一宽度T；以及金属凸块柱，形成在所述接合金属迹线上并且与所述接合金属迹线对准，其中，所述金属凸块柱包括以所述第一方向限定的第二宽度U，并且所述第二宽度U大于所述第一宽度T。
在上述集成电路中，其中，所述第一宽度T和所述第二宽度U限定大于或等于0.5并小于1的T/U比。
在上述集成电路中，其中，所述第一宽度T和所述第二宽度U限定大于或等于0.5并小于1的T/U比，其中，所述T/U比大于或等于0.7并小于0.9。
在上述集成电路中，其中，所述第一宽度T和所述第二宽度U限定大于或等于0.5并小于1的T/U比，其中，所述T/U比大于或等于0.75并小于0.85。
在上述集成电路中，其中，所述金属凸块柱包括以垂直于所述第一方向的第二方向限定的长度L，并且L/U比小于2。
在上述集成电路中，还包括邻近所述接合金属迹线的相邻接合金属迹线，其中间隔S限定为所述金属凸块柱和所述相邻接合金属迹线之间的距离，以及S/T比小于0.6。
在上述集成电路中，还包括邻近所述接合金属迹线的相邻接合金属迹线，其中间隔S限定为所述金属凸块柱和所述相邻接合金属迹线之间的距离，以及S/T比小于0.6，其中，所述S/T比小于0.5。
在上述集成电路中，还包括邻近所述接合金属迹线的相邻接合金属迹线，其中间隔S限定为所述金属凸块柱和所述相邻接合金属迹线之间的距离，以及S/T比小于0.6，其中，所述S/T比小于0.4。
在上述集成电路中，还包括邻近所述接合金属迹线的相邻接合金属迹线，其中间隔S限定为所述金属凸块柱和所述相邻接合金属迹线之间的距离，以及S/T比小于0.6，其中，U/T比大于2并小于4。
在上述集成电路中，还包括邻近所述接合金属迹线的相邻接合金属迹线，其中间隔S限定为所述金属凸块柱和所述相邻接合金属迹线之间的距离，以及S/T比小于0.6，其中，U/T比大于2.5并小于3.5。
在上述集成电路中，其中，所述金属凸块柱包含铜。
在上述集成电路中，其中，所述第一方向垂直于通过所述接合金属迹线的电流的方向。
在上述集成电路中，其中，所述金属凸块柱包括来自圆柱形和圆锥形之一的形状。
在上述集成电路中，其中，所述金属凸块柱包括从上往下看选自由圆形、多边形、细长形和椭圆形组成的组的形状。
根据本发明的另一方面，还提供了一种方法，包括：在衬底上形成互连结构；在所述互连结构上形成接合金属迹线，其中，所述接合金属迹线包括以第一方向限定的第一宽度T；以及在所述接合金属迹线上形成金属凸块柱，其中，所述金属凸块柱包括以所述第一方向限定的第二宽度U，并且所述第二宽度U大于所述第一宽度T。
在上述方法中，其中，所述金属凸块柱的形成包括通过沉积和电镀中的至少一种形成铜柱。
在上述方法中，还包括在所述衬底上形成各种集成电路器件。
在上述方法中，其中，所述金属凸块柱的形成包括形成具有大于或等于0.5并小于1的T/U比的金属凸块柱。
在上述方法中，其中，所述金属凸块柱的形成包括形成具有选自圆柱形和圆锥形之一的形状的金属凸块柱。
在上述方法中，其中，所述金属凸块柱的形成包括形成具有从上往下看选自圆形、多边形、细长形和椭圆形组成的组的形状的金属凸块柱。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制。实际上，为了清楚论述起见，各种部件的尺寸可以被任意增大或减小。
图1示出在一个或多个实施例中根据本发明各个方面构建的集成电路的接合结构的截面图。
图2示出根据一个或多个实施例的图1的集成电路的透视图。
图3示出在一个或多个实施例中根据本发明各个方面构建的集成电路的接合结构的截面图。
图4示出根据一个或多个实施例的图3的集成电路的俯视图。
图5示出根据各个实施例的金属凸块柱的透视图。
图6示出根据各个实施例的金属凸块柱的俯视图。
具体实施方式
可以理解为了实施本发明的不同部件，以下公开内容提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不打算用于限定。另外，本发明可能在各个实例中重复附图编号和/或字母。这种重复是为了简明和清楚的目的且其本身并没有表明所论述的各个实施例和/或结构之间的关系。此外，在以下描述中第一部件在第二部件上方或者在第二部件上的形成可以包括其中第一部件和第二部件以直接接触形成的实施例，并且也可包括其中在第一部件和第二部件之间形成额外的部件，使得第一部件和第二部件可以不直接接触的实施例。
图1示出在一个或多个实施例中根据本发明各个方面构建的集成电路10的接合结构的截面图。图2示出根据一个或多个实施例的集成电路10的透视图。参照图1和图2一起描述集成电路10及其制造方法。
在诸如硅衬底的半导体衬底(未示出)上形成集成电路10。可选地或者另外地，衬底包含锗、硅锗或者其他适当的半导体材料。半导体衬底也可以包括在衬底中形成的用于分隔各个器件的各种隔离部件，例如浅沟槽隔离(STI)。半导体衬底还包括各种掺杂区，例如n阱和p阱。
集成电路10还包括各种器件，例如晶体管、二极管、电阻器、电容器、传感器、存储单元或者其他合适的IC器件。在一个实例中，集成电路10包括场效应晶体管(具有形成在半导体衬底中的源极和漏极部件)，还包括形成在半导体衬底上并设置在源极和漏极部件之间的栅极堆叠件，源极和漏极部件被配置成形成功能晶体管。
集成电路10还包括具有各种金属层的互连结构。互连结构包括形成在金属层中的金属线和接触部件以及通孔部件。接触部件将掺杂部件和/或栅电极连接至相应的金属线，而通孔部件连接位于邻近金属层中的金属线。互连结构被配置成连接各种掺杂部件和导电部件以形成各种器件，导致集成在半导体衬底上的一个或多个功能电路。
具体而言，集成电路10包括将各种IC器件连接至封装件(或者封装基板)并且进一步连接至输入/输出信号和电源的各种接合结构。在一个实例中，部件42是具有器件和互连结构的一部分衬底而部件45是封装基板的一部分。
为了简明，图1仅示出一个接合结构。接合结构包括适当地连接至互连结构的接合金属迹线(landing metal trace)20并且还包括与接合金属迹线20对准并且位于接合金属迹线20上面的金属凸块柱(或者金属柱)40。在一个实施例中，可以在接合金属迹线20和金属凸块柱40之间设置各种导电部件。在该实施例中，T/U比低于0.6。
图3示出在一个或多个实施例中根据本发明各个方面构建的集成电路50的接合结构的截面图。图4示出根据一个或多个实施例的集成电路50的俯视图。参照图3和图4一起描述集成电路50及其制备方法。也在衬底诸如半导体衬底上形成集成电路50。集成电路50也包括各种器件和互连结构。
集成电路50包括将各种IC器件连接至封装件并且进一步连接至输入/输出信号和电源的各种接合结构。为了简明，图3仅示出一个接合结构。接合结构包括适当地连接至互连结构的接合金属迹线20并且还包括与接合金属迹线20对准并且位于接合金属迹线20上面的金属凸块柱40。在一个实例中，金属凸块柱40包含通过溅射、电镀或者它们的组合形成的铜。
接合金属迹线20限定图4中标记为“T”的宽度。以与通过接合金属迹线20的电流方向垂直的方向限定和跨越宽度T。金属凸块柱40限定图4中标记为“U”的宽度以及标记为“L”的长度。宽度U被限定为垂直于接合金属迹线布线方向的尺寸。在金属凸块柱和邻近的接合金属迹线之间限定间隔“S”，如图3和图4所示。长度L被限定为以电流的第一方向跨越。宽度U和T被限定为以垂直于第一方向的第二方向跨越。具体而言，根据本实施例，金属凸块柱20的宽度U大于接合金属迹线20的宽度T。
在又一实施例中，L/U比小于2即，L/U＜2。T/U比范围为0.5＝＜T/U＜1。可选地，T/U比范围为0.7＝＜T/U＜0.9，或者0.75＝＜T/U＜0.85。S/T比范围为S/T＜0.6。可选地，S/T比范围为S/T＜0.5，或者S/T＜0.4。比值U/S范围为2＜U/S＜4。可选地，比值U/S范围为2.5＜U/S＜3.5。
公开的结构的设计考虑以本发明发现的问题为基础。一个问题是在接合金属迹线20和金属凸块柱40之间的界面处可能发生的桥接风险。另一问题是电迁移(EM)。在设计考虑中，平均故障间隔时间(MTTF)由等式MTTF＝A(l/fn)xexp(Q/kT)来确定。集成电路50有效地消除或者减少桥接风险。集成电路50还降低了EM问题并且提高了电路性能。
图5示出可以合并到根据各个实施例的图3和图4的集成电路50中的金属凸块柱40的透视图。金属凸块柱40可以具有圆柱形、圆锥形或者其他合适的形状，例如图5中示出的形状。
图6示出可以合并到根据各个实施例的图3和图4的集成电路50中的金属凸块柱40的俯视图。金属凸块柱40可以具有不同的几何形状，例如圆形、多边形、细长形、椭圆形或者图6中示出的其他合适的形状。
虽然本发明的实施例已经详细描述，但本领域的技术人员应该理解，可以在不背离本发明的精神和范围的情况下，进行各种改变、替换和更改。例如，本发明不限于特别的应用。在一个实例中，集成电路50可以包括各种IC结构，例如场效应晶体管、动态随机存取存储(DRAM)单元、现场可编程门阵列(FPGA)和/或其他微电子器件。当然，本发明的各个方面可以用于许多不同的应用，包括传感器单元、逻辑单元等。
因此，本发明提供了集成电路的一个实施例。该集成电路包括形成在衬底上的互连结构；形成在互连结构上并且与互连结构连接的接合金属迹线，其中接合金属迹线包括以第一方向限定的第一宽度T；以及形成在接合金属迹线上并且与接合金属迹线对准的金属凸块柱，其中金属凸块柱包括以第一方向限定的第二宽度U，并且第二宽度U大于第一宽度T。
在集成电路的一个实施例中，第一宽度T和第二宽度U限定大于或等于0.5并且小于1的第一比值T/U。在另一实施例中，第一比值T/U大于或等于0.7并且小于0.9。在又一实施例中，第一比值T/U大于或等于0.75并且小于0.85。
在另一实施例中，金属凸块柱包括以垂直于第一方向的第二方向限定的长度L，第二比值L/U小于2。
在又一实施例中，集成电路还包括邻近接合金属迹线的相邻接合金属迹线，其中间隔S限定为金属凸块柱和相邻接合金属迹线之间的距离，并且第三比值S/T小于0.6。
在又一实施例中，第三比值S/T小于0.5。在又一实施例中，第三比值S/T小于0.4。在又一实施例中，第四比值U/S大于2并且小于4。在又一实施例中，第四比值U/S大于2.5并且小于3.5。
在又一实施例中，金属凸块柱包含铜。在又一实施例中，第一方向垂直于通过接合金属迹线的电流的方向。
在又一实施例中，金属凸块柱包括圆柱形和圆锥形之一的形状。
在又一实施例中，金属凸块柱包括选自由从上往下看为圆形、多边形、长形和椭圆形组成的组的形状。
本发明还提供了方法的一个实施例。该方法包括在衬底上形成互连结构；在互连结构上形成接合金属迹线，其中接合金属迹线包括以第一方向限定的第一宽度T；以及在接合金属迹线上形成的金属凸块柱，其中金属凸块柱包括以第一方向限定的第二宽度U，并且第二宽度U大于第一宽度T。
在方法的一个实施例中，金属凸块柱的形成包括通过沉积和电镀中的至少一种形成铜柱。
在另一实施例中，该方法还包括在衬底上形成各种集成电路器件。
在又一实施例中，金属凸块柱的形成包括形成具有大于或等于0.5并且小于1的第一比值T/U的金属凸块柱。
在又一实施例中，金属凸块柱的形成包括形成具有选自圆柱形和圆锥形之一的形状的金属凸块柱。
在又一实施例中，金属凸块柱的形成包括形成具有选自从上往下看为圆形、多边形、细长形和椭圆形组成的组的形状的金属凸块柱。
上面论述了若干实施例的部件。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种集成电路，包括：
互连结构，形成在衬底上；
接合金属迹线，形成在所述互连结构上并且与所述互连结构连接，其中，所述接合金属迹线包括以第一方向限定的第一宽度T；以及
金属凸块柱，形成在所述接合金属迹线上并且与所述接合金属迹线对准，其中，所述金属凸块柱包括以所述第一方向限定的第二宽度U，并且所述第二宽度U大于所述第一宽度T。
2.根据权利要求1所述的集成电路，其中，所述第一宽度T和所述第二宽度U限定大于或等于0.5并小于1的T/U比。
3.根据权利要求2所述的集成电路，其中，所述T/U比大于或等于0.7并小于0.9。
4.根据权利要求2所述的集成电路，其中，所述T/U比大于或等于0.75并小于0.85。
5.根据权利要求1所述的集成电路，其中，所述金属凸块柱包括以垂直于所述第一方向的第二方向限定的长度L，并且L/U比小于2。
6.一种方法，包括：
在衬底上形成互连结构；
在所述互连结构上形成接合金属迹线，其中，所述接合金属迹线包括以第一方向限定的第一宽度T；以及
在所述接合金属迹线上形成金属凸块柱，其中，所述金属凸块柱包括以所述第一方向限定的第二宽度U，并且所述第二宽度U大于所述第一宽度T。
7.根据权利要求6所述的方法，其中，所述金属凸块柱的形成包括通过沉积和电镀中的至少一种形成铜柱。
8.根据权利要求6所述的方法，还包括在所述衬底上形成各种集成电路器件。
9.根据权利要求6所述的方法，其中，所述金属凸块柱的形成包括形成具有大于或等于0.5并小于1的T/U比的金属凸块柱。
10.根据权利要求6所述的方法，其中，所述金属凸块柱的形成包括形成具有选自圆柱形和圆锥形之一的形状的金属凸块柱。
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CN102956609B (zh) 2015-12-16
US8981576B2 (en) 2015-03-17
KR101366401B1 (ko) 2014-02-24
US8643196B2 (en) 2014-02-04
TWI474438B (zh) 2015-02-21
TW201306175A (zh) 2013-02-01

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