TWI474438B - 積體電路及其製造方法 - Google Patents

積體電路及其製造方法 Download PDF

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TWI474438B
TWI474438B TW101125104A TW101125104A TWI474438B TW I474438 B TWI474438 B TW I474438B TW 101125104 A TW101125104 A TW 101125104A TW 101125104 A TW101125104 A TW 101125104A TW I474438 B TWI474438 B TW I474438B
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integrated circuit
width
metal
metal bump
forming
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TW201306175A (zh
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Chen Hua Yu
Tin Hao Kuo
Chen Shien Chen
Mirng Ji Lii
sheng yu Wu
Yen Liang Lin
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Taiwan Semiconductor Mfg Co Ltd
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Description

積體電路及其製造方法
本發明係有關於一種積體電路技術，特別是有關於一種積體電路及其製造方法。
在先進的積體電路技術中，裝置尺寸不斷縮小。各種不同的因素降低積體電路的效能。後段製程中凸塊下方金屬(under bump metal,BUM)的尺寸及結構影響了電子遷移(electro-migration,EM)問題。另一方面，若想改善電子遷移效能而改變UBM的結構及尺寸，將會引起其他的問題，例如凸塊架橋。因而降低凸塊疲勞效能。因此，需要一種UBM結構及其製造方法，以解決上述問題。
在本發明一實施例中，一種積體電路，包括：一內連結構，形成於一基底上；一接合金屬走線，形成於內連結構上，且耦接至內連結構，其中接合金屬走線包括沿一第一方向所定義出的一第一寬度T；以及一金屬凸塊柱體，形成於接合金屬走線上，且與其對準，其中金屬凸塊柱體包括沿第一方向所定義出的一第二寬度U，且第二寬度U大於第一寬度T。
在本發明另一實施例中，一種積體電路之製造方法，包括：在一基底上形成一內連結構；在內連結構上形成一接合金屬走線，其中接合金屬走線包括沿一第一方向所定義出的一第一寬度T；以及在接合金屬走線上形成一金屬凸塊柱體，其中金屬凸塊柱體包括沿第一方向所定義出的 一第二寬度U，且第二寬度U大於第一寬度T。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明各種不同實施例的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。再者，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。
第1圖係繪示出根據本發明一或多個實施例中各種不同形態之積體電路10之接合結構剖面示意圖。第2圖係繪示出第1圖中積體電路10之立體示意圖。以下配合第1及2圖來一同說明積體電路10及其製造方法。
積體電路10形成於一半導體基底(未繪示)上，例如一矽基底。另外，基底也包括鍺、矽化鍺或其他適當的半導體材料。半導體基底也包括各種不同的隔離特徵部件，例如，淺溝槽隔離(shallow trench isolation,STI)，其形成於基底內，以隔開各種不同的元件。半導體基底也包括各種不同的摻雜區，例如，n型井區及p型井區。
積體電路10更包括各種不同的裝置，例如，電晶體、二極體、電阻、電容、感測器、記憶單元或其他適當的積體電路裝置。在一範例中，積體電路10包括場效電晶體，其具有源極及汲極特徵部件形成於半導體基底內，且更包括一閘極疊層形成於半導體基底上，並設置於源極及汲極特徵部件之間，而構成一功能電晶體。
積體電路10也包括一內連結構，其具有不同的金屬層。內連結構包括形成於金屬層內的金屬線、接觸(contact)特徵部件及介層連接(via)特徵部件。接觸部件將摻雜特徵部件及/或閘極電極連接至對應的金屬線，而介層連接特徵部件則連接相鄰的金屬層內的金屬線。內連結構的配置係耦接各種不同的摻雜特徵部件及導電特徵部件，以構成不同的裝置，而在半導體基底上形成一或多個功能電路。
特別的是積體電路10包括各種不同的接合結構，以將各種不同的積體電路裝置耦接至封裝體(或封裝基底)，且進一步耦接至輸入/輸出信號及電源。在一範例中，特徵部件42為具有裝置及內連結構的基底的一部分，而特徵部件45為封裝基底的一部分。
為了簡化圖式，第1圖僅繪示出一接合結構。接合結構包括耦接至內連結構的一接合金屬走線(landing metal trace)20，且更包括對準且位於接合金屬走線20上方的一金屬凸塊柱體(或金屬柱體)40。在一實施例中，不同導電特徵部件可設置於接合金屬走線20與金屬凸塊柱體40之間。在本實施例中，比率T/U低於0.6。
第3圖係繪示出根據本發明一或多個實施例中各種不 同形態之積體電路50之接合結構剖面示意圖。第4圖係繪示出第3圖中積體電路50之平面示意圖。以下配合第3及4圖來一同說明積體電路50及其製造方法。積體電路50同樣形成於一基底上，例如半導體基底。積體電路50同樣包括各種不同的裝置及一內連線結構。
積體電路50包括各種不同的接合結構，以將各種不同的積體電路裝置耦接至封裝體，且進一步耦接至輸入/輸出信號及電源。為了簡化圖式，第3圖僅繪示出一接合結構。接合結構包括耦接至內連結構的一接合金屬走線20，且更包括對準且位於接合金屬走線20上方的一金屬凸塊柱體40。在一實施例中，金屬凸塊柱體40包括銅且可透過濺鍍、電鍍或其組合而形成。
接合金屬走線20定義出一寬度，如第4圖中所標示的”T”。寬度T的定義為跨越於流經接合金屬走線20的電流路徑方向的垂直方向。金屬凸塊柱體40定義出一寬度及一長度，如第4圖中所標示的”U”及”L”。寬度U的定義為垂直於接合金屬走線延伸方向的尺寸。金屬凸塊柱體與鄰近的接合金屬走線之間定義出一間隔”S”，如第3及4圖所示。長度L的定義為跨越於電流的一第一方向。特別的是根據本實施例，金屬凸塊柱體40的寬度U大於接合金屬走線20的寬度T。
又在一實施例中，比率L/U小於2(L/U<2)。比率T/U為0.5=<T/U<1。另外，比率T/U也可為0.7=<T/U<0.9或者為0.75=<T/U<0.85。比率S/T為<0.6。另外，比率S/T也可為<0.5或者為<0.4。比率U/S為2<U/S<4。另外，比 率U/S也可為2.5<U/S<3.5。
以上所述的結構的設計考量取決於本說明書所發現的問題。其一為架橋風險，其可能發生於接合金屬走線20與金屬凸塊柱體40之間的界面。另一則為電子遷移(EM)。在設計考量中，平均故障間隔時間(mean time between failure,MTBF)由一方程式所決定，其公式為MTBF=A(1×fn )×exp(Q/kT)。積體電路50有效排除或降低架橋風險。積體電路50進一步降低EM問題並提升電路效能。
第5圖係繪示出根據本發明不同實施例之金屬凸塊柱體40立體示意圖，金屬凸塊柱體40可併入於第3及4圖的積體電路50中。金屬凸塊柱體40可具有不同的幾何形貌，例如，圓柱型、圓錐型或其他適合外型，例如第5圖所示。
第6圖係繪示出根據本發明不同實施例之金屬凸塊柱體40平面示意圖，金屬凸塊柱體40可併入於第3及4圖的積體電路50中。金屬凸塊柱體40可具有不同的上視幾何形貌，例如，圓形、多邊形、長條形、橢圓形或其他適合形狀，例如第6圖所示。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，本發明並未限定於特定應用。在一範例中，積體電路50可包括部同的積體電路結構，例如，場效電晶體、動態隨機存取記憶體(DRAM)單元、場效可編程閘極陣列(field programmable gate-array,FPGA)及/或其他 微電子裝置。當然，本發明的型態可實施於許多不同的應用，包括感測器單元、邏輯單元及其他。
因此，本發明實施例提供一種積體電路。積體電路包括：一內連結構，形成於一基底上；一接合金屬走線，形成於內連結構上，且耦接至內連結構，其中接合金屬走線包括沿一第一方向所定義出的一第一寬度T；以及一金屬凸塊柱體，形成於接合金屬走線上，且與其對準，其中金屬凸塊柱體包括沿第一方向所定義出的一第二寬度U，且第二寬度U大於第一寬度T。
在積體電路的一實施例中，第一寬度T及第二寬度U定義出一第一比率(T/U)，其大於或等於0.5且小於1。在另一實施例中，第一比率(T/U)大於或等於0.7且小於0.9。又一實施例中，第一比率(T/U)大於或等於0.75且小於0.85。
在另一實施例中，金屬凸塊柱體包括沿垂直於第一方向的一第二方向所定義出的一長度L，且一第二比率(L/U)小於2。
又另一實施例中，積體電路更包括一相鄰接合金屬走線，鄰近於接合金屬走線，其中一間隔S定義為金屬凸塊柱體與相鄰接合金屬走線之間的一距離，且一第三比率(S/T)小於0.6。
又另一實施例中，第三比率(S/T)小於0.5。又另一實施例中，第三比率(S/T)小於0.4。又另一實施例中，一第四比率(U/S)大於2且小於4。又另一實施例中，第四比率(U/S)大於2.5且小於3.5。
又另一實施例中，金屬凸塊柱體包括銅。又另一實施例中，第一方向垂直於電流通過接合金屬走線的一方向。
又另一實施例中，金屬凸塊柱體的外型為圓柱型及圓椎型的其中一者。
又另一實施例中，金屬凸塊柱體的上視形狀係擇自於由圓形、多邊形、長條形及橢圓形所組成的群組。
本發明實施例也提供一種積體電路之製造方法。積體電路之製造方法包括：在一基底上形成一內連結構；在內連結構上形成一接合金屬走線，其中接合金屬走線包括沿一第一方向所定義出的一第一寬度T；以及在接合金屬走線上形成一金屬凸塊柱體，其中金屬凸塊柱體包括沿第一方向所定義出的一第二寬度U，且第二寬度U大於第一寬度T。
在一積體電路之製造方法實施例中，形成金屬凸塊柱體的步驟包括以沉積及電鍍至少一者來形成一銅柱體。
在另一實施例中，積體電路之製造方法更包括在基底上形成各種不同的積體電路裝置。
又另一實施例中，形成金屬凸塊柱體的步驟包括形成具有一第一比率(T/U)大於或等於0.5且小於1的一金屬凸塊柱體。
又另一實施例中，形成金屬凸塊柱體的步驟包括形成具有一外型為圓柱型及圓椎型其的中一者的一金屬凸塊柱體。
又另一實施例中，形成金屬凸塊柱體的步驟包括形成具有一上視形狀擇自於由圓形、多邊形、長條形及橢圓形 所組成的群組的一金屬凸塊柱體。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於後續本發明的詳細說明可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到本說明書可輕易作為其它結構或製程的變更或設計基礎，以進行相同於本發明實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本發明之精神和保護範圍內，且可在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。
10、50‧‧‧積體電路
20‧‧‧接合金屬走線
40‧‧‧金屬凸塊柱體
42、45‧‧‧特徵部件
L‧‧‧長度
S‧‧‧間隔
T、U‧‧‧寬度
第1圖係繪示出根據本發明一或多個實施例中各種不同形態之積體電路之接合結構剖面示意圖；第2圖係繪示出第1圖中積體電路之立體示意圖；第3圖係繪示出根據本發明一或多個實施例中各種不同形態之積體電路之接合結構剖面示意圖；第4圖係繪示出第3圖中積體電路之平面示意圖；第5圖係繪示出根據本發明不同實施例之金屬凸塊柱體立體示意圖；第6圖係繪示出根據本發明不同實施例之金屬凸塊柱體平面示意圖。
10‧‧‧積體電路
20‧‧‧接合金屬走線
40‧‧‧金屬凸塊柱體
42、45‧‧‧特徵部件
S‧‧‧間隔
T、U‧‧‧寬度

Claims (8)

  1. 一種積體電路，包括：一內連結構，形成於一基底上；一接合金屬走線，形成於該內連結構上，且耦接至該內連結構，其中該接合金屬走線包括沿一第一方向所定義出的一第一寬度T；以及一金屬凸塊柱體，形成於該接合金屬走線上，且與其對準，其中該金屬凸塊柱體包括沿該第一方向所定義出的一第二寬度U，且該第二寬度U大於該第一寬度T，以及其中該第一寬度T對該第二寬度U的比率(T/U)大於或等於0.5且小於1。
  2. 如申請專利範圍第1項所述之積體電路，其中該金屬凸塊柱體包括沿垂直於該第一方向的一第二方向所定義出的一長度L，且該長度L對該第二寬度U的比率(L/U)小於2。
  3. 如申請專利範圍第1項所述之積體電路，更包括一相鄰接合金屬走線，鄰近於該接合金屬走線，其中一間隔S定義為該金屬凸塊柱體與該相鄰接合金屬走線之間的一距離，且一比率(S/T)小於0.6。
  4. 如申請專利範圍第3項所述之積體電路，其中一比率(U/S)大於2且小於4。
  5. 如申請專利範圍第1項所述之積體電路，其中該第一方向垂直於電流通過該接合金屬走線的一方向。
  6. 如申請專利範圍第1項所述之積體電路，其中該金屬凸塊柱體的外型為圓柱型及圓椎型的其中一者，且該金 屬凸塊柱體的上視形狀係擇自於由圓形、多邊形、長條形及橢圓形所組成的群組。
  7. 一種積體電路之製造方法，包括：在一基底上形成一內連結構；在該內連結構上形成一接合金屬走線，其中該接合金屬走線包括沿一第一方向所定義出的一第一寬度T；以及在該接合金屬走線上形成一金屬凸塊柱體，其中該金屬凸塊柱體包括沿該第一方向所定義出的一第二寬度U，且該第二寬度U大於該第一寬度T，以及其中形成該金屬凸塊柱體的步驟包括形成具有一比率(T/U)大於或等於0.5且小於1的一金屬凸塊柱體。
  8. 如申請專利範圍第7項所述之積體電路之製造方法，其中形成該金屬凸塊柱體的步驟包括形成具有一外型為圓柱型及圓椎型其中一者的一金屬凸塊柱體，且包括形成具有一上視形狀擇自於由圓形、多邊形、長條形及橢圓形所組成的群組的一金屬凸塊柱體。
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