CN102934224B - 微电子封装及其制造方法 - Google Patents

微电子封装及其制造方法 Download PDF

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Publication number
CN102934224B
CN102934224B CN201180027667.5A CN201180027667A CN102934224B CN 102934224 B CN102934224 B CN 102934224B CN 201180027667 A CN201180027667 A CN 201180027667A CN 102934224 B CN102934224 B CN 102934224B
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tube core
tube
microelectronics packaging
techonosphere
rear side
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CN102934224A (zh
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R·K·纳拉
M·J·曼努沙洛
D·德莱尼
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Intel Corp
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Intel Corp
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Abstract

微电子封装包括基板（110），嵌入到基板内的管芯（120），其中管芯具有前侧（121）和后侧（122）并且还具有位于其中的穿过硅的通孔（123），构造在管芯前侧上的构造层（130），以及与管芯后侧物理接触的电源面（140）。在另一个实施例中，微电子封装包括基板（210），第一管芯（220）和第二管芯（260），其中两个管芯嵌入到基板中，两个管芯具有前侧（221,261）和后侧（222,262），并且两个管芯内具有穿过硅的通孔（223,263），在第一和第二管芯的前侧上的构造层（230），以及与第一和第二管芯的后侧物理接触的导电结构（240）。

Description

微电子封装及其制造方法
发明领域
所公开的本发明的实施例一般涉及微电子封装，更具体地涉及无凸块（bumpless）构造层封装。
发明背景
无凸块构造层（BBUL）是微电子器件的封装技术，其中封装包括嵌入到基板中的至少一个管芯（亦称为“芯片”），有一个或多个构造层形成在基板上。构造层和管芯接合焊盘之间的电连接可通过使用标准微通孔形成工艺制成。BBUL封装实现了小的电环路电感并对低介电常数（低k）管芯材料的减小的热机械应力。它们还允许高引线数目、易于集成多个电子和光学组件（诸如逻辑、存储器、射频（RF）以及微机电系统（MEMS）等等）、以及固有的可伸缩性。BBUL封装的现有工艺流程涉及在用铜箔覆盖的临时芯/载体上构建基板，该铜箔在封装与芯/载体分离后被蚀刻掉。
附图简述
通过阅读以下的详细描述并结合附图可以更好地理解所公开的实施例，在附图中：
图1A和图1B分别是根据本发明实施例的微电子封装的平面图和截面图；
图2A和图2B分别是根据本发明另一实施例的微电子封装的平面图和截面图；
图3是根据本发明实施例的多芯片封装的截面图；
图4是示出根据本发明实施例的制造微电子封装的方法的流程图；
图5是根据本发明实施例的微电子封装的一部分在其制造过程中在一特定点上的截面图；以及
图6是根据本发明实施例的图5的微电子封装的一部分在其制造过程中在一后续点上的截面图。
为了说明简洁，附图示出一般的构造方式，且省略公知特征和技术的描述和细节，以避免不必要地使对本发明所述实施例的讨论晦涩。此外，附图中的各要素不一定按比例绘制。举例而言，附图中一些要素的尺寸可能相对于其它要素被放大来帮助改善对本发明各实施例的理解。不同附图中的相同附图标记表示相同要素，而类似附图标记可能但不一定表示类似要素。
在说明书和权利要求书中的术语“第一”、“第二”、“第三”、“第四”等（如果有的话）用于在类似元件之间进行区分，且未必是用于描述特定次序或时间顺序。要理解，在适当情况下如此使用的这些术语可互换，例如使得本文所述的本发明实施例能够以不同于本文所述或所示的其它顺序来操作。类似地，如果本文所述的方法包括一系列步骤，则本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些所陈述的步骤可被省略和/或一些本文未描述的其它步骤可被添加到该方法。此外，术语“包括”、“包含”、“具有”及其任何变形旨在适用非排他地包括，使得包括一系列要素的过程、方法、制品或装置不一定限于那些要素，但可包括未明确列出的或这些过程、方法、制品或装置所固有的其它要素。
在说明书和权利要求书中,术语“左”、“右”、“前”、“后”、“顶”、“底”、“上”、“下”等如果出现，则用于描述的目的，且不一定用于描述永久的相对位置，除非明确地或者根据上下文另外说明。应该理解如此使用的术语在适当情况下是可以互换的，使得本文所述的本发明的实施例例如能够以本文示出或以其它方式描述的方向以外的其它方向操作。如本文所使用的术语“耦合”被定义为以电气或非电气方式的直接或间接连接。在本文中描述为彼此“相邻”的物体按照适于使用该短语的上下文可以在物理上彼此接触、彼此紧邻或彼此处于同一通用区域或区中。在本文中短语“在一个实施例中”的出现不一定全指同一实施例。
附图详细描述
在本发明的一个实施例中，微电子封装包括基板，嵌入到基板内的管芯（在本文中亦可称为芯片）——管芯具有前侧和相对的后侧并且还具有位于其中的至少一个穿过硅的通孔，邻近于管芯前侧并在管芯前侧上构造的多个构造层，以及邻近于管芯后侧并与管芯后侧物理接触的电源面。在另一个实施例中，微电子封装包括基板，第一管芯和第二管芯，其中两个管芯均嵌入到基板中，两个管芯均具有前侧和相对的后侧，并且两个管芯内均具有位于其中的至少一个穿过硅的通孔，邻近于第一与第二管芯的前侧并在第一与第二管芯的前侧上构造的多个构造层，以及邻近于第一与第二管芯的后侧并与第一与第二管芯的后侧物理接触的导电结构。
如以下讨论将阐明的，本发明的实施例实现了管芯的有源侧上的电源凸块（或其它种类的凸块）的数量的减少，从而便于管芯尺寸的减小。另外，本发明的实施例实现了可被称为管芯下电源上（Die-DownPower-Up，DDPU）系统的系统，除了其它优点，该系统还提供较好的第二级互连（SLI）返回路径优化，使输入/输出（I/O）元件的信号地面比（signal-to-ground）的增大成为可能，并且消除了I/O与电源之间的麻烦的折衷。本发明的相同或其它实施例实现了封装中多个管芯之间的可达到的I/O密度的增大。
现在参见附图，图1A和图1B分别是根据本发明实施例的微电子封装100的平面图和截面图。图1B是沿图1A中的线B-B获取的。如图1A和图1B所示，微电子封装100包括基板110和管芯120，管芯120嵌入到基板110内。管芯120具有前侧121（即，晶体管（未示出）所位于的那一侧）以及相对的后侧122。管芯120中还具有位于其中的穿过硅的通孔（TSV）123，TSV123一直延伸到后侧122并且在后侧122暴露。基板110包括多个构造层130（其中一个是介电层139），所述多个构造层130邻近于管芯120的前侧121并在管芯120的前侧121上（以及周围）构造。
微电子封装100还包括电源面140，电源面140邻近于管芯120的后侧122并与管芯120的后侧122物理接触。电源面140的厚度可以是由微电子封装100的功率输送要求所规定的。电源面140的存在实现了前侧121上的电源凸块（或I/O凸块或可能的哑凸块（dummybump））的数量的减少，以及管芯120的尺寸的相应减小，因为所需要的凸块中的一些可能替代地在某位置中（后侧122）的电源面140内形成，所述位置是之前未使用或浪费的空间。换言之，通过将一些电源凸块或其它凸块移动到后侧122，本发明的实施例在不对电源和I/O能力进行折衷的情况下实现了管芯覆盖区域的减小。另外，本发明的实施例允许电源电路从管芯底部或从管芯顶部（或这两者）引入到管芯中，但是以前所有电源必须从底部引入。（即使电源被引入封装的顶侧，这也是正确的；即，顶侧封装电源需要从管芯底侧被布线到管芯且引入管芯。）本发明的实施例消除了该需要，并且替代地实现了双侧功能部件，而之前仅有的功能部件都是单侧的。
如所述，本发明的实施例实现了DDPU系统，其中电源从有源器件所在位置的相对侧引入管芯。同样如所述，DDPU系统通过提供更多凸块（甚至在较小覆盖区域中）而具有诸如改善的SLI返回路径优化以及增大的I/O信号地面比之类的优点。
电源面140位于后侧122的TSV123的暴露部分的顶部上，这意味着在电源面140和TSV123之间可制作连接（并从该处到管芯120的其它部件），而不需要在后侧122处的任何连接凸块。在一个实施例中，电源面140包括铜，该材料与现有设备和技术工艺是兼容的。在例示实施例中，微电子封装100还包括位于电源面140上的保护层150，以便保护电源面免受机械或环境损伤（诸如氧化之类）等。（为了使例示更加清楚，保护层150未在图1A中示出。）作为示例，保护层150可以是氧化铝或类似层，这些层作为被执行以减少侵蚀等的化学处理的结果而形成。作为另一示例，保护层150可以是由聚合物材料、纤维增强塑料等制成的包覆模制（overmold）。
尽管在图1A和图1B中未示出，电源面140可在某些实施例中用作一个或多个无源组件（例如，电容器、电感器等）的附连点。在这些（或其它）未例示实施例中的一些实施例中，电源面140中可具有位于其中的凹部，该凹部包围管芯120的部分或全部。该凹入配置允许减小微电子封装100的总厚度（通常被称为Z-高度），使得除了其它优点外，它还能与具有较小形状因数的器件和产品兼容。
图1A示出管芯120的周界124。图1B仅示出周界124的两个端点125，并且仅示出该周界穿过基板110的延伸的外部边界126。该延伸（或覆盖区域）限定管芯区域127，管芯区域127的横向延伸在图1B中示出。可以看出构造层130包含在管芯区域127外的多个通孔131以及在管芯区域127内的多个通孔132。在所示实施例中，通孔131将电源面140和基板110彼此电连接，并且通孔132将管芯120和基板110彼此电连接。
在管芯区域127外的通孔131需要较大的钻孔尺寸，因为它们穿透较厚的电介质，换言之，它们是较长的。在该方面，上述凹入配置的附加优点是它将减小POP通孔（通孔131）的纵横比，从而使那些通孔更加易于制造且制造成本更低。通孔132较短，因为它们仅须到达管芯120而不是一直到达载体140。因此，用于通孔132的激光器可比用于通孔131的激光器小。作为示例，可通过使用半添加工艺（SAP）技术、激光投影图案化（LPP）技术或任何其它合适的通孔形成技术来产生通孔。
图2A和图2B分别是根据本发明实施例的微电子封装200的平面图和截面图。图2B是沿图2A中的线B-B获取的。如图2A和图2B所示，微电子封装200包括基板210以及嵌入到基板210中的管芯220和管芯260。管芯220具有前侧221（即，晶体管（未示出）所位于的那一侧）以及相对的后侧222。管芯220中还具有位于其中的TSV223，TSV223一直延伸到后侧222并且在后侧222暴露。类似地，管芯260具有前侧261（再一次，晶体管（未示出）所位于的那一侧）以及相对的后侧262。管芯260中还具有位于其中的TSV263，TSV263一直延伸到后侧262并且在后侧262暴露。基板210包括多个构造层230（其中一个是介电层239），所述多个构造层230邻近于管芯220和260的前侧221和261并在管芯220和260的前侧221和261上（以及周围）构造。
微电子封装200还包括导电结构240，导电结构240邻近于管芯220的后侧222和管芯260的后侧262并与管芯220的后侧222和管芯260的后侧262物理接触。在所示实施例中，导电结构240包括互连241（例如，I/O管芯内连接），互连241将管芯220的后侧222和管芯260的后侧262彼此电连接。导电结构240还包括可用于管芯堆叠的管芯连接焊盘242。（以下将进一步讨论根据本发明实施例的管芯堆叠，包括管芯连接焊盘242的作用。）
在一个实施例中，导电结构240包括铜。在同一或另一实施例中，微电子封装200还包括导电结构240上的保护层250，以便保护导电结构免受机械或环境损伤等。（为了使例示更加清楚，保护层250未在图2A中示出。）作为示例，保护层250可类似于图1A和图1B中所示的保护层150。
在一个实施例中，导电结构240中可具有位于其中的凹部（未示出），该凹部包围管芯220和260的部分或全部。在某些实施例中，导电结构240可包含用于每个管芯的单独凹部。
管芯220和260（包括它们之间的区域）的延伸（或覆盖区域）限定管芯区域227，管芯区域227的横向延伸在图2B中示出。可以看出构造层230包含在管芯区域227外的多个通孔231以及在管芯区域227内的多个通孔232。在所示实施例中，多个通孔231将管芯连接焊盘242和基板210彼此电连接，并且多个通孔232将管芯220和260与基板210彼此电连接。如图所示，管芯连接焊盘242可位于未用于I/O连接的TSV的顶部以及通孔232的顶部两者之上。
多芯片封装环境中的管芯到管芯互连非常昂贵并且难以按比例缩小以跟上整体器件缩放。本发明的实施例减少或避免了这些困难和费用，这些实施例并非通过减少线和空间宽度而是通过在先前未使用的位置上放置一些互连来增大互连密度：所述位置即管芯的后侧。本发明实施例因而可用于粗略地使给定管芯尺寸可容纳的互连的数目加倍。
图3是根据本发明实施例的多芯片封装300的截面图，该多芯片封装300包括带有其管芯220和260的微电子封装200以及附加管芯310。管芯310通过互连311连接到管芯连接焊盘242，并且因而连接到通孔231和基板210。在未例示的实施例中，导线接合或其它连接机制可用于代替图3所示的焊接。这个以及其它封装上封装（POP）或封装中封装（PIP）配置是合乎需要的，因为它们具有由于BBUL架构而大大减小的高度和厚度。此外，本发明实施例使得I/O能够比现有POP架构中的更加密集，而在现有POP架构中，可能两排或三排凸块（其上放置附加封装）就是封装所能全部容纳的，并且整个封装的外部上的全部连接须在被布线到管芯之前穿过底部封装。本发明的实施例允许此类连接中的部分或全部在管芯后侧上形成，并且还允许它们更加密集。整个连接阵列是可能的，其中甚至管芯的后侧被至少部分地用连接覆盖。此外，导电结构自身可用作附加布线层。
图4是示出根据本发明实施例的制造微电子封装的方法400的流程图。作为示例，方法400可导致微电子封装的形成，该微电子封装类似于图1A和图1B所示的微电子封装100或者类似于图2A、图2B和图3所示的微电子封装200。
方法400的步骤410是提供导电载体。作为示例，导电载体可类似于首先在图5中示出的导电载体510。该导电载体可以是例如附连到可剥离芯或者其它临时或牺牲载体结构的铜箔等。箔的厚度可以是由微电子封装的功率输送要求所规定的。如果需要，可使用多层箔，其可能具有可（在后续步骤中）接收管芯的凹部。在例如管芯上方的箔厚度需要与其它位置的箔厚度不同的情况下，多层箔可提供所需的挠性。作为其它示例，多层箔还可提供多层无源器件产生方面的优点，并且它可帮助改善扭曲。
方法400的步骤420提供管芯，该管芯具有前侧、相对的后侧以及其中的至少一个穿过硅的通孔。作为示例，该管芯可类似于图1A、图1B、图2A、图2B和图3中所示的管芯120、管芯220以及管芯260中的一个或多个，并且还可类似于首先在图5中示出的管芯520。如所例示的，管芯520具有前侧521、后侧522以及TSV523。在某些实施例中，可提供多个管芯，如在图5中示出的第二个（未标记）管芯所例示的。（应当理解，管芯数量不限于仅仅一个或两个；相反，根据期望的微电子封装的需要或适于期望的微电子封装，可提供任何数量的管芯。）
方法400的步骤430将管芯的后侧附连到导电载体。例如，这可通过在TSV焊盘上（或者，如果TSV不具有焊盘，则在TSV自身的末端上）分配导电粘合剂或焊料等并且使用热压接合等将管芯（或多个管芯）粘附至箔上来实现。作为示例，这些连接可用于输送功率至管芯。图5示出已被附连到管芯520的后侧522之后的管芯520。
方法400的步骤440在管芯的前侧上形成多个构造层。该步骤的第一（或早期）部分可以是在整个面板上层叠或以其它方式形成介电膜，从而为构造工艺的平衡提供水准面。在层叠之前可执行铜膜的粗糙化，以便帮助粘附到介电膜。较小的通孔可形成于管芯区域中，该管芯区域落在管芯上的焊盘（例如，铜焊盘）上。较大的通孔可形成在管芯区域外，以将导电载体（在其被如下所述地功能化之后）连接到基板或连接到焊盘，其中该焊盘可用于将附加管芯或封装堆叠到微电子封装的顶部上。
附加层随后可被构造在介电膜上。例如，SAP技术可用于电镀落在封装的基板部分的第一金属层以及管芯焊盘上的通孔。也可使用LPP或其它技术。去往和来自管芯的I/O连接可在第一金属层或在后续层上制成，其可通过使用标准基板SAP（或其它）构造方法来形成以形成封装的其余部分。当构造完成时，封装连同铜箔一起可与临时芯/载体的其余部分分离开。
作为示例，构造层、较大的通孔、较小的通孔以及介电膜可分别类似于图6中所示出的构造层630、通孔631、通孔632以及介电膜639。构造层630也可类似于构造层130（图1B中示出）以及构造层230（首先在图2B中示出）。通孔631也可类似于通孔131（参见图1B）和通孔231（参见图2B和图3），而通孔632也可类似于通孔132（参见图1B）和通孔232（参见图2B和图3）。介电膜639也可类似于介电膜139（参见图1A和图1B）和介电膜239（参见图2A、图2B以及图3）。
方法400的步骤450用于图案化导电载体，以便形成微电子封装的导电组件。在一个实施例中，该导电组件是电源面。图1A和图1B示出由方法400的这一实施例的执行所产生的微电子封装的示例。
在特定实施例中，步骤450或另一步骤可包括将电源面和基板电连接到电源（例如，供电轨）。作为示例，步骤450可包括将干膜等层叠在铜箔的顶部上，并且随后执行减法式图案化以形成电源面。可在其上形成连接以通过TSV将来自于功率输送通孔的功率连接到管芯，其中功率输送通孔在管芯外部。
在另一实施例中（其中微电子封装包括多个管芯），导电组件是管芯中的两个（或更多个）之间的电连接。图2A、图2B和图3示出由方法400的这一实施例的执行所产生的微电子封装的示例。作为示例，步骤450可包括将干膜等层叠在铜箔的顶部上，并且随后执行减法式图案化以形成穿过TSV的附加I/O连接。可用于将管芯或封装堆叠在顶部上的焊盘也可被形成在管芯区域外的通孔的顶部以及未用于I/O连接的TSV的顶部两者之上。这些焊盘可类似于首先在图2A和图2B中示出的管芯连接焊盘242。
尽管已经参照特定实施例描述了本发明，但本领域的技术人员将理解可在不背离本发明的范围的情况下进行各种改变。因此，本发明实施例的公开旨在说明本发明的范围，而非旨在限制。本发明的范围旨在应仅由所附权利要求所主张的范围来限制。例如，对于本领域普通技术人员，显而易见的是可在各个实施例中实现本文讨论的微电子封装和相关联的结构和方法，且这些实施例中的某些实施例的前述某些讨论不一定表示所有可能实施例的全部描述。
另外，参考特定实施例描述了益处、其它优点和问题解决方案。但是，这些好处、优点、对问题的解决方案以及可使任何好处、优点或解决方案产生或变得更显著的任何要素不能被解释为任何或所有权利要求的关键的、必要的、或基本的特征或要素。
此外，如果实施例和/或限制有以下情况时，在专用原则下本文所公开的实施例和限制不专用于公众：（1）在权利要求中未明确要求的；且（2）其在等同原则下，权利要求中明确的元素和/或限制的可能等同方案。

Claims (13)

1.一种微电子封装，包括：
基板；
第一管芯和第二管芯，其中两个管芯均嵌入到所述基板中，两个管芯均具有前侧和相对的后侧，并且两个管芯均具有位于其中的至少一个穿过硅的通孔；
多个构造层，所述多个构造层邻近于所述第一和第二管芯的前侧并且构造在所述第一和第二管芯的前侧上；以及
导电结构，所述导电结构邻近于所述第一和第二管芯的后侧并且与所述第一和第二管芯的后侧物理接触。
2.如权利要求1所述的微电子封装，其特征在于：
所述导电结构包括：
互连，所述互连将所述第一和第二管芯的后侧彼此电连接；以及
管芯连接焊盘。
3.如权利要求2所述的微电子封装，其特征在于：
所述第一管芯具有第一管芯周界且所述第二管芯具有第二管芯周界；
所述第一管芯周界和所述第二管芯周界穿过所述构造层的延伸限定了管芯区域；以及
所述构造层包含所述管芯区域外的多个第一通孔以及所述管芯区域内的多个第二通孔。
4.如权利要求3所述的微电子封装，其特征在于：
所述多个第一通孔将所述管芯连接焊盘和所述基板彼此电连接；以及
所述多个第二通孔将所述第一和第二管芯与所述基板彼此电连接。
5.如权利要求1所述的微电子封装，其特征在于：
所述导电结构包括铜。
6.如权利要求1所述的微电子封装，其特征在于，还包括：
在所述导电结构上的保护层。
7.如权利要求1所述的微电子封装，其特征在于：
所述导电结构具有位于其中的凹部；以及
所述第一管芯和所述第二管芯至少部分位于所述凹部内。
8.一种制造微电子封装的方法，所述方法包括：
提供导电载体；
提供第一管芯和第二管芯，所述第一管芯和第二管芯均具有前侧、相对的后侧以及位于其中的至少一个穿过硅的通孔；
将所述第一管芯和第二管芯的所述后侧附连到所述导电载体；
在所述第一管芯和第二管芯的所述前侧上形成多个构造层，所述构造层和所述导电载体形成所述微电子封装的基板的一部分；以及
图案化所述导电载体，以便形成所述微电子封装的导电组件，所述导电组件是所述第一管芯与所述第二管芯之间的电连接。
9.如权利要求8所述的方法，其特征在于：
所述导电组件是电源面。
10.如权利要求9所述的方法，其特征在于，还包括：
将所述电源面电连接到电源；以及
将所述基板电连接到所述电源。
11.如权利要求8所述的方法，其特征在于：
所述导电载体包括铜。
12.如权利要求8所述的方法，其特征在于，还包括：
形成邻近于所述导电组件的多个连接焊盘。
13.如权利要求8所述的方法，其特征在于：
提供所述导电载体包括提供附连到牺牲芯的铜箔；
所述方法还包括在所述构造层完成后将所述铜箔与所述牺牲芯分离；以及
图案化所述导电载体以便形成所述微电子封装的所述导电组件包括图案化所述铜箔。
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