TW202145465A - 模組化之堆疊式矽封裝組件 - Google Patents

模組化之堆疊式矽封裝組件 Download PDF

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TW202145465A
TW202145465A TW110117126A TW110117126A TW202145465A TW 202145465 A TW202145465 A TW 202145465A TW 110117126 A TW110117126 A TW 110117126A TW 110117126 A TW110117126 A TW 110117126A TW 202145465 A TW202145465 A TW 202145465A
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Taiwan
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die
circuitry
rdl
chiplet
chip package
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TW110117126A
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賈斯匹利特 辛格 甘地
蘇芮戌 瑞瑪林嘉
威廉 Ｅ 阿萊爾
宏 史
凱瑞 Ｍ 皮爾斯
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美商吉林克斯公司
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Publication of TW202145465A publication Critical patent/TW202145465A/zh

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Abstract

本發明提供一種晶片封裝組件及其製造方法，該晶片封裝組件提供可與一或多個小晶片匹配之一模組化晶片堆疊。小晶片之使用使得能夠在大量的不同晶片封裝組件設計中利用相同模組化堆疊，從而在總體解決方案成本之一小部分下產生顯著更快的研發時間。

Description

模組化之堆疊式矽封裝組件
本發明之具體實例大體上係關於一種晶片封裝組件，且特定言之，係關於一種包含小晶片（chiplet）的晶片封裝組件，該小晶片經由重佈線層與一或多個積體電路晶粒介接。
電子裝置（諸如平板電腦、電腦、影印機、數位攝影機、智慧型電話、控制系統、自動化櫃員機、資料中心、人工智慧系統及機器學習系統以及其他電子裝置）通常採用充分利用晶片封裝組件以用於增加的功能性及較高部件密度之電子部件。習知晶片封裝方案通常利用封裝基板，通常與矽穿孔（through-silicon-via；TSV）內插基板結合，以使得複數個積體電路（integrated circuit；IC）晶粒能夠安裝至單個封裝基板。IC晶粒可包括記憶體、邏輯或其他IC裝置。
歸因於晶片封裝設計之複雜度，欲以及時方式滿足市場需求尤其具有挑戰性。採用較大單片IC晶粒之封裝通常需要較長設計及建置時間，此從而導致較高成本。此等屬性在需要較短設計交貨時間及較低成本之市場中（諸如在資料中心、人工智慧及機器學習應用中）並不為特別需要的。此外，歸因於愈來愈快速地改變之應用要求，迅速且成本有效地滿足演進的市場需求之能力已變得極具挑戰性。
因此，需要具有經改善模組性之晶片封裝組件，與習知單片解決方案相比，該模組性以適當成本實現較短設計及建置交貨時間。
提供一種晶片封裝組件及其製造方法，該晶片封裝組件提供可與多種個別小晶片匹配之模組化晶片堆疊。使用具有簡單I/O界面之模組化堆疊允許堆疊之組成易於改變，同時仍易於與廣泛多種小晶片選擇方案整合，因此使得能夠自先前或更有效研發之部件裝配大量不同晶片封裝組件設計，從而在成本之一小部分下產生顯著更快的研發時間。
在一個實例中，一種晶片封裝組件包括輸入/輸出積體電路（input/output integrated circuit；I/O IC）晶粒、功能IC晶粒、第一小晶片及基板。I/O IC晶粒具有第一表面及第二表面。功能IC晶粒堆疊於I/O IC晶粒之第一表面上。基板具有第一表面及第二表面。第一小晶片安置於基板與I/O IC晶粒之間。基板具有基板電路系統，該基板電路系統在晶片封裝組件內經由第一小晶片及I/O IC晶粒通信以耦接至功能IC晶粒之功能電路系統。
在另一實例中，提供一種晶片封裝組件，其包括輸入/輸出積體電路（I/O IC）晶粒、第一重佈線層（redistribution layer；RDL）、第一功能IC晶粒、第一小晶片及基板。IC I/O晶粒具有第一表面及第二表面。功能IC晶粒堆疊於I/O IC晶粒之第一表面上。第一RDL將I/O IC晶粒之第二表面耦接至第一小晶片。基板具有第一表面及第二表面。第一小晶片安置於基板與I/O IC晶粒之間。基板具有基板電路系統，該基板電路系統在晶片封裝組件內經由第一RDL、第一小晶片及I/O IC晶粒以通信耦接至功能IC晶粒之功能電路系統。第一RDL具有將I/O IC晶粒之I/O電路系統直接連接至基板電路系統，同時繞過第一小晶片的電路系統。介電填充層側向安置於I/O IC晶粒及功能IC晶粒周圍。
在又另一具體實例中，提供一種用於製造晶片封裝組件的方法，其包括(a)形成包括複數個積體電路（IC）晶粒及I/O IC晶粒的晶粒堆疊，I/O IC晶粒具有暴露觸點；(b)在I/O IC晶粒之暴露觸點上形成第一重佈線層（RDL）；(c)將小晶片耦接至第一RDL；及(d)將小晶片耦接至基板。
提供一種晶片封裝組件及其製造方法，該晶片封裝組件包括可與一或多個小晶片（chiplet）匹配之模組化晶片堆疊。使用具有可調式模組化晶片堆疊之一或多個小晶片使得能夠將大量的不同晶片封裝組件設計有效引入市場，從而在成本之一小部分下產生顯著更快的研發時間。藉由在晶片堆疊之底部處利用簡單輸入/輸出積體電路系統（I/O IC）晶粒來實現晶片封裝組件之模組性。重佈線層（RDL）用以將晶片堆疊之I/O IC晶粒耦接至一或多個小晶片。因此，I/O IC晶粒使得能夠在晶片堆疊內使用功能（亦即記憶體或邏輯）I/C晶粒之近乎任何組合，此保持與RDL的相同連接覆蓋區。RDL製造之靈活性使得各種小晶片能夠與單個I/O IC晶粒設計一起使用。因此，I/O IC晶粒/RDL界面允許功能IC晶粒之許多不同組合與許多不同小晶片匹配，而不必設計及下線整個晶片封裝組件以用於每一新的應用。
在下文所描述之實例中，晶片封裝組件包括利用重佈線層（RDL）與小晶片互連的晶片堆疊。晶片堆疊可提供作為可有益地用於其他晶片封裝組件中之晶片封裝組件的單式子部件。此外，組合為晶片堆疊/RDL組件之晶片堆疊及RDL亦可提供作為可有益地用於使用多種小晶片的其他晶片封裝組件之晶片封裝組件的單式子部件中。在一些實例中，至少一個小晶片嵌入小晶片層中，該小晶片層具有用於有效接地及功率路由之導電信號饋入通孔。小晶片層經組態以直接連接至晶片堆疊/RDL組件以提供模組化組件技術，同時使得能夠在組態之間無顯著研發及設計成本的情況下使用不同晶片堆疊及/或小晶片。
有益地，上文所描述及下文進一步詳述之組態及技術提供模組化及可調式晶片封裝組件。因此，與習知較大單片晶粒解決方案相比，顯著改善用於形成晶片封裝組件之成本及研發時間。
現轉至圖1，說明晶片封裝組件100之示意性截面視圖。晶片封裝組件100包括藉由重佈線層（RDL）116以耦接至小晶片112之晶片堆疊102。晶片封裝組件100亦包括封裝基板134。小晶片112安置於小晶片層110中，該小晶片層110亦包括複數個導電信號饋入通孔114。RDL 116之電路系統120經組態以在晶片封裝組件100之區域內將封裝基板134之封裝基板電路系統142及小晶片112之電路系統與晶片堆疊102之電路系統連接。
晶片堆疊102嵌入模製化合物144中。晶片堆疊102及模製化合物144與RDL 116一起形成晶片堆疊/RDL組件146。晶片堆疊/RDL組件146直接與小晶片層110機械及電性地連接，且經由小晶片層110以連接至封裝基板134。
晶片堆疊102包括至少一個輸入/輸出積體電路（I/O IC）晶粒104及至少一個功能IC晶粒106。儘管圖1中將三個功能IC晶粒106展示為豎直堆疊於I/O IC晶粒104之頂部上，但功能IC晶粒106之總數目可介於一個至多達可適配於晶片封裝組件100內之範圍內。另外，儘管圖1中說明單個IC晶片堆疊102，但額外IC晶片堆疊可側向安置於共同的封裝基板134上，藉由一或多個小晶片層110經由共同或個別RDL 116以連接至共同的封裝基板134。
I/O IC晶粒104通常包括用於將RDL 116之電路系統120耦接至IC晶片堆疊102內的功能IC晶粒106之電路系統的路由電路系統。I/O IC晶粒104為使得資料能夠在多個複雜矽裝置（亦即功能IC晶粒106）之間移動的簡單矽裝置。I/O IC晶粒104包括控制輸入，該等控制輸入選擇資料/使得資料能夠自一或多個複雜矽裝置（例如功能IC晶粒106）輸入，且隨後以靈活方式分配至一或多個複雜矽裝置。I/O IC晶粒104不同於與I/O IC晶粒104之電路系統所連接的功能IC晶粒106，此係因為I/O IC晶粒電路系統不對或幾乎不對在功能IC晶粒106之間或在功能IC晶粒106與RDL 116之電路系統120之間傳送的資料執行處理。如此，I/O IC晶粒104之電路系統比功能IC晶粒106之複雜度小許多個數量級。
在一個實例中，I/O IC晶粒104之電路系統僅包括路由電路系統。在另一實例中，I/O IC晶粒104之電路系統包括多工及解多工電路系統。I/O IC晶粒104之電路系統可另外包括計時電路系統。在需要經由I/O IC晶粒104以在功能IC晶粒106之間及在功能IC晶粒106之電路系統與RDL 116之電路系統120之間對信號進行路由的情況下，簡單路由處理電路系統可存在於I/O IC晶粒104之電路系統中。
如上文所陳述，一或多個功能IC晶粒106堆疊於I/O IC晶粒104上。用於晶片堆疊102中之功能IC晶粒106中的一或多者包括但不限於：可程式化邏輯裝置，諸如場可程式化閘陣列（field programmable gate array；FPGA）；記憶體裝置，諸如高頻寬記憶體（high band-width memory；HBM）；光學裝置；處理器或其他IC邏輯結構。功能IC晶粒106中之一或多者可視情況包括光學裝置，諸如光偵測器、雷射、光學源及其類似者。在圖1之實例中，最遠離I/O IC晶粒104之功能IC晶粒106為邏輯晶粒，其具有用於加快硬體中之機器學習數學運算（諸如自動駕駛汽車、人工智慧及資料中心神經網路應用）的數學處理器（亦已知為數學引擎）電路系統。在一個實例中，晶片堆疊102中之功能IC晶粒106包括區塊隨機存取記憶體（block random access memory；BRAM）、UltraRAM（URAM）、數位信號處理（digital signal processing；DSP）區塊、可組態邏輯元件（configurable logic elements；CLE）及其類似者。經審慎考慮，包含晶片堆疊102之功能IC晶粒106可為相同或不同類型，包括FPGA晶粒以外的類型。
模製化合物144安置於晶粒104、106外部上，且對封裝組件100提供額外剛性，同時亦保在護功能IC晶粒104、106之間的互連件108。模製化合物144可為聚合材料，諸如環氧類材料或其他合適的材料。
每一功能IC晶粒106包括底部表面及頂部表面。功能IC晶粒106之底部表面耦接至IC晶片堆疊102內之下一下部的功能IC晶粒106的頂部表面。IC晶片堆疊102內之最底部的功能IC晶粒106的底部表面耦接至I/O IC晶粒104之頂部表面。功能IC晶粒106與I/O IC晶粒104經由互連件108彼此機械及電性地耦接，該等互連件108可為無焊料混合接合及/或焊料連接。
I/O IC晶粒104之底部表面耦接至RDL 116之頂部表面。I/O IC晶粒104之電路系統經由互連件108（諸如無焊料混合接合或經由焊料連接）機械及電性地耦接至RDL 116之電路系統120。RDL 116之底部表面經由互連件130耦接至小晶片層110之頂部表面，該等互連件130可為無焊料混合接合及/或焊料連接。
如上文所論述，小晶片層110包括導電信號饋入通孔114及小晶片112。導電信號饋入通孔114及小晶片112嵌入模製化合物132中。導電信號饋入通孔114通常作為在小晶片層110之頂部表面與底部表面之間通過的導電路由。模製化合物132為介電填充層，其在導電信號饋入通孔114之間提供電絕緣，且對小晶片層110提供剛性。
小晶片112為經組態以使晶片堆疊102或安置於晶片封裝組件100內之其他小晶片工作的積體電路區塊。小晶片112含有包含以下各者中之一或多者的電路系統：實體層（physical layer；PHY）電路系統、高頻寬記憶體電路系統、處理器、串列解串器（serial deserializer；SerDes）、高速串列匯流排、類比至數位轉換器、數位至類比轉換器、視訊編碼解碼器電路系統、電至光轉換器、記憶體子系統、處理器子系統、快閃記憶體及功率調節/分配系統或光至電轉換器以及其他者。小晶片112亦可組態為或可為高頻寬記憶體（HBM）裝置之部分。小晶片112之頂部表面經由互連件130以耦接至RDL 116之底部表面，而小晶片112之底部表面經由虛設球124以耦接至封裝基板134之頂部表面136。可替代地，在其中小晶片112包括TSV之具體實例中，虛設球124可主動將小晶片112及/或RDL 116之電路系統連接至封裝基板134之封裝基板電路系統142。虛設球124為小晶片112提供與封裝基板134之頂部表面136的良好均一間隔表面，以使得將導電信號饋入通孔114耦接至封裝基板134之封裝基板電路系統142的焊料互連件148在暴露於較寬溫度範圍時具有減小的應力。藉由虛設球124提供之間隔亦允許將底部填充物150安置於封裝基板134與小晶片層110之間，以保護焊料互連件148及虛設球124，同時增加晶片封裝組件100之剛性。
小晶片112可視情況包括矽穿孔以允許功率、接地及/或資料信號直接通過小晶片112。在圖1中所描繪之實例中，因為小晶片112之所有輸入及輸出均經由互連件130以路由穿過作用表面126，故小晶片112不具有矽穿孔，而所有功率、接地及/或資料信號均經由導電信號饋入通孔114而直接在RDL 116之電路系統120與封裝基板134之封裝基板電路系統142之間路由。
封裝基板134之底部表面138藉由焊球140或其他合適的電性連接以耦接至印刷電路板（printed circuit board；PCB，圖中未示）。焊球140經由封裝基板134之封裝基板電路系統142將電信號（諸如資料、接地及功率）提供至小晶片層110，且最終經由RDL 116之電路系統120及I/O IC晶粒104之電路系統將該等電信號提供至功能IC晶粒106之電路系統。
如上文所論述，I/O IC晶粒104之電路系統連接至RDL 116之電路系統120。在I/O IC晶粒104與RDL 116之間的連接之細節進一步提供於圖2中。RDL 116亦與模製化合物144之底部表面152接觸。
參考圖2之部分截面視圖，I/O IC晶粒104包括接觸墊202，I/O IC晶粒104之電路系統204終止於該等接觸墊202處。接觸墊202暴露於I/O IC晶粒104之底部表面。互連件154形成於接觸墊202上。互連件154亦電性及機械地連接至RDL 116之電路系統120。RDL 116之頂部表面製造於I/O IC晶粒104之底部表面及模製化合物144之底部表面152正上方。可替代地，RDL 116可形成於小晶片112之表面上。RDL 116包括經圖案化以產生RDL 116之電路系統120的至少3層金屬及介電質。在一個實例中，包含藉由圖案化之金屬線210及穿孔212形成於介電層214內之電路系統120的路由在無焊料連接的情況下直接連接至暴露於I/O IC晶粒104之底部下方的互連件154。以此方式，在接觸墊202之間的間隔可具有比利用焊料互連件之連接顯著更精細的間距。包含電路系統120之路由終止且暴露於RDL 116之底部表面，以有助於與下方小晶片112及導電信號饋入通孔114之電路系統的電性及機械連接。舉例而言，RDL 116之電路系統120經由互連件130以連接至暴露於小晶片112之作用表面126上的接觸墊206。RDL 116之電路系統120亦經由互連件118以連接至導電信號饋入通孔114。
圖3為用於製造具有經由RDL以耦接至小晶片之晶片堆疊的晶片封裝組件（尤其諸如上文參考圖1至圖2所描述之晶片封裝組件100）之方法300的流程圖。圖4A至圖4F為圖3之方法300的不同階段處之晶片封裝組件100的示意性截面視圖。應注意，晶粒104、106及圖4A至圖4E中所說明之其他部件的定向與如圖1中所展示之定向相比相差180度。換言之，與如圖1中所展示相比，晶粒104、106及圖4A至圖4E所說明之其他部件倒置。
如圖4A中所說明，藉由將包括至少一個I/O IC晶粒104及至少一個功能晶粒106之晶片堆疊102附接至載板400，方法300始於操作302處。載板400僅在初始製造操作期間予以使用，且如此在將晶片堆疊102及稍後製造的RDL 116安裝至基板（諸如封裝基板134）及完成晶片封裝組件100之製造之前以可拆卸方式與晶片堆疊102附接。在一個實例中，使用可釋放壓敏黏著劑將晶片堆疊102之頂部表面402附接至載板400。
說明自I/O IC晶粒104之表面（亦即最上部的功能IC晶粒106背對相鄰的功能IC晶粒106之表面）延伸的互連件154。互連件154可藉由圖案化及鍍覆或經由另一技術進行製造。可替代地在方法300之後期階段形成互連件154。
在操作304處，模製化合物144安置於晶粒104、106周圍且與載板400接觸，如圖4B中所說明。模製化合物144延伸超出I/O IC晶粒104之底部表面達至初始表面440。互連件154通常在初始表面440下方，且藉由模製化合物144來包封。可藉由另一合適方法來旋塗、分配、超模製或沈積模製化合物144。在操作304處，模製化合物144填充限定於相鄰晶粒104、106之間的隙間空間。
視情況在操作304處，至少一或多個輔助元件可鄰近於晶片堆疊102而嵌入模製化合物144中。嵌入模製化合物中之輔助元件可為虛設晶粒、電容器、電感器或小晶片。在一些實例中，多個輔助元件鄰近於晶片堆疊102而嵌入模製化合物144中。當多個輔助元件嵌入模製化合物144中時，每一輔助元件可為相同類型之輔助元件，或可替代地，輔助元件中之一或多者可為不同類型的輔助元件。
可替代地，當使用時，輔助元件稍後可在已沈積模製化合物144之後耦接至RDL 116。亦即，輔助元件可不嵌入模製化合物144內，且稍後耦接至RDL 116。
在操作306處，將模製化合物144之初始表面440及互連件154之遠端接地，以機械或其他方式移除以形成模製化合物144之底部表面152，如圖4C中所說明。操作306使互連件154之遠端與模製化合物144之底部表面152共平面。
在操作308處，在不使用焊料連接之情況下，將RDL 116製造於模製化合物144之底部表面152正上方，如圖4D中所展示。藉由沈積其中形成有由金屬線210及穿孔214所形成之金屬路由的至少3個或更多個介電層214來製造RDL 116。金屬路由之金屬線210及穿孔212形成重佈線層116之電路系統120。
在操作310處，移除載板400，且利用互連件118、130將RDL 116電性及機械地連接至小晶片層110，如圖4E中所展示。小晶片層110可定向為使得小晶片112之作用表面126安置為抵靠RDL 116且電性連接至RDL 116。可替代地，小晶片層110可定向為使得小晶片112之矽表面128安置為抵靠RDL 116，以使得RDL 116之電路系統120耦接至暴露於小晶片112之表面上的矽穿孔。
在操作312處，封裝基板134利用互連件（焊料互連件148）電性及機械地連接至小晶片層110，如圖4E中所說明。在圖4E中之實例中，小晶片112之作用表面126面向RDL 116，以使得藉由焊料互連件148或其他合適連接來提供在小晶片層110之導電信號饋入通孔114與封裝基板134之封裝基板電路系統142之間的電性連接，而小晶片112之電路系統藉由互連件130或其他合適連接而機械及電性地耦接至RDL 116之電路系統120。可替代地且如圖4F中所展示，小晶片112之作用表面126背對RDL 116，以使得互連件130用以將RDL 116之電路系統120耦接至經由小晶片112所形成的矽穿孔450，而焊料互連件148用以將小晶片層110之導電信號饋入通孔114連接至RDL 116之電路系統120。
在操作312處，封裝基板134藉由焊料互連件148以耦接至小晶片層110，如圖1中所展示，使小晶片112之作用表面126面向RDL 116。操作312亦可包括藉由虛設（或功能）球124將封裝基板134耦接至小晶片層110。在其中小晶片112包括矽穿孔之實例中，穿孔可藉由焊料互連件148或其他合適連接而電性及機械地耦接至封裝基板134之封裝基板電路系統142。
可替代地，RDL 116可製造於小晶片層110上，隨後利用焊料或其他連接而附接至晶片堆疊102。
圖5描繪具有藉由重佈線層（RDL）116以耦接至小晶片460之晶片堆疊102之晶片封裝組件500的示意性截面視圖。如上文所描述來組態晶片堆疊102及重佈線層RDL 116，從而形成晶片堆疊/RDL組件146。晶片堆疊/RDL組件146安裝至包括小晶片460之小晶片層510。
除了其中安置於小晶片層510中之小晶片460具有面向安裝有小晶片層510之封裝基板134的作用表面126，小晶片層510基本上組態為與小晶片層110相同。小晶片460之矽表面128面向且耦接至RDL 116。
更具體言之，除了其中小晶片460包括複數個矽穿孔450，小晶片460基本上組態為與小晶片112相同。矽穿孔450在小晶片460之矽表面128上藉由互連件502以耦接至封裝基板134之封裝基板電路系統（142，圖5中未示），該等互連件502可為無焊料混合接合及/或焊料連接。矽穿孔450在小晶片460之作用表面126上藉由互連件130以耦接至RDL 116之電路系統120，該等互連件130可為無焊料混合接合及/或焊料連接。在圖5中所描繪之實例中，複數個矽穿孔450中之至少一些經組態以在RDL 116與封裝基板134之間傳輸功率及/或接地信號。
由於互連件502可相較於焊料互連件148更緊密間隔，因而在與封裝基板134的焊料互連件148藉以連接至導電信號饋入通孔114之部分552中的電路系統相比，在封裝基板134的互連件502藉以連接至小晶片460之一部分550中的封裝基板電路系統142具有顯著更精細的間距。
舉例而言，當小晶片460之作用表面126安裝至封裝基板134時，部分550中之封裝基板134的接觸墊之間距及小晶片460之接觸墊206的間距可為130 µm或更小，諸如54 µm或更小，因而有助於高密度信號傳輸。在封裝基板134之部分552中的接觸墊之間距及小晶片層510之導電信號饋入通孔114之間距大於200 µm，因而允許在小晶片層510的環繞小晶片460（亦即在小晶片460外部）之區中更具成本效益地製造。
圖6描繪具有藉由重佈線層（RDL）116以耦接至小晶片460之晶片堆疊102之晶片封裝組件600的示意性截面視圖。如上文所描述來組態晶片堆疊102及重佈線層RDL 116，從而形成晶片堆疊/RDL組件646。晶片堆疊/RDL組件646安裝至包括小晶片460之小晶片層510。如上文參考圖5所描述來製造小晶片層510。
除了其中晶片堆疊/RDL組件646包括安置於晶片堆疊/RDL組件646之模製化合物144中的至少一個輔助元件602，晶片堆疊/RDL組件646基本上與上文參考圖1所描述之晶片堆疊/RDL組件146相同。輔助元件602可提供額外功能性，增強效能，或抑制晶片封裝組件600之翹曲。
可替代地，輔助元件602中之一或多者或全部可在不嵌入模製化合物144中的情況下耦接至RDL 116。亦即，輔助元件602在模製化合物144外部，此允許輔助元件602視需要在組件方法之不同階段處耦接至RDL 116。
圖6中所描繪之實例，說明包封於模製化合物144中之兩個輔助元件602。經審慎考慮，可在晶片封裝組件600中使用一個至許多可適配於模製化合物144內之輔助元件602。輔助元件602之頂部可接地或另外與模製化合物144之頂部表面及最上部的功能IC晶粒106之所暴露頂部表面共面。可替代地，輔助元件602中之一或多者的頂部可不與晶片堆疊102之頂部及/或與其他輔助元件602中之一或多者共面。輔助元件602經由互連件604以耦接至RDL 116。互連件604可為無焊料混合接合及/或焊料連接焊料及/或其他類型之接合材料，諸如環氧樹脂。在一些實例中，互連件604僅將輔助元件602機械緊固至RDL 116。在其他實例中，互連件604向RDL 116之電路系統120提供在輔助元件602內之電路系統的電性連接及機械連接兩者。
在一個實例中，輔助元件602中之至少一或多者為虛設晶粒。歸因於溫度變化及在堆疊於晶片封裝組件600內之部件之間的熱膨脹係數之間的失配，以減小應力之配置將虛設晶粒分佈於模製化合物144內。
在另一實例中，輔助元件602中之至少一或多者為電容器。組態為電容器（諸如深溝槽電容器）之輔助元件602可與具有其他類型之組態的輔助元件602一起使用。形成於輔助元件602中之電容器的電路系統藉由互連件604以電性及機械地耦接至RDL 116之電路系統120。在一個實例中，輔助元件602之深溝槽電容器電路系統耦接至RDL 116之電路系統120的功率軌。
在另一實例中，輔助元件602中之至少一或多者為電感器。組態為電感器之輔助元件602可與具有其他類型之組態的輔助元件602一起使用。形成於輔助元件602中之電感器的電路系統藉由互連件604以電性及機械地耦接至RDL 116之電路系統120。
在另一實例中，輔助元件602中之至少一或多者為小晶片。組態為小晶片之輔助元件602可與具有其他類型之組態的輔助元件602一起使用。形成於輔助元件602中之小晶片的電路系統藉由互連件604以電性及機械地耦接至RDL 116之電路系統120。輔助元件602之小晶片電路系統可組態為以下各者中之一或多者：實體層（PHY）電路系統、高頻寬記憶體電路系統、處理器、串列解串器（SerDes）、高速串列匯流排、類比至數位轉換器、數位至類比轉換器、視訊編碼解碼器電路系統、電至光轉換器、記憶體子系統、處理器子系統、快閃記憶體、及功率調節/分配系統或光至電轉換器以及其他者。
圖7為揭露安置於晶片堆疊102周圍之輔助元件602之例示性幾何配置的圖6之晶片封裝組件600的示意性俯視圖。輔助元件602通常安置於模製化合物144之區706中，該區706限定於晶片堆疊102之最外邊緣702與模製化合物144之最外邊緣704之間。區706通常包圍晶片堆疊102。
在一個實例中，單個輔助元件602安置於兩個相鄰邊緣702、704之間的區706中。在其他實例中，複數個輔助元件602安置於兩個相鄰邊緣702、704之間的區706中。兩個或更多個輔助元件602可以至少兩個輔助元件602藉由晶片堆疊102所分離之配置而安置於區706中。在其他實例中，一或多個輔助元件602安置於每一對鄰近邊緣702、704之間包圍晶片堆疊102之區706中。在圖7中所描繪之實例中，四個輔助元件602交疊於晶片堆疊102之兩個相鄰邊緣702的相交點，此進一步增強晶片封裝組件600對翹曲之耐受性。輔助元件602亦可具有比晶片堆疊102之功能IC晶粒106之平面面積小得多的平面面積。輔助元件602亦可具有比晶片堆疊102之功能IC晶粒106之長度與寬度縱橫比顯著更大的長度與寬度縱橫比。輔助元件602之高縱橫比不僅更有效地適配於相鄰邊緣702、704之間，且亦促使加固晶片封裝組件600。
儘管將輔助元件602說明為併入具有與晶片封裝組件500類似的構造之晶片封裝組件600中，如上文所描述的一或多個輔助元件602亦可併入本文中所描述之晶片封裝組件中之任一者的模製化合物144中，其中包括利用包圍一或多個IC晶粒之模製化合物的晶片封裝組件。
圖8為具有藉由晶片封裝組件800之第一重佈線層（RDL）116以耦接至晶片堆疊102之小晶片460的又另一晶片封裝組件800之示意性截面視圖。102。如上文參考圖1、圖2及圖6所描述來組態晶片堆疊102及第一RDL 116，從而形成晶片堆疊/RDL組件646。晶片堆疊/RDL組件646安裝至小晶片層/RDL組件800。小晶片層/RDL組件800包括形成於小晶片層510正上方之第二RDL 820。當小晶片層510包含小晶片460時，第二RDL 820之一部分形成於小晶片460正上方。可如上文參考圖5所描述來製造小晶片層510。
晶片堆疊/RDL組件646基本上與上文參考圖6所描述之晶片堆疊/RDL組件相同。輔助元件602可提供額外功能性，增強效能，或抑制晶片封裝組件600之翹曲。
除了小晶片層510經由第二重佈線層（RDL）820以耦接至封裝基板134，可如圖6中參考晶片封裝組件600所描述來製造晶片封裝組件800。如圖2中參考RDL 116所描述來製造第二RDL 820，從而形成將小晶片層510之電路系統（亦即小晶片460之電路系統及導電信號饋入通孔114）電性耦接至封裝基板134之封裝基板電路系統142的電路系統802。
第二RDL 820之電路系統802可視情況包括線性延伸穿過第二RDL 820之導電穿孔804。此導電穿孔804可經組態以直接經由第二RDL 820來路由功率及/或接地。另外，導電穿孔804可與形成於小晶片460中之導電穿孔450豎直對準，以使得功率及/或接地可直接經由第二RDL 820及小晶片460來路由至第一RDL 116。
第二RDL 820之電路系統802的一部分直接耦接至小晶片層510之導電信號饋入通孔114。第二RDL 820之電路系統802的一部分藉由互連件502以直接耦接至小晶片460之電路系統，該等互連件502可為無焊料混合接合及/或焊料連接。第二RDL 820之電路系統802的一部分藉由互連件830以直接耦接至封裝基板之封裝基板電路系統142，該等互連件830亦可為無焊料混合接合及/或焊料連接。第二RDL 820之電路系統802的一部分藉由焊料互連件148（諸如焊料凸塊）以直接耦接至封裝基板134之封裝基板電路系統142。在封裝基板134與第二RDL 820的互連件830之間的隙間空間可經底部填充物806填充以保護焊料互連件148、互連件830且加固晶片封裝組件800。
因此，已描述一種晶片封裝組件及製造方法，該晶片封裝組件利用可與一或多個小晶片匹配之模組化晶片堆疊。有利地，由於晶片堆疊建置於簡單的I/O IC晶粒上，因而可使用各種功能晶粒，同時維持晶片堆疊經由I/O IC晶粒之相同輸出界面，此實現可以極少成本及時間來快速設計及研發的模組化及靈活設計。此外，使用小晶片使得能夠在各種不同小晶片中利用可調式及模組化晶片堆疊，從而進一步增強快速且在研發習知設計所需之成本及時間的一小部分下來設計及研發大量晶片封裝組件設計之靈活性。因此，模組化晶片封裝組件提供極佳可調性、低研發成本及極引人注目之研發時間。
除下述申請專利範圍以外，所揭示之技術亦可描述於以下非限制性實例中。 實施例1.一種晶片封裝組件，其包括：輸入/輸出積體電路（I/O IC）晶粒，其具有第一表面及第二表面；功能IC晶粒，其堆疊於I/O IC晶粒之第一表面上；第一小晶片，其具有耦接至I/O IC晶粒之電路系統的電路系統；及基板，其具有第一表面及第二表面，第一小晶片安置於基板與I/O IC晶粒之間，基板具有基板電路系統，該基板電路系統在晶片封裝組件內經由第一小晶片及I/O IC晶粒以通信耦接至功能IC晶粒之功能電路系統。 實施例2.    如實施例1之晶片封裝組件，其進一步包括第一重佈線層（RDL），該第一重佈線層將I/O IC晶粒之第二表面耦接至第一小晶片。 實施例3.    如實施例2之晶片封裝組件，其進一步包括電路系統，該電路系統將I/O IC晶粒之I/O電路系統直接連接至基板電路系統，同時繞過第一小晶片。 實施例4.    如實施例3之晶片封裝組件，其進一步包括：第一介電填充層，其側向安置於第一小晶片周圍；及導電穿孔，其安置於第一介電填充層中，從而在I/O電路系統與基板電路系統之間提供電性連接。 實施例5.    如實施例4之晶片封裝組件，其中第一小晶片進一步包括焊料連接，該等焊料連接將第一小晶片機械及電性地耦接至基板。 實施例6.    如實施例2之晶片封裝組件，其進一步包括第二RDL，該第二RDL將基板耦接至第一小晶片之作用側。 實施例7.    如實施例6之晶片封裝組件，其中第一小晶片進一步包括導電穿孔，該導電穿孔安置為穿過第一小晶片之第一小晶片基板，導電穿孔將第一小晶片之電路系統耦接至第一RDL。 實施例8.    如實施例2之晶片封裝組件，其中第一小晶片進一步包括導電穿孔，該導電穿孔安置為穿過第一小晶片之第一小晶片基板，導電穿孔將第一小晶片之電路系統耦接至第一RDL之第一RDL電路系統及基板之基板電路系統。 實施例9.    如實施例4之晶片封裝組件，其進一步包括：第二介電填充層，其側向安置於I/O IC晶粒及功能IC晶粒周圍；及電路元件，其安置於第二介電填充層中，電路元件耦接至第一RDL之第一RDL電路系統。 實施例10.  如實施例9之晶片封裝組件，其中電路元件為電容器。 實施例11.   如實施例10之晶片封裝組件，其中電容器為耦接至第一RDL之第一RDL電路系統內的功率軌之深溝槽電容器。 實施例12.  如實施例4之晶片封裝組件，其進一步包括：第二介電填充層，其側向安置於I/O IC晶粒及功能IC晶粒周圍；及第二小晶片，其安置於第二介電填充層中而與第一小晶片側向偏移，第二小晶片具有耦接至第一RDL之第一RDL電路系統的第二小晶片電路系統。 實施例13.  如實施例12之晶片封裝組件，其中第二小晶片為具有耦接至第一RDL之第一RDL電路系統的小晶片電路系統之複數個小晶片中的一者。 實施例14.  如實施例12之晶片封裝組件，其中第二小晶片電路系統包括以下各者中之一或多者：實體層（PHY）電路系統、高頻寬記憶體電路系統、處理器、串列解串器（SerDes）、高速串列匯流排、類比至數位轉換器、數位至類比轉換器、視訊編碼解碼器電路系統、電至光轉換器、記憶體子系統、處理器子系統、快閃記憶體及功率調節/分配系統或光至電轉換器。 實施例15.  如實施例1之晶片封裝組件，其中第一小晶片不具有矽穿孔。 實施例16.  如實施例1之晶片封裝組件，其中第一小晶片之第一小晶片電路系統進一步包括以下各者中之一或多者：實體層（PHY）電路系統、高頻寬記憶體電路系統、處理器、串列解串器（SerDes）、高速串列匯流排、類比至數位轉換器、數位至類比轉換器、視訊編碼解碼器電路系統、電至光轉換器、記憶體子系統、處理器子系統、快閃記憶體及功率調節/分配系統或光至電轉換器。 實施例17.  如實施例1之晶片封裝組件，其中I/O IC晶粒進一步包括多工及解多工電路系統。 實施例18.  如實施例1之晶片封裝組件，其進一步包括堆疊於第一IC晶粒上之複數個IC晶粒，其中複數個IC晶粒中安置為最遠離第一IC晶粒之第二IC晶粒為處理器。 實施例19.  一種晶片封裝組件，其包括：輸入/輸出積體電路（I/O IC）晶粒，其具有第一表面及第二表面；複數個功能積體電路（IC）晶粒，其堆疊於I/O IC晶粒之第一表面上；第一小晶片；第一重佈線層（RDL），其將I/O IC晶粒之第二表面耦接至第一小晶片；基板，其具有第一表面及第二表面，第一小晶片安置於基板與I/O IC晶粒之間，基板具有基板電路系統，該基板電路系統在晶片封裝組件內經由第一RDL、第一小晶片及I/O IC晶粒以通信耦接至功能IC晶粒之功能電路系統；電路系統，其將I/O IC晶粒之I/O電路系統直接連接至基板電路系統，同時繞過第一小晶片；及介電填充層，其側向安置於I/O IC晶粒及功能IC晶粒周圍。 實施例20.  如實施例19之晶片封裝組件，其進一步包括安置於介電填充層中而與第一小晶片側向偏移之電路元件或第二小晶片，電路元件耦接至第一RDL之第一RDL電路系統。 實施例21.  如實施例19之晶片封裝組件，其中第一小晶片之第一小晶片電路系統進一步包含以下各者中之一或多者：實體層（PHY）電路系統、高頻寬記憶體電路系統、處理器、串列解串器（SerDes）、高速串列匯流排、類比至數位轉換器、數位至類比轉換器、視訊編碼解碼器電路系統、電至光轉換器、記憶體子系統、處理器子系統、快閃記憶體及功率調節/分配系統或光至電轉換器。 實施例22.  如實施例19之晶片封裝組件，其中第一小晶片具有比I/O IC晶粒更小的平面面積。 實施例23.  如實施例19之晶片封裝組件，其中第一小晶片不具有矽穿孔。 實施例24.  如實施例19之晶片封裝組件，其中I/O IC晶粒進一步包括多工及解多工電路系統。 實施例25.  如實施例19之晶片封裝組件，其中複數個IC晶粒中安置為最遠離I/O IC晶粒之IC晶粒為處理器。 實施例26.  如實施例19之晶片封裝組件，其中第一小晶片進一步包括焊料連接，該等焊料連接將第一小晶片機械及電性地耦接至基板。 實施例27.  如實施例19之晶片封裝組件，其進一步包括第二RDL，該第二RDL將基板耦接至第一小晶片之作用側。 實施例28.  如實施例27之晶片封裝組件，其中第一小晶片進一步包括導電穿孔，該導電穿孔安置為穿過第一小晶片之第一小晶片基板，導電穿孔將第一小晶片之電路系統耦接至第一RDL。 實施例29.  如實施例19之晶片封裝組件，其中第一小晶片進一步包括導電穿孔，該導電穿孔安置為穿過第一小晶片之第一小晶片基板，導電穿孔將第一小晶片之電路系統耦接至第一RDL之第一RDL電路系統及基板之基板電路系統。 實施例30.  一種用於製造晶片封裝組件之方法，該方法包括：形成包括複數個積體電路（IC）晶粒及I/O IC晶粒之晶粒堆疊，I/O IC晶粒具有暴露觸點；在I/O IC晶粒之暴露觸點上形成第一重佈線層（RDL）；將小晶片耦接至第一RDL；及將小晶片耦接至基板。 實施例31.  如實施例30之方法，其進一步包括在小晶片的與第一RDL相對之側上形成第二RDL。 實施例32.  如實施例30之方法，其進一步包括將第一RDL電性連接至I/O IC晶粒，同時繞過小晶片之電路系統。 實施例33.  如實施例30之方法，其進一步包括在I/O IC晶粒周圍形成第一介電填充層。 實施例34.  如實施例33之方法，其進一步包括將安置於第一介電填充層中而側向地在I/O IC晶粒外部的電路元件電性地耦接至第一RDL。 實施例35.  如實施例33之方法，其進一步包括將安置於第一介電填充層中而側向地在I/O IC晶粒外部的第二小晶片電性地耦接至第一RDL。
雖然前述內容係針對本發明之具體實例，但在不脫離本發明之基本範圍的情況下，可設計出本發明之其他及另外的具體實例，且由以下申請專利範圍來判定本發明之範圍。
100:晶片封裝組件 102:晶片堆疊 104:輸入/輸出積體電路（I/O IC）晶粒 106:功能IC晶粒 108:互連件 110:小晶片層 112:小晶片 114:導電信號饋入通孔 116:重佈線層（RDL） 118:互連件 120:電路系統 124:虛設球 126:作用表面 128:矽表面 130:互連件 132:模製化合物 134:封裝基板 136:頂部表面 138:底部表面 140:焊球 142:封裝基板電路系統 144:模製化合物 146:晶片堆疊/RDL組件 148:焊料互連件 150:底部填充物 152:底部表面 154:互連件 202:接觸墊 204:電路系統 206:接觸墊 210:圖案化金屬線 212:穿孔 214:介電層 300:方法 302:操作 304:操作 306:操作 308:操作 310:操作 312:操作 400:載板 402:頂部表面 440:初始表面 450:矽穿孔 460:小晶片 500:晶片封裝組件 502:互連件 510:小晶片層 550:部分 552:部分 600:晶片封裝組件 602:輔助元件 604:互連件 646:晶片堆疊/RDL組件 702:最外邊緣 704:最外邊緣 706:區 800:晶片封裝組件 802:電路系統 804:導電穿孔 806:底部填充物 820:第二重佈線層（RDL） 830:互連件
因此，可參考具體實例獲得可詳細地理解本發明之上述特徵的方式、上文簡要概述之本發明的更特定描述，其中一些說明於隨附圖式中。然而，應注意，隨附圖式僅說明本發明之典型具體實例，且因此不應被視為限制本發明之範圍，因為本發明可准許其他同等有效的具體實例。 [圖1]為具有藉由晶片封裝組件之重佈線層以耦接至晶片堆疊的小晶片之晶片封裝組件的示意性截面視圖。 [圖2]為說明晶片封裝組件之重佈線層之一部分的圖1之晶片封裝組件的部分截面視圖。 [圖3]為用於製造具有藉由晶片封裝組件之重佈線層以耦接至晶片堆疊的小晶片之晶片封裝組件之方法的流程圖。 [圖4A至圖4F]為圖3之方法的不同階段處之晶片封裝組件的示意性截面視圖。 [圖5]為具有藉由晶片封裝組件之重佈線層以耦接至晶片堆疊的小晶片之另一晶片封裝組件的示意性截面視圖。 [圖6]為具有藉由晶片封裝組件之重佈線層以耦接至晶片堆疊的小晶片之另一晶片封裝組件的示意性截面視圖。 [圖7]為揭露安置於晶片堆疊周圍之輔助元件之例示性幾何配置的圖6之晶片封裝組件的示意性俯視圖。 [圖8]為具有藉由晶片封裝組件之重佈線層以耦接至晶片堆疊的小晶片之又另一晶片封裝組件的示意性截面視圖。 為有助於理解，在可能之情況下，已使用相同元件符號來表示圖式中所共有的相同元件。經審慎考慮，一個具體實例之元件可有益地併入其他具體實例中。
100:晶片封裝組件
102:晶片堆疊
104:輸入/輸出積體電路(I/O IC)晶粒
106:功能IC晶粒
108:互連件
110:小晶片層
112:小晶片
114:導電信號饋入通孔
116:重佈線層(RDL)
118:互連件
120:電路系統
124:虛設球
126:作用表面
128:矽表面
130:互連件
132:模製化合物
134:封裝基板
136:頂部表面
138:底部表面
140:焊球
142:封裝基板電路系統
144:模製化合物
146:晶片堆疊/RDL組件
148:焊料互連件
150:底部填充物
152:底部表面
154:互連件

Claims (15)

  1. 一種晶片封裝組件，其包含： 輸入/輸出積體電路（I/O IC）晶粒，其具有第一表面及第二表面； 功能IC晶粒，其堆疊於該I/O IC晶粒之該第一表面上； 第一小晶片（chiplet），其具有耦接至該I/O IC晶粒之電路系統的電路系統；及 基板，其具有第一表面及第二表面，該第一小晶片安置於該基板與該I/O IC晶粒之間，該基板具有基板電路系統，該基板電路系統在該晶片封裝組件內經由該第一小晶片及該I/O IC晶粒以通信耦接至該功能IC晶粒之功能電路系統。
  2. 如請求項1之晶片封裝組件，其進一步包含： 第一重佈線層（RDL），其將該I/O IC晶粒之該第二表面耦接至該第一小晶片。
  3. 如請求項2之晶片封裝組件，其進一步包含： 電路系統，其將該I/O IC晶粒之I/O電路系統直接連接至該基板電路系統，同時繞過該第一小晶片。
  4. 如請求項3之晶片封裝組件，其進一步包含： 第一介電填充層，其側向安置於該第一小晶片周圍；及 導電穿孔，其安置於該第一介電填充層中，從而在該I/O電路系統與該基板電路系統之間提供電性連接。
  5. 如請求項4之晶片封裝組件，其中該第一小晶片進一步包含： 焊料連接，其將該第一小晶片機械及電性地耦接至該基板。
  6. 如請求項4之晶片封裝組件，其進一步包含： 第二介電填充層，其側向安置於該I/O IC晶粒及該功能IC晶粒周圍；及 輔助元件，其安置於該第二介電填充層中，該輔助元件耦接至該第一RDL之第一RDL電路系統，其中該輔助元件為電容器、虛設結構或小晶片。
  7. 如請求項4之晶片封裝組件，其進一步包含： 第二介電填充層，其側向安置於該I/O IC晶粒及該功能IC晶粒周圍；及 第二小晶片，其安置於該第二介電填充層中而與該第一小晶片側向偏移，該第二小晶片具有耦接至該第一RDL之第一RDL電路系統的第二小晶片電路系統。
  8. 如請求項7之晶片封裝組件，其中該第二小晶片為具有耦接至該第一RDL之該第一RDL電路系統的小晶片電路系統之複數個小晶片中的一者。
  9. 如請求項1之晶片封裝組件，其中該第一小晶片不具有矽穿孔。
  10. 如請求項1之晶片封裝組件，其中該I/O IC晶粒進一步包含： 多工及解多工電路系統。
  11. 如請求項1之晶片封裝組件，其進一步包含： 複數個IC晶粒，其堆疊於該第一IC晶粒上，其中該複數個IC晶粒中安置為最遠離該第一IC晶粒之第二IC晶粒為處理器。
  12. 一種晶片封裝組件，其包含： 輸入/輸出積體電路（I/O IC）晶粒，其具有第一表面及第二表面； 複數個功能積體電路（IC）晶粒，其堆疊於該I/O IC晶粒之該第一表面上； 第一小晶片； 第一重佈線層（RDL），其將該I/O IC晶粒之該第二表面耦接至該第一小晶片； 基板，其具有第一表面及第二表面，該第一小晶片安置於該基板與該I/O IC晶粒之間，該基板具有基板電路系統，該基板電路系統在該晶片封裝組件內經由該第一RDL、該第一小晶片及該I/O IC晶粒以通信耦接至該功能IC晶粒之功能電路系統； 電路系統，其將該I/O IC晶粒之I/O電路系統直接連接至該基板電路系統，同時繞過該第一小晶片；及 介電填充層，其側向安置於該I/O IC晶粒及該功能IC晶粒周圍。
  13. 如請求項1或12之晶片封裝組件，其中該第一小晶片之第一小晶片電路系統進一步包含以下各者中之一或多者：實體層（PHY）電路系統、高頻寬記憶體電路系統、處理器、串列解串器（SerDes）、高速串列匯流排、類比至數位轉換器、數位至類比轉換器、視訊編碼解碼器電路系統、電至光轉換器、記憶體子系統、處理器子系統、快閃記憶體、高頻寬記憶體及功率調節/分配系統或光至電轉換器。
  14. 如請求項2或12之晶片封裝組件，其進一步包含： 第二RDL，其將該基板耦接至該第一小晶片之作用側。
  15. 如請求項2或12之晶片封裝組件，其中該第一小晶片進一步包含： 導電穿孔，其安置為穿過該第一小晶片，該導電穿孔將該第一小晶片之電路系統耦接至該第一RDL之第一RDL電路系統及該基板之該基板電路系統。
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