CN103021981A - 集成电路及制造方法 - Google Patents
集成电路及制造方法 Download PDFInfo
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Abstract
本发明揭示电路及制造电路的方法。所述电路的实施例包括具有侧的裸片,其中连接点位于所述侧上。电介质层具有第一侧、第二侧,及在所述第一侧与所述第二侧之间延伸的至少一个通孔,所述电介质层位于接近所述裸片的所述侧处。所述通孔电连接到所述连接点。导电层位于邻近于所述第一电介质层的所述第二侧处,其中所述导电层的至少一部分电连接到所述通孔。
Description
本专利申请案主张2011年9月23日申请的第61/538,365号美国临时专利申请案“使用模制和分配方法的永久载体和包封互连方法(PERMANENT CARRIER ANDPACKAGE INTERCONNECT METHOD USING MOLD AND DISTRIBUTEAPPROACH)”及2012年2月8日申请的第61/596,617号美国临时专利申请案“集成电路及制造方法(INTEGRATED CIRCUIT AND METHOD OF MAKING)”的优先权,其均以引用的方式全部并入本文中。
技术领域
背景技术
常规集成电路具有裸片,裸片为小型电路,其被电及/或机械地连接到引线框或其它连接机构。在所述裸片与所述引线框之间的电连接通常由连接在所述裸片上的导电衬垫与所述引线框上的导体之间的线接合组成。所述线接合非常小而且非常易损,因此施加到线接合的较小的力就能对其造成损害。因此,在处置具有与其相连的线接合的电路时必须非常小心。除了非常易损,还要花时间连接所述线接合,因此其增加了成本及制造集成电路的时间。
许多高速高频电路应用需要将裸片连接到引线框的短引线。短引线减少所述裸片受到电磁干扰的概率且其影响与所述引线相关联的寄生电感和电容。线接合相对较长,并增加所述裸片与集成电路的所述引线框之间的连接的寄生电容和电感。线接合还易于受到电磁干扰。
在常规裸片被连接到引线框之后,用包封剂包封所述集成电路。包封工艺通常是制造所述集成电路的最后或接近最后的阶段。包封剂防止污染物干扰所述集成电路。举例来说,包封剂防止水分损害所述裸片。包封剂还防止线接合受到损害。在集成电路被包封前,裸片、线接合和其它组件容易因为和污染物接触而失效。因此在制造工艺期间必须格外小心以防止集成电路在包封之前被损害。
发明内容
本文揭示集成电路及制造电路的方法。集成电路的一个实施例包括具有侧的裸片,其中连接点位于所述侧上。电介质层具有第一侧、第二侧,及在所述第一侧与所述第二侧之间延伸的至少一个第一通孔,所述电介质层附接到所述裸片的所述侧上,使得所述电介质层的第一侧位于邻近于所述裸片的所述侧处。导电层位于邻近于所述电介质层的所述第二侧处,且所述第一通孔被电连接在所述连接点与所述导电层之间。
附图说明
图1为集成电路的实施例的侧面剖视图。
图2为图1中的电路的印刷电路板的一部分的放大图。
图3为描述制造图1中的电路的方法的实施例的流程图。
图4为正处于制造工艺中且其中裸片已经被包封在里面的图1中的电路的侧面正视图。
图5为图4中的电路的仰视平面图。
图6为描述将第一电介质层附加到图1中的电路的方法的实施例的流程图。
图7为附着到牺牲载体的第一电介质层的侧面正视图。
图8为附加到图4中的电路的图7中的电介质层与牺牲载体的侧面正视图。
图9为牺牲载体被移除且其中通孔的孔形成在第一电介质层中的图8中的电路的侧面正视图。
图10为具有被施加到其中导电层被连接到通孔的第一电介质层的导电层的图9中的电路的侧面正视图。
图11为添加有第二电介质层的图10中的电路的侧面正视图。
图12为具有穿过第二电介质层而形成的通孔的图11中的电路的侧面正视图。
具体实施方式
本文揭示了集成电路(本文简称“电路”)和制造电路的方法。图1为电路100的侧面剖视图。电路100包括包封剂106、裸片108、印刷线路板110和连接机构112。以下更详细地描述用于制造电路100的方法的实施例。
包封剂106可为通常用于包封集成电路或电子装置的常规包封剂。在一些实施例中,包封剂106通过转印模制工艺来施加。包封剂106具有第一侧120和位于所述第一侧120对面的第二侧122。如下文更详细描述,大小经设计以接纳裸片108的孔隙124位于第一侧120中。在许多实施例中,包封剂106模制在裸片108周围,因此孔隙124为包封工艺期间在裸片108的位置处形成的包封剂106的凹陷部分。
裸片108可为通常在集成电路中使用的常规裸片。裸片108具有第一侧126及对面的第二侧128。裸片108的第一侧126与包封剂106的第一侧120一起形成大体上连续的平坦表面。电路及/或电子装置(未图示)可以常规方式位于裸片108中或裸片108上。举例来说,可将电子装置制造在第二侧128上。多个导电衬垫130位于第一侧126上。导电衬垫130用来将裸片108电连接到外部装置或导体。导电衬垫130相对于电路100的其它组件可为非常薄,然而,出于说明的目的,它们被展示为相当厚。
将印刷线路板110附着到裸片108的第一侧126,且还可将其附着到或制造到包封剂106的第一侧120。印刷线路板110有三层:第一电介质层134、导电层136和第二电介质层138。印刷线路板110可与电路100分开制造,且可作为完整的组合件被施加到裸片108及包封剂106。下文描述了两种制造方法。
印刷线路板110的放大视图展示于图2中。第一电介质层134具有第一侧140和第二侧142。第一侧140附接到或附着到裸片108的第一侧126(图1),且还可附接到或附着到包封剂106的第一侧120。导电层136可大体上与裸片中的重新分配层类似。导电层136包括用作迹线的导电材料144(例如铜)及位于导体迹线之间的不导电材料146。导电材料144可为金属,例如与在减性处理时使用的铜箔类似或相同的铜箔,或以半加性或全加性形式镀敷。铜箔的实例包括一个半到两个盎司的铜箔。在其它实施例中,导电材料144可为具有几个层的箔,例如铜/铝/铜箔。导电层136具有第一侧148及第二侧150,其中第一侧148附接到或附着到第一电介质层134的第二侧142。不导电材料146可为第一电介质层或者第二电介质层138的部分。第二电介质层138具有第一侧152和第二侧154,其中第一侧152附接到或附着到导电层136的第二侧150。第一电介质层134和第二电介质层138两者都可为通常在电路中使用的绝缘材料。
印刷线路板110用来电性地及/或机械地将裸片108连接到连接机构112。为了实现电连接,多个迹线和通孔可位于印刷线路板110内,以将裸片108电连接到连接机构112。如图1及2所示,第一电介质层134具有多个在第一侧140与第二侧142之间延伸的通孔156。通孔156将裸片108上的导电衬垫130电连接到印刷线路板110的导电层136内的导电材料144。导电层136通过导电材料144在特定位置为连接机构112提供导电点。在图1及2的实施例中,通孔158延伸穿过导电层136与第二电介质层138的第二侧154之间的第二电介质层138。注意,连接机构112电连接到通孔158。因此,连接机构112电连接到裸片108上的导电衬垫130。
连接机构112可包括多个电性地和机械地连接到多个导体162的焊球160。导体162可大体上类似于在半导体制造中使用的凸块下金属层。导体162电连接到通孔158。由此得出电连接在焊球160与裸片108上的导电衬垫130之间延伸。注意,焊球160和导体162为用来将通孔158连接到外部装置和其它装置的装置的实例,例如引脚或线接合,其可用来将通孔158电连接到外部装置。
已经描述了电路100的机构,现在将描述电路100的制造方法。参考图3的流程图300,其描述一种制造电路100的方法。以下将进一步描述其它制造方法。
电路100的制造从提供流程图300的步骤304处所描述的裸片108开始。裸片108为制造到晶片或衬底上的常规电路。裸片108可为一种通常在集成电路中使用的类型。裸片108可为完整的电路,这意味着不需要进一步的电路制造。然而,裸片108确实需要电连接到连接机构112,以便给裸片108供电,并发送和接收如下文所描述的信号。如上文所描述,裸片108具有用来将裸片108电连接到连接机构112的连接点或导电衬垫130。
如步骤306中所描述,用包封剂106来包封裸片108。被包封的裸片108展示于图4中,图4为裸片108及包封剂106的侧面、剖视正视图。图4中的包封电路100的仰视平面图展示于图5中。包封剂106可为制造集成电路时所使用的常规包封剂。在一些实施例中,使用转印模制技术来包封裸片108。在此制造阶段包封裸片108是独特的。在常规电路中,在电连接到连接件或其它连接装置之前,裸片是不被包封的。举例来说,在制造倒装芯片时,在印刷线路板被附加到裸片之前,包封过程是不会发生的。通过在电路100的此制造阶段包封裸片108,可在受损害的可能性较低的情况下处置或以其它方式操纵裸片108。被包封的裸片108也比较不可能被污染物损害。
在本文所描述的实施例中,除了第一侧126外整个裸片108都被包封。通过在制造期间的此点处包封除第一侧126之外的裸片108,裸片108得到保护,并且衬垫130为可接近的,以便将裸片108连接到连接机构112。如图4及5所示,包封剂106可延伸到裸片108的第一侧126之外,其使完成的电路100能够配合到较大的封装中。包封剂的第一边缘172和裸片108的第一边缘125间隔开距离170。包封剂106的第二边缘176和裸片108的第二边缘127隔开距离174,如图5中所示。距离170、174决定包封剂106的第一侧120的大小,其可大体上为平面的。裸片108可以裸片108的第一侧126及包封剂106的第一侧120形成大体上平面且连续的表面的方式位于包封剂106中。
包封剂106可以不同的方法施加到裸片108。举例来说,液体包封剂可模制在裸片108上并以常规方式固化。在其它实施例中,固体包封剂可用位于其中的孔隙124来形成。裸片108可固定在孔隙124,使得裸片108被包封剂106有效地包封。在其它实施例中,包封剂106与印刷线路板110或印刷线路板110内的组件的固化同时而固化。在此些实施例中,包封剂106可在此制造阶段被固化到B阶段或胶状状态。在印刷线路板110附接到裸片108及包封剂106之后,包封剂106及印刷线路板110中的组件可接着同时被固化。所述同时固化可增强印刷线路板110与包封剂106之间的接合。举例来说,包封剂106和第一电介质层134能够在其胶状状态下一起流动,并接着被一起充分固化。
下文将描述将印刷线路板110施加到裸片108的几个不同的实施例。注意,印刷线路板110代替常规线接合。因此,本文所描述的电路100的实施例中没有一个实施例需要裸片108与连接机构112之间的线接合或类似物。因此,印刷线路板110的所有实施例使裸片108与连接机构112之间的距离能够非常短,这减少了与裸片108和连接机构112之间的电连接相关联的寄生电容和电感。
将印刷线路板110施加到电路100的第一个实施例以将第一电介质层134施加到电路开始,如流程图300的步骤308处所描述。在图6的流程图350中更详细地描述第一电介质层134的施加。参考图7,其展示附着到牺牲载体177的第一电介质层134,如流程图350的步骤352中所描述。第一电介质层134可通过常规低温真空层压工艺而层压到牺牲载体177。第一电介质层134可为非纤维电介质材料,例如由日本的味之素(Ajinomoto)精细科技公司和美国新泽西州李福特(Fort Lee)的味之素北美有限公司生产的味之素积聚膜(ABF)。第一电介质层134可具有十到五十微米之间的厚度。在第一电介质层134中使用的材料在被固化之前具有较低的粘度。为了保持第一电介质层134在其处于具有较低粘度的状态时不从牺牲层177滑落,可将第一电介质层134固化到其中第一电介质层134具有胶状粘度的B阶段。如下文所描述,此固化使第一电介质层134能够通过牺牲载体177输送,并附着到包封剂105及裸片108。
牺牲载体177可为金属,例如铜箔。在一些实施例中,牺牲载体177为一个半到两个盎司的铜箔。在其它实施例中,牺牲载体177可为具有几个层的箔,例如铜/铝/铜箔。牺牲载体177具有第一侧178及第二侧179,其中第一侧178附着到或位于邻近于第一电介质层134的第二侧142处。牺牲载体177用于通过形成用以支撑第一电介质层134的刚性载体而将第一电介质层施加到包封剂106及裸片108,使得其能够被压贴着包封剂106和裸片108。
在此制造阶段,第一电介质层134附着到牺牲载体177。可接着通过使用牺牲载体177来输送或处置第一电介质层134,这降低了在处置期间对所述第一电介质层134造成损害的可能性。第一电介质层134的胶状状态使其能够被施加到电路100,如流程图350的步骤354处所描述,这产生如图8中所展示的电路100。举例来说,裸片108和包封剂106可被压贴到第一电介质层134上。注意,在一些实施例中,一大片第一电介质层附着到多个裸片(其在以后的制造阶段期间被单一化)。
第一电介质层134的部分固化胶状状态使其能够容易地附着到或位于邻近于所有裸片108和包封剂106处,并降低或消除表面之间的孔隙的可能性。更确切地说,如果包封剂106处于胶状状态,那么第一电介质层134和包封剂106可一起流动以更好的粘合。导电衬垫130可被嵌入胶状化的电介质层134中。如流程图350的步骤356处所描述,第一电介质层134和包封剂106可接着被同时固化。
在制造过程中的此点处,电路100具有与附着到裸片108及/或包封剂106的第一电介质层134一起被固化的第一电介质层134和包封剂106。如流程图350的步骤358中所描述,接着移除牺牲载体177。在一些实施例中,通过常规的蚀刻工艺来蚀刻掉牺牲载体177。所得电路100展示于图9中。如图所示,电路100具有附加到其上的第一电介质层134,且牺牲层177已经被移除。如在图9中进一步展示,用于通孔156的孔形成到接近导电衬垫130的第一电介质层134中,如流程图350的步骤360中所描述。在一个实施例中,使用激光来形成所述孔。在其它实施例中,钻孔或使用化学药品来形成用于通孔156的孔。
镀敷或以其它方式用导电材料填充用于通孔156的所述孔,如流程图350的步骤362中所描述。举例来说,可将镀敷材料施加到第一电介质层134,以在通孔156中形成导电路径。也可使用其它方法来提供导电材料以形成通孔156。举例来说,在一些实施例中,在将导电层136施加到第一电介质层134时,形成用于通孔156的导电材料。
将导电层136施加到第一电介质层,如图3的流程图300的步骤310中所描述。导电层136可以类似于将重新分配层施加到集成电路的方式来施加。举例来说,可将抗蚀剂(未图示)施加到第一电介质层134的第二侧142。注意,如果用于通孔156的所述孔尚未被镀敷,那么就不可在接近所述孔处施加抗蚀剂。可接着通过常规技术(例如镀敷)将导电层136施加到第一电介质层134的第二侧142。图2的导电材料144将附着到第一电介质层134的不存在抗蚀剂的位置处(其可包括用于通孔156的所述孔)。所得电路100展示于图10中,其展示导电层136中被连接到通孔156的导电材料144。
在一些实施例中,如图10所展示的电路100是完整的。电路100是实用的,且可通过印刷线路板110连接到其它装置。举例来说,可将导体连接到导电层136,以便将电路100电连接到其它组件。
在电路100的其它实施例中,将第二电介质层138附加到导电层136,如流程图300的步骤312中所描述且如图11中所示。如上文所描述,第二电介质层138具有第一侧152和第二侧154,其中第一侧152附着到或附接到导电层136。第二电介质层138可与第一电介质层134大体上为相同的材料。第二电介质层138用来保护导电层136在处置期间不受损害,并不受可使导电层134短路或以其它方式损害导电层134的碎屑或其它物质的影响。另外,第二电介质层138用来支撑连接机构112。
在第二电介质层138中形成通孔158,如流程图300的步骤314中所描述且如图12所示。通孔158在第二电介质层138的第一侧152与第二侧154之间延伸。通过穿过第二电介质层138形成孔来制造通孔158,其中所述孔接触导电层136的导电材料144的特定部分。所述孔可以与形成在第一电介质层134中的孔相同的方式形成以制造通孔156。同样,以与形成通孔156的方式类似的方式,使用导电材料填充或镀敷所述孔以形成通孔158。
电路100现在具有经包封的裸片108,其具有从裸片108到第二电介质层138的第二侧154的电连接。连接机构112现在可附加到第二电介质材料138的第二侧154,如流程图300的步骤316中所描述且如图1中所示。连接机构112电性地及/或机械地将电路100连接到其它装置。举例来说,连接机构112可提供去往和来自裸片108的输入和输出信号。连接机构112还可使电路100能够以物理方式附接到衬底(未图示),例如印刷电路板或其它物理结构。
如上文简要描述,连接机构112可包括多个附接到第二电介质层138的第二侧154的导体162。导体162电连接到通孔158,以提供到裸片108的电连接。导体162可为常规金属,例如通常用来支撑焊球160的凸块下金属层。焊球160可以常规方式附接到导体162。
相比于常规集成电路,电路100具有许多优点。举例来说,电路100在制造工艺中被较早包封。因此,电路100可在剩余的生产工艺期间以较低的受损概率被处置和操纵。此外,电路100在生产期间比较不易于受到污染物的损害。
在电方面,相比于常规集成电路,电路100具有许多好处。电路100不需要任何线接合。因此,电路100不易于增加与线接合相关联的寄生电容和电感。此外,导电层136使裸片108上的导电衬垫130与连接机构112之间的引线长度非常短。短距离减少了电路100易于受到的电磁干扰。因此得出电路100更适于在高频、高速及低功率应用中操作。
已经描述了制造电路100的一些实施例,现在将描述其它实施例。在一些实施例中,在不使用牺牲载体177的情况下,直接将第一电介质层134施加到裸片108和包封剂106(图7)。在此应用中,可定位电路100,使得包封剂106的第一侧120和裸片108的第一侧126面朝上。可接着将第一电介质层134施加到包封剂106的第一表面120和裸片108的第一表面126。可接着固化第一电介质层134,其中所述固化也可同时固化包封剂106。电路100的制造可从如上文所描述的流程图350的步骤360继续。
在制造工艺的另一实施例中,直接将第一电介质层134附着到导电层136,而不是附着到牺牲载体177(图7)。在此实施例中不需要移除牺牲载体177。而是,导电层136及(更确切地说)导电层136的导电材料144用作第一电介质层134的载体。可接着蚀刻导电材料144以形成导电层136。可如上文所描述而形成通孔156。也可镀敷通孔156,使得其与导电层136的导电材料144电连接。
在其它实施例中,将散热件与包封剂106一起使用或者作为包封剂106的替代品而使用。举例来说,裸片108在包封之前可位于散热件中。或者,裸片108可位于代替包封的散热件中。
已经在本文详细描述了尽管本发明的说明性和目前优选的实施例,但应理解,可以其它各种方式来体现和使用本发明的概念,且所附权利要求书既定被解释为包括现有技术所限制的范围以外的此类变化。
Claims (20)
1.一种电路,其包括:
具有侧的裸片,其中连接点位于所述侧上;
第一电介质层,其具有第一侧、第二侧,及在所述第一侧与所述第二侧之间延伸的至少一个第一通孔,其中所述第一电介质层的所述第一侧位于接近所述裸片的所述侧处,且其中所述第一通孔电连接到所述连接点;及
导电层,其具有第一侧和第二侧,其中所述第一侧位于邻近于所述第一电介质层的所述第二侧处,所述导电层的至少一部分电连接到所述第一通孔。
2.根据权利要求1所述的电路,其中所述第一电介质层附着到所述裸片的所述侧。
3.根据权利要求1所述的电路,且其进一步包括电连接到所述导电层的至少一部分的连接机构。
4.根据权利要求1所述的电路,其中所述裸片的至少一部分由包封剂包封。
5.根据权利要求4所述的电路,其中所述第一电介质层的至少一部分接触所述包封剂。
6.根据权利要求1所述的电路,且其进一步包括具有第一侧和第二侧的第二电介质层,其中所述第一侧位于邻近于所述导电层处,其中所述第二电介质层具有在所述第一侧和第二侧之间延伸的第二通孔,且其中所述第二通孔电连接到所述导电层。
7.根据权利要求6所述的电路,且其进一步包括电连接到所述第二通孔处的连接机构。
8.根据权利要求7所述的电路,其中所述连接机构机械地连接到所述第二电介质层。
9.一种制造电路的方法,所述方法包括:
提供裸片,所述裸片具有侧,其中连接点位于所述侧上;
将第一电介质层附加到所述裸片的所述第一侧,所述第一电介质层具有第一侧和第二侧,其中将所述第一电介质层的所述第一侧附加到所述裸片的所述侧;及
形成穿过所述第一侧与所述第二侧之间的所述第一电介质层的第一通孔,其中所述第一通孔电连接到所述连接点。
10.根据权利要求9所述的方法,且其进一步包括在将所述第一电介质层附加到所述裸片的所述侧之前包封所述裸片,其中所述包封包括大体上包封除了所述侧以外的所述裸片。
11.根据权利要求9所述的方法,且其进一步包括将所述裸片定位在接近散热件处。
12.根据权利要求9所述的方法,其中将所述第一电介质层附加到处于未固化状态的所述裸片,且进一步包括:
将未固化的包封剂施加到所述裸片;及
同时固化所述包封剂和所述第一电介质层。
13.根据权利要求9所述的方法,其中所述第一电介质层具有附加到所述第二侧的导电层,且所述方法进一步包括将所述导电层电连接到所述第一通孔。
14.根据权利要求13所述的方法,且其进一步包括:
将第二电介质层附加到所述导电层,所述第二电介质层具有第一侧和第二侧,其中所述第二电介质层的所述第一侧位于邻近于所述导电层处;及
在所述导电层与所述第二电介质层的所述第二侧之间形成第二通孔。
15.根据权利要求14所述的方法,且其进一步包括将连接机构附加到所述第二电介质层的所述第二侧,所述连接机构电连接到所述第二通孔。
16.根据权利要求9所述的方法,其中所述附加第一电介质层包括将第一电介质材料附加到载体,以及将具有所述载体的所述电介质材料施加到所述裸片的所述侧。
17.根据权利要求16所述的方法,且其进一步包括移除所述载体。
18.一种制造电路的方法,所述方法包括:
用包封剂包封除裸片的第一侧以外的所述裸片;及
在所述包封之后,将电介质衬底附加到所述裸片和所述包封剂。
19.根据权利要求18所述的方法,且其进一步包括使用延伸穿过所述电介质衬底的导电材料将所述裸片电连接到连接机构。
20.根据权利要求19所述的方法,其中所述电连接包括在将所述电介质衬底附接到所述裸片和所述包封剂之后将导电层附接到所述电介质衬底的一侧。
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US20130075890A1 (en) | 2013-03-28 |
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