CN102867850A - 具有高k栅电介质和金属栅电极的半导体器件 - Google Patents

具有高k栅电介质和金属栅电极的半导体器件 Download PDF

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CN102867850A
CN102867850A CN2012103621315A CN201210362131A CN102867850A CN 102867850 A CN102867850 A CN 102867850A CN 2012103621315 A CN2012103621315 A CN 2012103621315A CN 201210362131 A CN201210362131 A CN 201210362131A CN 102867850 A CN102867850 A CN 102867850A
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oxide
gate electrode
semiconductor device
metal
aluminide
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M.多茨
J.卡瓦里罗斯
M.梅茨
J.布拉斯克
S.达塔
R.曹
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Intel Corp
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Abstract

本发明的名称是“具有高k栅电介质和金属栅电极的半导体器件”。描述了一种半导体器件，其包括栅电介质和包含铝化物的金属栅电极。

Description

具有高k栅电介质和金属栅电极的半导体器件
本申请是申请日为2005年7月8日、申请号为200580024431.0、发明名称为“具有高k栅电介质和金属栅电极的半导体器件”的专利申请的分案申请。
技术领域
本发明涉及半导体器件，具体地说，涉及包括高k栅电介质和金属栅电极的那些半导体器件。
背景技术
具有由二氧化硅制成的非常薄的栅电介质的MOS场效应晶体管可能会经历不能接受的栅极漏电流。由特定高k介电材料替代二氧化硅形成栅电介质可以减小栅泄漏。然而，由于这种电介质可能与多晶硅不兼容，在包括高k栅电介质的器件中使用金属栅电极可能会令人满意。具有低于4.3eV的功函数的某些金属可以被用来制作用于NMOS晶体管的金属栅电极。然而，那些金属在40O℃以上的温度可能会热不稳定，导致它们与高k栅电介质不利地反应。
因此，存在对具有高k栅电介质以及具有低于4.3eV的功函数的在400℃热稳定的NMOS金属栅电极的半导体器件的需要。本发明提供这种半导体器件。
发明内容
根据第一实施例，提供了一种半导体器件，包括：
高k栅电介质，所述高k栅电介质包括从由氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽以及铌酸铅锌构成的组中选择的材料；
金属栅电极，其形成在栅电介质上，其包括具有成分MxAly的铝化物，其中M是过渡金属；
形成在铝化物上的填充金属；以及
PMOS金属栅电极，其布置在所述高k栅电介质上，所述PMOS金属栅电极不包括铝化物。
根据第二实施例，提供了一种半导体器件，包括：
高k栅电介质，所述高k栅电介质包括从由氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽以及铌酸铅锌构成的组中选择的材料；
NMOS金属栅电极，其包括具有成分MxAly的铝化物，其中M为过渡金属；和
PMOS金属栅电极，其布置在所述高k栅电介质上，所述PMOS金属栅电极不包括铝化物。
根据第三实施例，提供了一种CMOS半导体器件，包括：
高k栅电介质，所述高k栅电介质包括从由氧化铪、氧化锆以及氧化铝构成的组中选择的材料；
NMOS金属栅电极，其包括具有成分MxAly的铝化物，其中M为过渡金属；以及
PMOS金属栅电极，其布置在所述高k栅电介质上，所述PMOS金属栅电极不包括铝化物。
附图说明
图1a-1i表示当实施可以被用来制作本发明的半导体器件的替换栅方法的实施例时可以形成的结构的截面。
在这些图中示出的特征并不意味着按比例绘制。
具体实施方式
描述半导体器件。该半导体器件包括栅电介质和包括铝化物的金属栅电极。在以下描述中，许多细节被提出以提供对本发明的详尽的理解。然而，对本领域的技术人员来说显而易见的是，可以以除了在这里明确描述的那些之外的许多方式实施本发明。因此本发明并不被以下所公开的特定细节所限制。
本发明的一个实施例包括其上形成了包括铝化物的NMOS金属栅电极的高k栅电介质。该高k栅电介质可以包括氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽、以及铌酸铅锌。特别优选的是氧化铪、氧化锆、以及氧化铝。尽管在这里描述了可以用来形成这种高k栅电介质的材料的几个实例，但是也可以由其它用来减小栅泄漏的材料制成该电介质。
用来制成NMOS金属栅电极的铝化物是有序的金属间合金。这种合金的原子排列不同于常规金属合金的原子排列。与常规的铝合金不同，当保持在临界排序温度以下时，在铝化物中的合金原子是周期性排列的，形成超晶格晶体结构。在与常规的铝合金相比较时，铝化物可以表现出增强的结构稳定性和对高温变形的抵抗力。
在本发明的半导体器件的优选实施例中，该铝化物具有成分MxAly，其中M是过渡金属，并且x与y的比率代表在该铝化物中包含的该过渡金属与铝的相对原子百分比。具有该成分的铝化物可以例如包括锆、钨、钽、铪、钛、以及其它过渡金属，其当与铝结合时产生具有期望的功函数和热稳定性的成分。被包括在本发明的半导体中的铝化物也可以包括被束缚在具有铝合金的超晶格晶体结构内的多种过渡金属，例如利用相对少量的硼或镁掺杂的包括铝的合金。
当用来形成NMOS金属栅电极时，这些铝化物优选具有成分MxAly，其中x在1和4之间并且y在1和4之间。用于制作NMOS金属栅电极的特别优选的铝化物包括ZrAl、ZrAl2、ZrAl3、WAl4、TaAl、HfAl、TiAl、TiAl2、TiAl3、以及Ti3Al。所得到的NMOS金属栅电极可以具有小于4.3eV的功函数，并且其优选在大约3.9eV和大约4.3eV之间，并且更优选在大约4.0eV和大约4.2eV之间。
用来形成NMOS金属栅电极的铝化物应当足够厚以确保在它上面形成的任何材料将不显著影响它的功函数。优选地，这种铝化物厚度在大约20埃和大约2,000埃之间，并且更优选在大约100埃和大约300埃之间。这种NMOS金属栅电极优选在400℃是热稳定的。
当本发明的半导体是CMOS器件时，除了包括铝化物的NMOS金属栅电极之外，它还可以包括不包含铝化物的PMOS金属栅电极。这种PMOS金属栅电极可以被形成在高k栅电介质上，并且可以包括p型金属，例如钌、钯、铂、钴、镍、或导电的金属氧化物，例如氧化钌。尽管在这里描述了可以被用来形成p型金属层的金属的几个实例，但是这些层可以由许多其它材料制成。
当用来形成PMOS金属栅电极时，这种p型金属优选具有在大约4.9eV和大约5.2eV之间的功函数。它们的厚度优选在大约20埃和大约2,000埃之间，并且更优选在大约100埃和大约300埃之间。类似于用于制作NMOS金属栅电极的铝化物，用来制作PMOS金属栅电极的p型金属应当在400℃是热稳定的。
图1a-1i示出当实施可以被用来制作本发明的半导体器件的替换栅方法的实施例时可以形成的结构。图1a表示在制作CMOS器件时可以形成的中间结构。该结构包括衬底100的第一部分101和第二部分102。隔离区103将第一部分101和第二部分102分开。第一多晶硅层104被形成在介电层105之上，并且第二多晶硅层106被形成在介电层107之上。第一多晶硅层104用侧壁隔离物108和109来托架，并且第二多晶硅层106用侧壁隔离物110和111来托架。介电层112分开层104和106。
衬底100可以包括可以用作基础的任何材料，半导体器件可以建立在该基础上。隔离区103可以包括二氧化硅、或可以分开该晶体管的有源区的其它材料。介电层105和107均可以包括二氧化硅、或可以使衬底与其它物质绝缘的其它材料。在该实施例中，第一多晶硅层104是掺杂的n型，并且第二多晶硅层106是掺杂的p型。第一和第二多晶硅层104和106可以是在大约100埃和大约2,000埃之间厚，并且优选是在大约500埃和大约1,600埃之间厚。隔离物108、109、110和111优选包括氮化硅，而介电层112可以包括二氧化硅或低k材料。
可以利用常规工艺步骤、材料以及设备形成图1a的结构，这对本领域的技术人员来说是显而易见的。如所示，可以例如通过常规的化学机械抛光(“CMP”)步骤向后抛光介电层112以暴露第一和第二多晶硅层104和106。尽管没有示出，但是图1a的结构可以包括许多其它的特征(例如，氮化硅刻蚀停层、源区和漏区、以及一个或多个缓冲层)，其可以利用常规工艺形成。
当利用常规的离子注入和退火工艺形成源区和漏区时，可以期望在多晶硅层104和106上形成硬掩模-以及在该硬掩模上的刻蚀停层-以在利用硅化物覆盖该源区和漏区时保护层104和106。这种硬掩模可以包括氮化硅。这种刻蚀停层可以包括硅、氧化物(例如，二氧化硅或二氧化铪)、或碳化物(例如碳化硅)。
当抛光介电层112时，可以从层104和106的表面抛光这种刻蚀停层和氮化硅硬掩模-同时那些层将通过该工艺中的该阶段来达到它们的目的。图1a表示这样的结构：其中可以预先形成在层104和106上的任何硬掩模或刻蚀停层已经从那些层的表面被除去。当利用离子注入工艺形成源区和漏区时，可以在该源区和漏区被注入的同时掺杂层104和106。
在形成图1a的结构之后，第一多晶硅层104被除去。在优选实施例中，该层通过下述来除去：在足够的温度将它暴露于按体积包括在大约2％和大约30％之间的氢氧化铵的水溶液足够的时间以基本上除去层104的全部而不除去相当大量的第二多晶硅层106。在该暴露步骤期间，可以期望施加频率在大约10KHz和大约2,000KHz之间的声能，同时在大约1和大约10瓦/cm2之间消耗。作为实例，如果n型多晶硅层104为大约1,350埃厚，那么它可以通过下述来去除：在大约25℃将它暴露于在去离子水中按体积包括大约15％的氢氧化铵的溶液大约30分钟同时施加在大约1,000KHz的声能-以大约5瓦/cm2消耗。
在除去第一多晶硅层104后，介电层105被除去。当介电层105包括二氧化硅时，可以利用对二氧化硅有选择性的蚀刻工艺除去它。这种蚀刻工艺可以包括将层105暴露于在去离子水中包括大约百分之一的HF的溶液。应当限制层105被暴露的时间，因为用来除去该层的刻蚀工艺也可以除去部分介电层112。考虑到上述，如果百分之一的HF基溶液被用于除去层105，那么该器件优选应当暴露于该溶液少于大约60秒，并且更优选为大约30秒或更少。如图1b中所示，介电层105的去除在介电层112内形成了位于侧壁隔离物108和109之间的沟槽113。
在除去介电层105之后，在沟槽113内以及衬底100之上形成可以包括以上所指定的材料中的一种的高k栅电介质115。可以利用常规的原子层化学汽相沉积(“CVD”)工艺在衬底100上形成高k栅电介质115。在这种工艺中，金属氧化物前体(例如金属氯化物)和蒸汽可以以选择的流速馈送到CVD反应器中，然后其在选择的温度和压力下工作以在衬底100和高k栅电介质115之间形成原子平滑的界面。该CVD反应器应当运转得足够长以形成具有期望厚度的电介质。在大多数应用中，高k栅电介质115应当为小于大约60埃厚，并且更优选为在大约5埃和大约40埃之间厚。
如图1C中所示，当利用原子层CVD工艺形成高k栅电介质115时，该电介质除了形成在沟槽113的底部之上外还将形成在该沟槽的侧上，并且将形成在介电层112上。如果高k栅电介质115包括氧化物，那么它可以在任意表面位置显现氧空位以及不可接受的杂质能级，取决于用来制作它的工艺。在沉积电介质115之后，可以期望从该电介质除去杂质，并且氧化它以形成具有几乎理想化的金属：氧化学计量关系的电介质。
为从高k栅电介质115除去杂质并且增加该电介质的氧含量，可以将高k栅电介质115暴露于按体积包括在大约2％和大约30％之间的过氧化氢的水溶液。在特别优选的实施例中，高k栅电介质115在大约25℃的温度暴露于按体积包括大约6.7％的H2O2的水溶液大约十分钟。在该暴露步骤期间，可以期望施加在大约1,000KHz的频率的声能，同时以大约5瓦/cm2消耗。
在示出的实施例中，第一金属层116被直接形成在高k栅电介质115上以形成图1d的结构。类似于高k栅电介质115，第一金属层116的部分给沟槽113做衬里，同时该层的部分溢出到介电层112上。如以上所示，第一金属层116包括铝化物，优选为具有成分MxAly的一种，其中M是过渡金属。可以利用常规的物理汽相沉积(“PVD”)工艺在高k栅电介质115上形成这种铝化物。在这种工艺中，合金靶(或多个纯靶)可以被溅射到高k栅电介质115上。可替换地，可以利用采用多个前体的CVD工艺形成铝化物。另外，可以利用纳米层叠(nanolaminate)技术(其依靠PVD、CVD、或原子层CVD工艺)来交替沉积超薄的铝和过渡金属层，其将以期望的方式结晶化以形成铝化物116。
在该实施例中，在高k栅电介质115上形成第一金属层116之后，在第一金属层116上形成第二金属层121。如图1e所示，第二金属层121填充沟槽113的剩余部分并且覆盖介电层112。第二金属层121优选包括可以容易地被抛光的材料，并且优选利用常规的金属沉积工艺被沉积在整个器件之上。这种填充金属可以包括氮化钛、钨、钛、铝、钽、氮化钽、钴、铜、镍、或任何其它金属，其可以被抛光并且其可以令人满意地填充沟槽113。当填充金属覆盖第一金属层116时，第一金属层116优选为在大约20埃和大约300埃之间厚，并且更优选为在大约25埃和大约200埃之间厚。当填充金属没有覆盖铝化物116时，例如当该铝化物完全填充沟槽113时，第一金属层116可以是高达2,000埃厚。如上面所提到的，第一金属层116优选具有在大约3.9eV和大约4.3eV之间的功函数。
在形成图1e的结构之后，从以上介电层112除去第二金属层121、第一金属层116、以及高k栅电介质115以形成图1f的结构。可以施加CMP步骤以从以上介电层112除去那些材料。可替换地，可以利用CMP步骤除去第二金属层121，而施加随后的干法刻蚀步骤(以及，任选地，附加的湿法腐蚀步骤)从以上介电层112除去第一金属层116和高k栅电介质115。
在第二金属层121之后，第一金属层116和高k栅电介质115被从以上介电层112除去，p型多晶硅层106被除去。可以通过在足够的温度(例如在大约60℃和大约90℃之间)将其暴露于在去离子水中按体积包括在大约20和大约30％之间的TMAH的溶液足够的时间，同时施加声能来对第二金属层121选择性地除去层106。
在除去第二多晶硅层106之后，例如通过利用被用来除去介电层105的相同工艺除去介电层107。如图1g所示，除去介电层107形成沟槽114。在除去该介电层之后，在沟槽114内以及在介电层112上形成高k栅电介质117。用来形成高k栅电介质115的同样的工艺步骤和材料可以被用来形成高k栅电介质117。
在该实施例中，然后在高k栅电介质117上沉积第三金属层120。第三金属层120可以包括以上所确定的p型金属中的一种，并且可以利用常规的PVD或CVD工艺形成在高k栅电介质117上。在该实施例中，第三金属层120优选为在大约20埃和大约300埃之间厚，并且更优选为在大约25埃和大约200埃之间厚。第三金属层120可以具有在大约4.9eV和大约5.2eV之间的功函数。
在高k栅电介质117上形成第三金属层120之后，可以在第三金属层120上形成第四金属层118，例如第二填充金属，以形成图1h的结构。用来形成第二金属层121的同样的工艺步骤和材料可以被用来形成第四金属层118。然后可以除去第四金属层118、第三金属层120和高k栅电介质117的覆盖介电层112的部分以形成图1i的结构。被用来从以上介电层112除去第一填充金属121、铝化物116和高k栅电介质115的同样的CMP和/或刻蚀步骤可以被用来从以上介电层112除去第二填充金属118、第三金属层120和高k栅电介质117。
在从以上介电层112除去第四金属层118、第三金属层120和高k栅电介质117之后，可以利用常规沉积工艺在所得到的结构上沉积覆盖介电层(未示出)。在这种覆盖介电层的沉积之后、用来完成该器件的工艺步骤，例如形成该器件的接触、金属互连、以及钝化层，是本领域的技术人员所公知的，并且在这里将不再描述。
本发明的半导体器件包括NMOS金属栅电极，其具有低于4.3eV的功函数并且在400℃是热稳定的。这种金属栅电极可以给NMOS晶体管提供结构和温度稳定性特性，其使它适合于半导体器件的高容量制造。
尽管前述的描述已经说明了可以用来形成本发明的半导体器件的特定材料，但是本领域的技术人员将理解的是可以进行多种修改和替代。因此，所有这些修改、变型、替代以及添加旨在被认为落入如所附权利要求所限定的本发明的精神和范围之内。

Claims (18)

1.一种半导体器件，包括：
高k栅电介质，所述高k栅电介质包括从由氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽以及铌酸铅锌构成的组中选择的材料；
金属栅电极，其形成在栅电介质上，其包括具有成分MxAly的铝化物，其中M是过渡金属；
形成在铝化物上的填充金属；以及
PMOS金属栅电极，其布置在所述高k栅电介质上，所述PMOS金属栅电极不包括铝化物。
2.如权利要求1所述的半导体器件，其中M包括从由锆、钨、钽、铪和钛构成的组中选择的元素。
3.如权利要求1所述的半导体器件，其中金属栅电极具有低于4.3eV的功函数。
4.如权利要求1所述的半导体器件，其中金属栅电极在400℃是热稳定的。
5.一种半导体器件，包括：
高k栅电介质，所述高k栅电介质包括从由氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽以及铌酸铅锌构成的组中选择的材料；
NMOS金属栅电极，其包括具有成分MxAly的铝化物，其中M为过渡金属；和
PMOS金属栅电极，其布置在所述高k栅电介质上，所述PMOS金属栅电极不包括铝化物。
6.如权利要求5所述的半导体器件，其中：
M包括从由锆、钨、钽、铪和钛构成的组中选择的元素。
7.如权利要求5所述的半导体器件，其中NMOS金属栅电极具有在3.9eV和4.3eV之间的功函数，并且在400℃是热稳定的。
8.如权利要求5所述的半导体器件，其中NMOS金属栅电极进一步包括形成在铝化物上的填充金属。
9.如权利要求8所述的半导体器件，其中填充金属是从由氮化钛、钨、钛、铝、钽、氮化钽、钴、铜以及镍构成的组中选择的。
10.一种CMOS半导体器件，包括：
高k栅电介质，所述高k栅电介质包括从由氧化铪、氧化锆以及氧化铝构成的组中选择的材料；
NMOS金属栅电极，其包括具有成分MxAly的铝化物，其中M为过渡金属；以及
PMOS金属栅电极，其布置在所述高k栅电介质上，所述PMOS金属栅电极不包括铝化物。
11.如权利要求10所述的CMOS半导体器件，其中：
M包括从由锆、钨、钽、铪和钛构成的组中选择的元素；以及
PMOS金属栅电极包括从由钌、钯、铂、钴、镍以及导电的金属氧化物构成的组中选择的材料。
12.如权利要求10所述的CMOS半导体器件，其中NMOS金属栅电极具有在3.9eV和4.3eV之间的功函数，并且PMOS金属栅电极具有在4.9eV和5.2eV之间的功函数。
13.如权利要求10所述的CMOS半导体器件，其中铝化物具有成分MxAly，其中M是过渡金属，x在1和4之间并且y在1和4之间。
14.如权利要求13所述的CMOS半导体器件，其中铝化物是从由ZrAl、ZrAl2、ZrAl3、WAl4、TaAl、HfAl、TiAl、TiAl2、TiAl3以及Ti3Al构成的组中选择的。
15.如权利要求10所述的CMOS半导体器件，其中NMOS金属栅电极进一步包括形成在铝化物上的填充金属。
16.如权利要求15所述的CMOS半导体器件，其中填充金属是从由氮化钛、钨、钛、铝、钽、氮化钽、钴、铜以及镍构成的组中选择的。
17.如权利要求10所述的CMOS半导体器件，其中：
高k栅电介质是利用原子层化学汽相沉积工艺形成的，并且厚度在5埃和40埃之间，以及
铝化物的厚度在100埃和300埃之间。
18.如权利要求10所述的CMOS半导体器件，其中NMOS金属栅电极和PMOS金属栅电极在400℃都是热稳定的。
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